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www.renesas.com all information contained in these materials, including products and product specifications, represents information on the product at the ti me of publication and is subject to change by renesas technology corp. without notice. please review the latest information published by renesas technology corp. through various means, including the renesas technology corp. website (http://www.renesas.com). rej09b0244-0300 16 r8c/24 group , r8c/25 group hardware manual renesas 16-bit single-chip mcu r8c family / r8c/2x series rev.3.00 revision date: feb 29, 2008 free datasheet http:///
1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. 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general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. free datasheet http:///
how to use this manual 1. purpose and target readers this manual is designed to provide the user with an understanding of the hardwa re functions and electrical characteristics of the mcu. it is intended for users de signing application systems incorporating the mcu. a basic knowledge of electric circuits, logi cal circuits, and mcus is necessa ry in order to use this manual. the manual comprises an overview of the product; descriptions of the cpu, system control functions, peripheral functions, and electrical charac teristics; and usage notes. particular attention should be paid to the precautio nary notes when using the manual. these notes occur within the body of the text, at the end of each section, and in the usage notes section. the revision history summarizes the loca tions of revisions and additions. it does not list all revisions. refer to the text of the manual for details. the following documents apply to the r8c/24 group, r8c/25 group . make sure to refer to the latest versions of these documents. the newest versions of the documents listed may be obtained from the renesas technology web site. document type description document title document no. datasheet hardware overview and elec trical characteristics r8c/24 group, r8c/25 group datasheet rej03b0117 hardware manual hardware specifications (pin assignments, memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description note: refer to the applic ation notes for details on using peripheral functions. r8c/24 group, r8c/25 group hardware manual this hardware manual software manual description of cpu instruction set r8c/tiny series software manual rej09b0001 application note information on using peripheral functions and application examples sample programs information on writing programs in assembly language and c available from renesas technology web site. renesas technical update product specifications, updates on documents, etc. free datasheet http:///
2. notation of numbers and symbols the notation conventions for register na mes, bit names, numbers, and symbols used in this manual are described below. (1) register names, bit names, and pin names registers, bits, and pins are referred to in the text by symbols. the symbol is accompanied by the word ?register,? ?bit,? or ?pin? to distinguish the three categories. examples the pm03 bit in the pm0 register p3_5 pin, vcc pin (2) notation of numbers the indication ?b? is appended to numeric values given in binary format. however, nothing is appended to the values of single bits. the indication ?h? is appended to numeric values given in hexadecimal format. nothing is appended to numeric values given in decimal format. examples binary: 11b hexadecimal: efa0h decimal: 1234 free datasheet http:///
3. register notation the symbols and terms used in register diagrams are described below. *1 blank: set to 0 or 1 acco rding to the application. 0: set to 0. 1: set to 1. x: nothing is assigned. *2 rw: read and write. ro: read only. wo: write only. ? : nothing is assigned. *3 ? reserved bit reserved bit. set to specified value. *4 ? nothing is assigned nothing is assigned to the bit. as the bit may be used for future functions, if necessary, set to 0. ? do not set to a value operation is not guaranteed when a value is set. ? function varies according to the operating mode. the function of the bit varies with the peripheral functi on mode. refer to the regist er diagram for information on the individual modes. xxx register symbol address after reset xxx xxx 00h bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 xxx bits 1 0: xxx 0 1: xxx 1 0: do not set. 1 1: xxx b1 b0 xxx1 xxx0 xxx4 reserved bits xxx5 xxx7 xxx6 function nothing is assigned. if necessary, set to 0. when read, the content is undefined. xxx bit function varies according to the operating mode. set to 0. 0 (b3) (b2) rw rw rw rw wo rw ro xxx bits 0: xxx 1: xxx *1 *2 *3 *4 free datasheet http:///
4. list of abbrevia tions and acronyms abbreviation full form acia asynchronous communication interface adapter bps bits per second crc cyclic redundancy check dma direct memory access dmac direct memory access controller gsm global system for mobile communications hi-z high impedance iebus inter equipment bus i/o input/output irda infrared data association lsb least significant bit msb most significant bit nc non-connection pll phase locked loop pwm pulse width modulation sfr special function registers sim subscriber identity module uart universal asynchrono us receiver/transmitter vco voltage controlled oscillator all trademarks and registered trademarks are the property of thei r respective owners. free datasheet http:///
a - 1 sfr page reference ............................................................................................................ ............... b - 1 1. overview .................................................................................................................... ..................... 1 1.1 applications ............................................................................................................... ................................ 1 1.2 performance overview ....................................................................................................... ....................... 2 1.3 block diagram .............................................................................................................. ............................ 4 1.4 product information .................................... .................................................................... .......................... 5 1.5 pin assignments ............................................................................................................ ............................ 9 1.6 pin functions .............................................................................................................. ............................. 11 2. central processing unit (cpu) ............................................................................................... ...... 13 2.1 data registers (r0, r1, r2, and r3) ........................................................................................ .............. 14 2.2 address registers (a0 and a1) .............................................................................................. ................. 14 2.3 frame base register (fb) ................................................................................................... .................... 14 2.4 interrupt table register (intb) ..................... ....................................................................... .................. 14 2.5 program counter (pc) ....................................................................................................... ...................... 14 2.6 user stack pointer (usp) and interrupt stack pointer (isp) ................................................................. . 14 2.7 static base register (sb) .................................................................................................. ...................... 14 2.8 flag register (flg) ........................................................................................................ ........................ 14 2.8.1 carry flag (c) ........................................................................................................... .......................... 14 2.8.2 debug flag (d) ........................................................................................................... ........................ 14 2.8.3 zero flag (z) ............................................................................................................ ........................... 14 2.8.4 sign flag (s) ............................................................................................................ ........................... 14 2.8.5 register bank select flag (b) ............................................................................................ ................ 14 2.8.6 overflow flag (o) ........................................................................................................ ...................... 14 2.8.7 interrupt enable flag (i) ................................................................................................ ..................... 15 2.8.8 stack pointer select flag (u) ............................................................................................ .................. 15 2.8.9 processor interrupt priority le vel (ipl) ................................................................................. ............ 15 2.8.10 reserved bit ............................................................................................................ ............................ 15 3. memory ...................................................................................................................... ................... 16 3.1 r8c/24 group .............. .............. .............. .............. .............. .............. .............. ............. .......................... 16 3.2 r8c/25 group .............. .............. .............. .............. .............. .............. .............. ............. .......................... 17 4. special function registers (sfrs) ........................................................................................... .... 18 5. resets ...................................................................................................................... ..................... 25 5.1 hardware reset ............................................................................................................. .......................... 28 5.1.1 when power supply is stable .............................................................................................. ............... 28 5.1.2 power on ................................................................................................................. ........................... 28 5.2 power-on reset function .................................................................................................... ................... 30 5.3 voltage monitor 0 reset .................................................................................................... ..................... 31 5.4 voltage monitor 1 reset .................................................................................................... ..................... 31 5.5 voltage monitor 2 reset .................................................................................................... ..................... 31 5.6 watchdog timer reset .... .............. .............. .............. .............. ........... ............ ........... ......... ..................... 32 5.7 software reset ............................................................................................................. ............................ 32 6. voltage detection circuit ................................................................................................... ........... 33 6.1 vcc input voltage .......................................................................................................... ........................ 40 table of contents free datasheet http:///
a - 2 6.1.1 monitoring vdet0 ......................................................................................................... ...................... 40 6.1.2 monitoring vdet1 ......................................................................................................... ...................... 40 6.1.3 monitoring vdet2 ......................................................................................................... ...................... 40 6.2 voltage monitor 0 reset .................................................................................................... ..................... 41 6.3 voltage monitor 1 interrupt and voltage monitor 1 re set .................................................................... . 42 6.4 voltage monitor 2 interrupt and voltage monitor 2 re set .................................................................... . 44 7. programmable i/o ports ...................................................................................................... ......... 46 7.1 functions of programmable i/o ports ........................................................................................ ............. 46 7.2 effect on peripheral functions ............................................................................................. ................... 47 7.3 pins other than programmable i/ o ports ..................................................................................... ........... 47 7.4 port settings .............................................................................................................. ............................... 59 7.5 unassigned pin handling .................................................................................................... .................... 70 8. processor mode .............................................................................................................. .............. 71 8.1 processor modes ............................................................................................................ .......................... 71 9. bus ......................................................................................................................... ....................... 72 10. clock generation circuit ................................................................................................... ............ 73 10.1 xin clock ................................................................................................................. .............................. 82 10.2 on-chip oscillator clocks ...... .............. .............. .............. ............... .............. ........... ......... ..................... 83 10.2.1 low-speed on-chip os cillator clock ...................................................................................... .......... 83 10.2.2 high-speed on-chip oscillator clock ..................................................................................... .......... 83 10.3 xcin clock ................................................................................................................ ............................. 84 10.4 cpu clock and peripheral function clock ................................................................................... .......... 85 10.4.1 system clock ............................................................................................................ .......................... 85 10.4.2 cpu clock ............................................................................................................... ........................... 85 10.4.3 peripheral function clock (f1, f2, f4, f8, and f3 2) ..................................................................... ........ 85 10.4.4 foco .................................................................................................................... ............................... 85 10.4.5 foco40m ................................................................................................................. .......................... 85 10.4.6 foco-f .................................................................................................................. ............................. 85 10.4.7 foco-s .................................................................................................................. ............................. 85 10.4.8 foco128 ................................................................................................................. ............................ 85 10.4.9 fc4 and fc32 ............................................................................................................ ........................... 86 10.5 power control ............................................................................................................. ............................. 87 10.5.1 standard operating mode ................................................................................................. .................. 87 10.5.2 wait mode ............................................................................................................... ........................... 89 10.5.3 stop mode ............................................................................................................... ............................ 93 10.6 oscillation stop detection function ....................................................................................... ................ 96 10.6.1 how to use oscillation stop detection function .......................................................................... ..... 96 10.7 notes on clock generation circuit ......................................................................................... ................ 99 10.7.1 stop mode ............................................................................................................... ............................ 99 10.7.2 wait mode ............................................................................................................... ........................... 99 10.7.3 oscillation stop detection function ..................................................................................... .............. 99 10.7.4 oscillation circuit constants ........................................................................................... ................... 99 free datasheet http:///
a - 3 11. protection ................................................................................................................. ................... 100 12. interrupts ................................................................................................................. .................... 101 12.1 interrupt overview ................................... ..................................................................... ........................ 101 12.1.1 types of interrupts ..................................................................................................... ....................... 101 12.1.2 software interrupts ..................................................................................................... ...................... 102 12.1.3 special interrupts ...................................................................................................... ........................ 103 12.1.4 peripheral function interrup t ........................................................................................... ................. 103 12.1.5 interrupts and interrupt vect ors ........................................................................................ ................ 104 12.1.6 interrupt control ....................................................................................................... ........................ 106 12.2 int interrupt .................................................................................................................... ..................... 115 12.2.1 inti interrupt (i = 0 to 3) ....................................................................................................... ........... 115 12.2.2 inti input filter (i = 0 to 3) .................................................................................................... .......... 117 12.3 key input interrupt ....................................................................................................... ......................... 118 12.4 address match interrupt ................................................................................................... ..................... 120 12.5 timer rd interrupt, clock synchronous serial i/o with chip select interrupts, and i 2 c bus interface interrupt (interrupts with multiple interrupt request so urces) ............................................................ 122 12.6 notes on interrupts ....................................................................................................... ......................... 124 12.6.1 reading address 00000h ....... .............. .............. .............. .............. .............. ............ ......... ................ 124 12.6.2 sp setting .............................................................................................................. ............................ 124 12.6.3 external interrupt and key input interrupt ..... ......................................................................... ......... 124 12.6.4 changing interrupt sources .............................................................................................. ................ 125 12.6.5 changing interrupt control register contents .. .......................................................................... ..... 126 13. watchdog timer ............................................................................................................. ............. 127 13.1 count source protection mode disabled ..................................................................................... ......... 130 13.2 count source protection mode enabled ...................................................................................... ......... 131 14. timers ..................................................................................................................... .................... 132 14.1 timer ra .................................................................................................................. ............................. 134 14.1.1 timer mode .............................................................................................................. ........................ 137 14.1.2 pulse output mode ....................................................................................................... .................... 139 14.1.3 event counter mode ...................................................................................................... ................... 141 14.1.4 pulse width measurement mode ............................................................................................ .......... 143 14.1.5 pulse period measurement mode ........................................................................................... .......... 146 14.1.6 notes on timer ra ....................................................................................................... .................... 149 14.2 timer rb .................................................................................................................. ............................. 150 14.2.1 timer mode .............................................................................................................. ........................ 154 14.2.2 programmable waveform generation mode ................................................................................... . 157 14.2.3 programmable one-shot generation mode .......... ......................................................................... ... 159 14.2.4 programmable wait one-shot generation mode ............................................................................. 163 14.2.5 notes on timer rb ....................................................................................................... .................... 167 14.3 timer rd .................................................................................................................. ............................. 171 14.3.1 count sources ........................................................................................................... ........................ 176 14.3.2 buffer operation .............. .......................................................................................... ....................... 177 14.3.3 synchronous operation ................................................................................................... .................. 179 14.3.4 pulse output forced cutoff .............................................................................................. ................ 180 14.3.5 input capture function .................................................................................................. ................... 182 14.3.6 output compare function ................................................................................................. ............... 196 free datasheet http:///
a - 4 14.3.7 pwm mode ................................................................................................................ ....................... 213 14.3.8 reset synchronous pwm mode .. .............. .............. .............. .............. .............. ........... ........... ......... 226 14.3.9 complementary pwm mode .................................................................................................. .......... 236 14.3.10 pwm3 mode .............................................................................................................. ....................... 250 14.3.11 timer rd interrupt ..................................................................................................... ...................... 262 14.3.12 notes on timer rd ...................................................................................................... ..................... 264 14.4 timer re .................................................................................................................. ............................. 270 14.4.1 real-time clock mode .................................................................................................... ................ 271 14.4.2 output compare mode ..................................................................................................... ................ 279 14.4.3 notes on timer re ....................................................................................................... .................... 285 15. serial interface ........................................................................................................... ................. 288 15.1 clock synchronous serial i/o mode ................ ......................................................................... ............ 294 15.1.1 polarity select function ................................................................................................ .................... 297 15.1.2 lsb first/msb first select f unction ..................................................................................... .......... 297 15.1.3 continuous receive mode .. .............. .............. .............. ............... .............. .............. .......... ............... 298 15.2 clock asynchronous serial i/o (uart) mode ................................................................................. ... 299 15.2.1 bit rate ................................................................................................................ ............................. 303 15.3 notes on serial interface ................................................................................................. ...................... 304 16. clock synchronous serial interface ............. ............................................................................ ... 305 16.1 mode selection ............................................................................................................ .......................... 305 16.2 clock synchronous serial i/o with chip select (s su) ....................................................................... . 306 16.2.1 transfer clock ................. ......................................................................................... ........................ 315 16.2.2 ss shift register (sstrsr) .............................................................................................. ............... 317 16.2.3 interrupt requests ...................................................................................................... ....................... 318 16.2.4 communication modes and pin f unctions ................................................................................... .... 319 16.2.5 clock synchronous communication mode .................................................................................... .. 320 16.2.6 operation in 4-wire bus communication mode ..... ......................................................................... 327 16.2.7 scs pin control and arbitration .................................................................................................. .... 333 16.2.8 notes on clock synchronous serial i/o with chip select ............................................................... 33 4 16.3 i 2 c bus interface .............. .............. .............. .............. .............. .............. .............. ............. ..................... 335 16.3.1 transfer clock ................. ......................................................................................... ........................ 345 16.3.2 interrupt requests ...................................................................................................... ....................... 346 16.3.3 i 2 c bus interface mode .... .............. .............. ............... .............. ........... ........... ............ ........... ........... 347 16.3.4 clock synchronous serial mode ........................................................................................... ........... 358 16.3.5 noise canceller ......................................................................................................... ........................ 361 16.3.6 bit synchronization circuit ............................................................................................. ................. 362 16.3.7 examples of register settin g ............................................................................................ ................ 363 16.3.8 notes on i 2 c bus interface ........ .............. .............. .............. .............. .............. ............ ........... .......... . 367 17. hardware lin ............................................................................................................... ............... 368 17.1 features .................................................................................................................. ............................... 368 17.2 input/output pins ......................................................................................................... ......................... 369 17.3 register configuration .................................................................................................... ...................... 370 17.4 functional description .................................................................................................... ...................... 372 17.4.1 master mode ............................................................................................................. ........................ 372 17.4.2 slave mode .............................................................................................................. ......................... 375 17.4.3 bus collision detection function ........................................................................................ ............. 379 free datasheet http:///
a - 5 17.4.4 hardware lin end pr ocessing ............................................................................................. ............ 380 17.5 interrupt requests ........................................................................................................ .......................... 381 17.6 notes on hardware lin ..................................................................................................... ................... 382 18. a/d converter .............................................................................................................. ............... 383 18.1 one-shot mode ............................................................................................................. ........................ 387 18.2 repeat mode ............................................................................................................... ........................... 390 18.3 sample and hold ........................................................................................................... ........................ 393 18.4 a/d conversion cycles ..................................................................................................... .................... 393 18.5 internal equivalent circuit of analog input ..... .......................................................................... ........... 394 18.6 output impedance of sensor under a/d conversion ........................................................................... . 395 18.7 notes on a/d converter .................................................................................................... .................... 396 19. flash memory ............................................................................................................... .............. 397 19.1 overview .................................................................................................................. ............................. 397 19.2 memory map ................................................................................................................ ......................... 398 19.3 functions to prevent rewriting of flash memory ............................................................................ .... 400 19.3.1 id code check function .................................................................................................. ................ 400 19.3.2 rom code protect function .......................... ..................................................................... ............. 401 19.4 cpu rewrite mode .......................................................................................................... ..................... 402 19.4.1 ew0 mode ................................................................................................................ ........................ 403 19.4.2 ew1 mode ................................................................................................................ ........................ 403 19.4.3 software commands ....................................................................................................... .................. 412 19.4.4 status registers ........................................................................................................ ......................... 417 19.4.5 full status check ....................................................................................................... ....................... 418 19.5 standard serial i/o mode .................................................................................................. .................... 420 19.5.1 id code check function .................................................................................................. ................ 420 19.6 parallel i/o mode ......................................................................................................... ......................... 424 19.6.1 rom code protect function .......................... ..................................................................... ............. 424 19.7 notes on flash memory ..................................................................................................... ................... 425 19.7.1 cpu rewrite mode ........................................................................................................ ................... 425 20. electrical characteristics ................................................................................................. ........... 428 21. usage notes ................................................................................................................ ............... 454 21.1 notes on clock generation circuit ......................................................................................... .............. 454 21.1.1 stop mode ............................................................................................................... .......................... 454 21.1.2 wait mode ............................................................................................................... ......................... 454 21.1.3 oscillation stop detection function ..................................................................................... ............ 454 21.1.4 oscillation circuit constants ........................................................................................... ................. 454 21.2 notes on interrupts ....................................................................................................... ......................... 455 21.2.1 reading address 00000h ....... .............. .............. .............. .............. .............. ............ ......... ................ 455 21.2.2 sp setting .............................................................................................................. ............................ 455 21.2.3 external interrupt and key input interrupt ..... ......................................................................... ......... 455 21.2.4 changing interrupt sources .............................................................................................. ................ 456 21.2.5 changing interrupt control register contents .. .......................................................................... ..... 457 21.3 notes on timers ........................................................................................................... ......................... 458 21.3.1 notes on timer ra ....................................................................................................... .................... 458 21.3.2 notes on timer rb ....................................................................................................... .................... 459 free datasheet http:///
a - 6 21.3.3 notes on timer rd ....................................................................................................... .................... 463 21.3.4 notes on timer re ....................................................................................................... .................... 469 21.4 notes on serial interface ................................................................................................. ...................... 472 21.5 notes on clock synchr onous serial interface ..... .............. ............... ........... ........... ........... ............ ........ 473 21.5.1 notes on clock synchronous serial i/o with chip select ............................................................... 47 3 21.5.2 notes on i 2 c bus interface ........ .............. .............. .............. .............. .............. ............ ........... .......... . 473 21.6 notes on hardware lin ..................................................................................................... ................... 474 21.7 notes on a/d converter .................................................................................................... .................... 475 21.8 notes on flash memory ..................................................................................................... ................... 476 21.8.1 cpu rewrite mode ........................................................................................................ ................... 476 21.9 notes on noise ............................................................................................................ .......................... 479 21.9.1 inserting a bypass capacitor between vcc and vss pins as a countermeasure against noise and latch-up ...................................................................................................................... ...................... 479 21.9.2 countermeasures against noise error of port contro l registers ..................................................... 479 22. notes on on-chip debugger .................................................................................................. .... 480 appendix 1. package dimensions ................................................................................................. ....... 481 appendix 2. connection examples between serial wr iter and on-chip debugging emulator ............ 482 appendix 3. example of oscillati on evaluation circuit ......................................................................... 483 index ......................................................................................................................... ............................ 484 free datasheet http:///
b - 1 note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol page 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 71 0005h processor mode register 1 pm1 71 0006h system clock control register 0 cm0 75 0007h system clock control register 1 cm1 76 0008h 0009h 000ah protect register prcr 100 000bh 000ch oscillation stop detection register ocd 77 000dh watchdog timer reset register wdtr 129 000eh watchdog timer start register wdts 129 000fh watchdog timer control register wdc 128 0010h address match interrupt register 0 rmad0 121 0011h 0012h 0013h address match interrupt enable register aier 121 0014h address match interrupt register 1 rmad1 121 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 129 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 78 0024h high-speed on-chip oscillator control register 1 fra1 78 0025h high-speed on-chip oscillator control register 2 fra2 79 0026h 0027h 0028h clock prescaler reset flag cpsrf 80 0029h high-speed on-chip oscillator control register 4 fra4 79 002ah 002bh high-speed on-chip oscillator control register 6 fra6 79 002ch high-speed on-chip oscillator control register 7 fra7 79 0030h 0031h voltage detection register 1 vca1 36 0032h voltage detection register 2 vca2 36, 80 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register vw1c 38 0037h voltage monitor 2 circuit control register vw2c 39 0038h voltage monitor 0 circuit control register vw0c 37 0039h 003ah 003bh 003ch 003dh 003eh 003fh address register symbol page 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h timer rd0 interrupt control register trd0ic 107 0049h timer rd1 interrupt control register trd1ic 107 004ah timer re interrupt control register treic 106 004bh 004ch 004dh key input interrupt control register kupic 106 004eh a/d conversion interrupt control register adic 106 004fh ssu/iic interrupt control register ssuic/iicic 107 0050h 0051h uart0 transmit interrupt control register s0tic 106 0052h uart0 receive interrupt control register s0ric 106 0053h uart1 transmit interrupt control register s1tic 106 0054h uart1 receive interrupt control register s1ric 106 0055h int2 interrupt control register int2ic 108 0056h timer ra interrupt control register traic 106 0057h 0058h timer rb interrupt control register trbic 106 0059h int1 interrupt control register int1ic 108 005ah int3 interrupt control register int3ic 108 005bh 005ch 005dh int0 interrupt control register int0ic 108 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh sfr page reference free datasheet http:///
b - 2 note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol page 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 291 00a1h uart0 bit rate register u0brg 291 00a2h uart0 transmit buffer register u0tb 290 00a3h 00a4h uart0 transmit/receive control register 0 u0c0 292 00a5h uart0 transmit/receive control register 1 u0c1 293 00a6h uart0 receive buffer register u0rb 290 00a7h 00a8h uart1 transmit/receive mode register u1mr 291 00a9h uart1 bit rate register u1brg 291 00aah uart1 transmit buffer register u1tb 290 00abh 00ach uart1 transmit/receive control register 0 u1c0 292 00adh uart1 transmit/receive control register 1 u1c1 293 00aeh uart1 receive buffer register u1rb 290 00afh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h ss control register h / iic bus control register 1 sscrh/iccr1 308, 338 00b9h ss control register l / iic bus control register 2 sscrl/iccr2 309, 339 00bah ss mode register / iic bus mode register ssmr/icmr 310, 340 00bbh ss enable register / iic bus interrupt enable register sser/icier 311, 341 00bch ss status register / iic bus status register sssr/icsr 312, 342 00bdh ss mode register 2 / slave address register ssmr2/sar 313, 343 00beh ss transmit data register/iic bus transmit data register sstdr/icdrt 314, 343 00bfh ss receive data register/iic bus receive data register ssrdr/icdrr 314, 344 address register symbol page 00c0h a/d register ad 386 00c1h 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d control register 2 adcon2 386 00d5h 00d6h a/d control register 0 adcon0 385 00d7h a/d control register 1 adcon1 386 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h port p0 register p0 56 00e1h port p1 register p1 56 00e2h port p0 direction register pd0 56 00e3h port p1 direction register pd1 56 00e4h port p2 register p2 56 00e5h port p3 register p3 56 00e6h port p2 direction register pd2 56 00e7h port p3 direction register pd3 56 00e8h port p4 register p4 56 00e9h 00eah port p4 direction register pd4 56 00ebh 00ech port p6 register p6 56 00edh 00eeh port p6 direction register pd6 56 00efh 00f0h 00f1h 00f2h 00f3h 00f4h port p2 drive capacity control register p2drr 58 00f5h uart1 function select register u1sr 293 00f6h 00f7h 00f8h port mode register pmr 58, 293, 314, 344 00f9h external input enable register inten 115 00fah int input filter select register intf 116 00fbh key input enable register kien 119 00fch pull-up control register 0 pur0 57 00fdh pull-up control register 1 pur1 57 00feh 00ffh free datasheet http:///
b - 3 note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol page 0100h timer ra control register tracr 135 0101h timer ra i/o control register traioc 135, 137, 140, 142, 144, 147 0102h timer ra mode register tramr 136 0103h timer ra prescaler register trapre 136 0104h timer ra register tra 136 0105h 0106h lin control register lincr 370 0107h lin status register linst 371 0108h timer rb control register trbcr 151 0109h timer rb one-shot control register trbocr 151 010ah timer rb i/o control register trbioc 152, 154, 158, 160, 165 010bh timer rb mode register trbmr 152 010ch timer rb prescaler register trbpre 153 010dh timer rb secondary register trbsc 153 010eh timer rb primary register trbpr 153 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 273, 281 0119h timer re minute data register / compare data register tremin 273, 281 011ah timer re hour data register trehr 274 011bh timer re day of week data register trewk 274 011ch timer re control register 1 trecr1 275, 282 011dh timer re control register 2 trecr2 276, 282 011eh timer re count source select register trecsr 277, 283 011fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012ah 012bh 012ch 012dh 012eh 012fh address register symbol page 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h timer rd start register trdstr 184, 198, 215, 228, 238, 252 0138h timer rd mode register trdmr 184, 198, 215, 228, 239, 252 0139h timer rd pwm mode register trdpmr 185, 199, 216 013ah timer rd function control register trdfcr 186, 200, 217, 229, 240, 253 013bh timer rd output master enable register 1 trdoer1 201, 218, 230, 241, 254 013ch timer rd output master enable register 2 trdoer2 201, 218, 230, 241, 254 013dh timer rd output control register trdocr 202, 219, 255 013eh timer rd digital filter function select register 0 trddf0 187 013fh timer rd digital filter function select register 1 trddf1 187 0140h timer rd control register 0 trdcr0 188, 203, 219, 231, 242, 256 0141h timer rd i/o control register a0 trdiora0 189, 204 0142h timer rd i/o control register c0 trdiorc0 190, 205 0143h timer rd status register 0 trdsr0 191, 206, 220, 232, 243, 257 0144h timer rd interrupt enable register 0 trdier0 192, 207, 221, 233, 244, 258 0145h timer rd pwm mode output level control register 0 trdpocr0 222 0146h timer rd counter 0 trd0 192, 207, 222, 233, 245, 258 0147h 0148h timer rd general register a0 trdgra0 193, 208, 223, 234, 245, 259 0149h 014ah timer rd general register b0 trdgrb0 193, 208, 223, 234, 245, 259 014bh 014ch timer rd general register c0 trdgrc0 193, 208, 223, 234, 259 014dh 014eh timer rd general register d0 trdgrd0 193, 208, 223, 234, 245, 259 014fh 0150h timer rd control register 1 trdcr1 188, 203, 219, 242 0151h timer rd i/o control register a1 trdiora1 189, 204 0152h timer rd i/o control register c1 trdiorc1 190, 205 0153h timer rd status register 1 trdsr1 191, 206, 220, 232, 243, 257 0154h timer rd interrupt enable register 1 trdier1 192, 207, 221, 233, 244, 258 0155h timer rd pwm mode output level control register 1 trdpocr1 222 0156h timer rd counter 1 trd1 192, 207, 222, 245 0157h 0158h timer rd general register a1 trdgra1 193, 208, 223, 234, 245, 259 0159h 015ah timer rd general register b1 trdgrb1 193, 208, 223, 234, 245, 259 015bh 015ch timer rd general register c1 trdgrc1 193, 208, 223, 234, 245, 259 015dh 015eh timer rd general register d1 trdgrd1 193, 208, 223, 234, 245, 259 015fh free datasheet http:///
b - 4 note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol page 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh address register symbol page 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h 01b3h flash memory control register 4 fmr4 408 01b4h 01b5h flash memory control register 1 fmr1 407 01b6h 01b7h flash memory control register 0 fmr0 406 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh ffffh option function select register ofs 27, 128, 401 free datasheet http:///
rev.3.00 feb 29, 2008 page 1 of 485 rej09b0244-0300 r8c/24 group, r8c/25 group single-chip 16-bit cmos mcu 1. overview these mcus are fabricated using a hi gh-performance silicon gate cmos proc ess, embedding the r8c/tiny series cpu core, and are packaged in a 52-pin molded-plastic lqfp or a 64-pin molded-plastic flga. it implements sophisticated instructions for a high level of instruction efficiency. with 1 mbyte of address space, they are capable of executing instructions at high speed. furthermore, the r8c/25 group has on-chip data flash (1 kb x 2 blocks). the difference between the r8c/24 grou p and r8c/25 group is only the presen ce or absence of data flash. their peripheral functions are the same. 1.1 applications electronic household appliances, office equipment, audio equipment, consumer products, etc. rej09b0244-0300 rev.3.00 feb 29, 2008 free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 2 of 485 rej09b0244-0300 1.2 performance overview table 1.1 outlines the functions and specifications for r8c/24 group and table 1.2 outlines the functions and specifications for r8c/25 group. notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d version if d version functions are to be used. 3. please contact renesas technology sales offices for the y version. table 1.1 functions and specifications for r8c/24 group item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.3 product inform ation for r8c/24 group peripheral functions ports i/o ports: 41 pins, input port: 3 pins led drive ports i/o ports: 8 pins timers timer ra: 8 bits 1 channel timer rb: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer rd: 16 bits 2 channels (input capture and output compare circuits) timer re: with real-time clock and compare match function serial interfaces 2 channels (uart0, uart1) clock synchronous serial i/o, uart clock synchronous serial interface 1 channel i 2 c bus interface (1) clock synchronous serial i/o with chip select lin module hardware lin: 1 channel (timer ra, uart0) a/d converter 10-bit a/d converter: 1 circuit, 12 channels watchdog timer 15 bits 1 channel (with prescaler) reset start selectable interrupts internal: 11 source s, external: 5 sources, software: 4 sources, priority levels: 7 levels clock clock generation circuits 3 circuits ? xin clock generation circuit (with on-chip feedback resistor) ? on-chip oscillator (h igh speed, low speed) high-speed on-chip osc illator has a frequency adjustment function ? xcin clock generation circuit (32 khz) real-time clock (timer re) oscillation stop de tection function xin clock oscillation stop detection function voltage detection circuit on-chip power-on reset circuit on-chip electrical characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) vcc = 2.2 to 5.5 v (f(xin) = 5 mhz) current consumption typ. 10 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 6 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 2.0 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz) typ. 0.7 a (vcc = 3.0 v, stop mode) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 100 times operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (2) -20 to 105 c (y version) (3) package 52-pin molded-plastic lqfp 64-pin molded-plastic flga free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 3 of 485 rej09b0244-0300 table 1.2 functions and specifications for r8c/25 group notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d version if d version functions are to be used. 3. please contact renesas technology sales offices for the y version. item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.4 product inform ation for r8c/25 group peripheral functions ports i/o ports: 41 pins, input port: 3 pins led drive ports i/o ports: 8 pins timers timer ra: 8 bits 1 channel timer rb: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer rd: 16 bits 2 channels (input capture and output compare circuits) timer re: with real-time clock and compare match function serial interface 2 channels (uart0, uart1) clock synchronous serial i/o, uart clock synchronous serial interface 1 channel i 2 c bus interface (1) clock synchronous serial i/o with chip select lin module hardware lin: 1 cha nnel (timer ra, uart0) a/d converter 10-bit a/d converter: 1 circuit, 12 channels watchdog timer 15 bits 1 channel (with prescaler) reset start selectable interrupts internal: 11 source s, external: 5 sources, software: 4 sources, priority levels: 7 levels clock clock generation circuits 3 circuits ? xin clock generation circ uit (with on-chip feedback resistor) ? on-chip oscillator (h igh speed, low speed) high-speed on-chip osc illator has a frequency adjustment function ? xcin clock generation circuit (32 khz) real-time clock (timer re) oscillation stop de tection function xin clock oscillation stop detection function voltage detection circuit on-chip power-on reset circuit on-chip electrical characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) vcc = 2.2 to 5.5 v (f(xin) = 5 mhz) current consumption typ. 10 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 6 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 2.0 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz) typ. 0.7 a (vcc = 3.0 v, stop mode) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 1,0000 times (data flash) 1,000 times (program rom) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (2) -20 to 105 c (y version) (3) package 52-pin molded-plastic lqfp 64-pin molded-plastic flga free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 4 of 485 rej09b0244-0300 1.3 block diagram figure 1.1 shows a block diagram. figure 1.1 block diagram r8c/tiny series cpu core a/d converter (10 bits 12 channels) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout uart or clock synchronous serial i/o (8 bits 2 channels) memory watchdog timer (15 bits) rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. i 2 c bus interface or clock synchronous serial i/o with chip select (8 bits 1 channel) 8 port p1 6 port p3 3 3 port p4 8 port p0 8 port p2 8 port p6 lin module (1 channel) timers timer ra (8 bits) timer rb (8 bits) timer rd (16 bits 2 channels) timer re (8 bits) peripheral functions free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 5 of 485 rej09b0244-0300 1.4 product information table 1.3 lists the product information for r8c/24 group and table 1.4 lists the product information for r8c/25 group. note: 1. the user rom is programmed before shipment. table 1.3 product information for r8c/24 group current of feb. 2008 type no. rom capacity ram capacity package type remarks r5f21244snfp 16 kbytes 1 kbyte plqp0052ja-a n version blank product r5f21245snfp 24 kbytes 2 kbytes plqp0052ja-a r5f21246snfp 32 kbytes 2 kbytes plqp0052ja-a r5f21247snfp 48 kbytes 2.5 kbytes plqp0052ja-a r5f21248snfp 64 kbytes 3 kbytes plqp0052ja-a r5f21244snlg 16 kbytes 1 kbyte ptlg0064ja-a r5f21246snlg 32 kbytes 2 kbytes ptlg0064ja-a r5f21244sdfp 16 kbytes 1 kbyte plqp0052ja-a d version blank product r5f21245sdfp 24 kbytes 2 kbytes plqp0052ja-a r5f21246sdfp 32 kbytes 2 kbytes plqp0052ja-a r5f21247sdfp 48 kbytes 2.5 kbytes plqp0052ja-a r5f21248sdfp 64 kbytes 3 kbytes plqp0052ja-a R5F21244SNXXXFP 16 kbytes 1 kb yte plqp0052ja-a n version factory programming product (1) r5f21245snxxxfp 24 kbytes 2 kbytes plqp0052ja-a r5f21246snxxxfp 32 kbytes 2 kbytes plqp0052ja-a r5f21247snxxxfp 48 kbytes 2.5 kbytes plqp0052ja-a r5f21248snxxxfp 64 kbytes 3 kbytes plqp0052ja-a r5f21244snxxxlg 16 kbytes 1 kbyte ptlg0064ja-a r5f21246snxxxlg 32 kbytes 2 kbytes ptlg0064ja-a r5f21244sdxxxfp 16 kbytes 1 kb yte plqp0052ja-a d version factory programming product (1) r5f21245sdxxxfp 24 kbytes 2 kbytes plqp0052ja-a r5f21246sdxxxfp 32 kbytes 2 kbytes plqp0052ja-a r5f21247sdxxxfp 48 kbytes 2.5 kbytes plqp0052ja-a r5f21248sdxxxfp 64 kbytes 3 kbytes plqp0052ja-a free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 6 of 485 rej09b0244-0300 figure 1.2 type number, memory size, and package of r8c/24 group type no. r 5 f 21 24 6 s n xxx fp package type: fp: plqp0052ja-a (0.65 mm pin-pitch, 10 mm square body) lg: ptlg0064ja-a (0.65 mm pin-pitch, 6 mm square body) rom number classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c y: operating ambient temperature -20c to 105c (1) s: low-voltage version rom capacity 4: 16 kb 5: 24 kb 6: 32 kb 7: 48 kb 8: 64 kb r8c/24 group r8c/tiny series memory type f: flash memory renesas mcu renesas semiconductor note: 1. please contact renesas technology sales offices for the y version. free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 7 of 485 rej09b0244-0300 note: 1. the user rom is programmed before shipment. table 1.4 product information for r8c/25 group current of feb. 2008 type no. rom capacity ram capacity package type remarks program rom data flash r5f21254snfp 16 kbytes 1 kbyte 2 1 kbyte plqp0052ja-a n version blank product r5f21255snfp 24 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f21256snfp 32 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f21257snfp 48 kbytes 1 kbyte 2 2.5 kbytes plqp0052ja-a r5f21258snfp 64 kbytes 1 kbyte 2 3 kbytes plqp0052ja-a r5f21254snlg 16 kbytes 1 kbyte 2 1 kbyte ptlg0064ja-a r5f21256snlg 32 kbytes 1 kbyte 2 2 kbytes ptlg0064ja-a r5f21254sdfp 16 kbytes 1 kbyte 2 1 kbyte plqp0052ja-a d version blank product r5f21255sdfp 24 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f21256sdfp 32 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f21257sdfp 48 kbytes 1 kbyte 2 2.5 kbytes plqp0052ja-a r5f21258sdfp 64 kbytes 1 kbyte 2 3 kbytes plqp0052ja-a r5f21254snxxxfp 16 kbytes 1 kbyte 2 1 kbyte plqp0052ja-a n version factory programming product (1) r5f21255snxxxfp 24 kbytes 1 kbyt e 2 2 kbytes plqp0052ja-a r5f21256snxxxfp 32 kbytes 1 kbyt e 2 2 kbytes plqp0052ja-a r5f21257snxxxfp 48 kbytes 1 kbyt e 2 2.5 kbytes plqp0052ja-a r5f21258snxxxfp 64 kbytes 1 kbyt e 2 3 kbytes plqp0052ja-a r5f21254snxxxlg 16 kbytes 1 kbyt e 2 1 kbyte ptlg0064ja-a r5f21256snxxxlg 32 kbytes 1 kbyt e 2 2 kbytes ptlg0064ja-a r5f21254sdxxxfp 16 kbytes 1 kbyte 2 1 kbyte plqp0052ja-a d version factory programming product (1) r5f21255sdxxxfp 24 kbytes 1 kbyt e 2 2 kbytes plqp0052ja-a r5f21256sdxxxfp 32 kbytes 1 kbyt e 2 2 kbytes plqp0052ja-a r5f21257sdxxxfp 48 kbytes 1 kbyt e 2 2.5 kbytes plqp0052ja-a r5f21258sdxxxfp 64 kbytes 1 kbyt e 2 3 kbytes plqp0052ja-a free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 8 of 485 rej09b0244-0300 figure 1.3 type number, memory size, and package of r8c/25 group type no. r 5 f 21 25 6 s n xxx fp package type: fp: plqp0052ja-a (0.65 mm pin-pitch, 10 mm square body) lg: ptlg0064ja-a (0.65 mm pin-pitch, 6 mm square body) rom number classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c y: operating ambient temperature -20c to 105c (1) s: low-voltage version rom capacity 4: 16 kb 5: 24 kb 6: 32 kb 7: 48 kb 8: 64 kb r8c/25 group r8c/tiny series memory type f: flash memory renesas mcu renesas semiconductor note: 1. please contact renesas technology sales offices for the y version. free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 9 of 485 rej09b0244-0300 1.5 pin assignments figure 1.4 shows plqp0052ja-a pack age pin assignments (top view). figure 1.5 shows ptlg0064ja-a package pin assignments. figure 1.4 plqp0052ja-a package pin assignments (top view) 52 p3_7/sso pin assignments (top view) r8c/24 group r8c/25 group 51 p0_0/an7 50 p0_1/an6 49 p0_2/an5 48 p0_3/an4 47 p6_1 46 p6_2 45 p6_0/treo 44 p4_2/vref 43 p0_4/an3 42 p0_5/an2 41 p0_6/an1 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 25 p2_6/trdioc1 p1_7/traio/int1 p1_6/clk0 p1_5/rxd0/(traio)/(int1) (2) p1_4/txd0 p1_3/ki3/an11 p2_5/trdiob1 p2_4/trdioa1 p2_3/trdiod0 p2_2/trdioc0 p2_1/trdiob0 p2_0/trdioa0/trdclk 26 28 29 30 31 32 33 34 35 36 37 38 39 27 40 nc p2_7/trdiod1 vcc/avcc p4_6/xin vss/avss (1) xout/p4_7 reset p4_4/xcout p4_3/xcin mode p3_4/sda/scs p3_3/ssi p3_5/scl/ssck p3_1/trbo p3_0/trao p6_5/clk1 p6_4 p6_3 p0_7/an0 p4_5/int0 p6_6/int2/txd1 p6_7/int3/rxd1 p1_2/ki2/an10 p1_1/ki1/an9 p1_0/ki0/an8 nc nc nc notes: 1. p4_7 is an input-only port. 2. can be assigned to the pin in parentheses by a program. nc: non-connection package: plqp0052ja-a(52p6a-a) 0.65 mm pin pitch, 10 mm square body free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 10 of 485 rej09b0244-0300 figure 1.5 ptlg0064ja-a package pin assignments p2_6/ trdioc1 p2_5/ trdiob1 p2_2/ trdioc0 p1_7/traio/ int1 p1_6/clk0 p1_3/ki3/ an11 p4_5/int0 p6_7/int3/ rxd1 xin/p4_6 p2_3/ trdiod0 p2_0/trdioa0/ trdclk p1_4/txd0 p6_6/int2/ txd1 vss/avss p2_4/ trdioa1 p2_1/ trdiob0 p1_5/rxd0/ (traio)/(int1) (2) p1_2/ki2/ an10 p4_4/xcout p4_3/xcin p3_5/scl/ ssck p6_3 p0_6/an1 p0_7/an0 mode p3_7/sso p6_1 p0_4/an3 p0_5/an2 p3_1/trbo p3_4/sda/ scs p0_0/an7 p0_2/an5 p4_2/vref p3_0/trao p6_5/clk1 p0_1/an6 p0_3/an4 p6_2 p6_0/treo p6_4 p2_7/ trdiod1 vcc/avcc xout/ p4_7 (1) reset p1_0/ki0/ an8 p1_1/ki1/ an9 abcdefgh abcdefgh r5f21244s nlg japan pin assignments (top view) 50 48 46 45 nc 36 nc 4 51 49 nc 44 34 35 nc nc 5 52 47 43 42 nc 33 7 nc 6 2 37 nc 41 38 13 12 nc 9 8 32 31 nc nc 10 16 19 23 nc nc 30 nc 11 17 20 nc 24 28 nc 14 15 18 21 22 25 27 29 pin assignments (top perspective view) 3 p3_3/ssi 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 notes: 1. p4_7 is an input-only port. 2. can be assigned to the pin in parentheses by a program. 3. in the figure, the numbers in circles are the pin numbers of the 52-pin lqfp package (plqp0052ja-a). nc: non-connection package: ptlg0064ja-a(64f0g) 0.65 mm pin pitch, 6 mm square body free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 11 of 485 rej09b0244-0300 1.6 pin functions table 1.5 lists pin functions. i: input o: output i/o: input and output table 1.5 pin functions type symbol i/o type description power supply input vcc, vss i apply 2.2 v to 5. 5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss i power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provid ed for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins. to use an external clock, input it to the xin pin and leave the xout pin open. xin clock output xout o xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins. to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 to int3 i int interrupt input pins. int0 is timer rd input pin. int1 is timer ra input pin. key input interrupt ki0 to ki3 i key input interrupt input pins timer ra traio i/o timer ra i/o pin trao o timer ra output pin timer rb trbo o timer rb output pin timer rd trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 i/o timer rd i/o ports trdclk i external clock input pin timer re treo o divided clock output pin serial interface clk0, clk1 i/o transfer clock i/o pin rxd0, rxd1 i serial data input pins txd0, txd1 o serial data output pins i 2 c bus interface scl i/o clock i/o pin sda i/o data i/o pin clock synchronous serial i/o with chip select ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin reference voltage input vref i reference voltage input pin to a/d converter a/d converter an0 to an11 i analog input pins to a/d converter i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5, p6_0 to p6_7 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. p2_0 to p2_7 also function as led drive ports. input port p4_2, p4_6, p4_7 i input-only ports free datasheet http:///
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 12 of 485 rej09b0244-0300 note: 1. can be assigned to the pin in parentheses by a program. table 1.6 pin name information by pin number pin number control pin port i/o pin functions for of peripheral modules interrupt timer serial interface clock synchronous serial i/o with chip select i 2 c bus interface a/d converter 2 p3_5 ssck scl 3 p3_3 ssi 4 p3_4 scs sda 5mode 6 xcin p4_3 7 xcout p4_4 8 reset 9 xout p4_7 10 vss/avss 11 xin p4_6 12 vcc/avcc 13 p2_7 trdiod1 14 p2_6 trdioc1 15 p2_5 trdiob1 16 p2_4 trdioa1 17 p2_3 trdiod0 18 p2_2 trdioc0 19 p2_1 trdiob0 20 p2_0 trdioa0/trdclk 21 p1_7 int1 traio 22 p1_6 clk0 23 p1_5 (int1) (1) (traio) (1) rxd0 24 p1_4 txd0 25 p1_3 ki3 an11 27 p4_5 int0 int0 28 p6_6 int2 txd1 29 p6_7 int3 rxd1 30 p1_2 ki2 an10 31 p1_1 ki1 an9 32 p1_0 ki0 an8 33 p3_1 trbo 34 p3_0 trao 35 p6_5 clk1 36 p6_4 37 p6_3 38 p0_7 an0 41 p0_6 an1 42 p0_5 an2 43 p0_4 an3 44 vref p4_2 45 p6_0 treo 46 p6_2 47 p6_1 48 p0_3 an4 49 p0_2 an5 50 p0_1 an6 51 p0_0 an7 52 p3_7 sso free datasheet http:///
r8c/24 group, r8c/25 group 2. ce ntral processing unit (cpu) rev.3.00 feb 29, 2008 page 13 of 485 rej09b0244-0300 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1) free datasheet http:///
r8c/24 group, r8c/25 group 2. ce ntral processing unit (cpu) rev.3.00 feb 29, 2008 page 14 of 485 rej09b0244-0300 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is an alogous to a0. a1 can be comb ined with a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register th at indicates the start address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp, and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation results in an overflow; otherwise to 0. free datasheet http:///
r8c/24 group, r8c/25 group 2. ce ntral processing unit (cpu) rev.3.00 feb 29, 2008 page 15 of 485 rej09b0244-0300 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupt are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority le vels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined. free datasheet http:///
r8c/24 group, r8c/25 group 3. memory rev.3.00 feb 29, 2008 page 16 of 485 rej09b0244-0300 3. memory 3.1 r8c/24 group figure 3.1 is a memory map of r8c/24 group. the r8c/ 24 group has 1 mbyte of addr ess space from addresses 00000h to fffffh. the internal rom is allocated lower addresses, beginning with address 0ffffh. for example, a 48-kbyte internal rom area is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal ram is allocated higher addresses, beginni ng with address 00400h. for example, a 2-kbyte internal ram area is allocated addresses 00400h to 00bffh. the inte rnal ram is used not only for storing data but also for calling subroutines and as stacks wh en interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.1 memory map of r8c/24 group undefined instruction overflow brk instruction address match single step watchdog timer/oscillation stop detection/voltage monitor (reserved) (reserved) reset part number internal rom internal ram size address 0yyyyh r5f21244snfp, R5F21244SNXXXFP, r5f21244sdfp, r5f21244sdxxxfp, r5f21244snlg, r5f21244snxxxlg r5f21245snfp, r5f21245snxxxfp, r5f21245sdfp, r5f21245sdxxxfp r5f21246snfp, r5f21246snxxxfp, r5f21246sdfp, r5f21246sdxxxfp, r5f21246snlg, r5f21246snxxxlg r5f21247snfp, r5f21247snxxxfp, r5f21247sdfp, r5f21247sdxxxfp r5f21248snfp, r5f21248snxxxfp, r5f21248sdfp, r5f21248sdxxxfp 16 kbytes 24 kbytes 32 kbytes 48 kbytes 64 kbytes ? ? ? ? 13fffh 007ffh 00bffh 00bffh 00dffh 00fffh 00400h 002ffh 00000h internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch address 0xxxxh note: 1. the blank regions are reserved. do not access locations in these regions. address 1zzzzh size 1 kbyte 2 kbytes 2 kbytes 2.5 kbytes 3 kbytes 0c000h 0a000h 08000h 04000h 04000h fffffh 0ffffh 0yyyyh internal rom (program rom) internal rom (program rom) 1zzzzh 0xxxh free datasheet http:///
r8c/24 group, r8c/25 group 3. memory rev.3.00 feb 29, 2008 page 17 of 485 rej09b0244-0300 3.2 r8c/25 group figure 3.2 is a memory map of r8c/25 group. the r8c/ 25 group has 1 mbyte of addr ess space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower ad dresses, beginning with a ddress 0ffffh. for example, a 48-kbyte internal rom area is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal rom (data flash) is allocated addresses 02400h to 02bffh. the internal ram area is allocated higher addresses, beginning with address 00400h. for example, a 2-kbyte internal ram is allocated addresses 00400h to 00bffh. th e internal ram is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.2 memory map of r8c/25 group undefined instruction overflow brk instruction address match single step watchdog timer/oscillation stop detection/voltage monitor (reserved) (reserved) reset part number internal rom internal ram size address 0yyyyh r5f21254snfp, r5f21254snxxxfp, r5f21254sdfp, r5f21254sdxxxfp, r5f21254snlg, r5f21254snxxxlg r5f21255snfp, r5f21255snxxxfp, r5f21255sdfp, r5f21255sdxxxfp r5f21256snfp, r5f21256snxxxfp, r5f21256sdfp, r5f21256sdxxxfp, r5f21256snlg, r5f21256snxxxlg r5f21257snfp, r5f21257snxxxfp, r5f21257sdfp, r5f21257sdxxxfp r5f21258snfp, r5f21258snxxxfp, r5f21258sdfp, r5f21258sdxxxfp 16 kbytes 24 kbytes 32 kbytes 48 kbytes 64 kbytes 007ffh 00bffh 00bffh 00dffh 00fffh fffffh 0ffffh 0yyyyh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch address 0xxxxh address 1zzzzh size 1 kbyte 2 kbytes 2 kbytes 2.5 kbytes 3 kbytes internal rom (data flash) (1) notes: 1. data flash block a (1 kbyte) and b (1 kbyte) are shown. 2. the blank regions are reserved. do not access locations in these regions. 0xxxxh 02400h 02bffh internal rom (program rom) 1zzzzh ? ? ? ? 13fffh 0c000h 0a000h 08000h 04000h 04000h free datasheet http:///
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 18 of 485 rej09b0244-0300 4. special function registers (sfrs) an sfr (special function regist er) is a control regist er for a peripheral function. ta bles 4.1 to 4.7 list the special function registers. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register. 3. the lvd0on bit in the ofs register is set to 1 and hardware reset. 4. power-on reset, voltage monitor 0 reset or the lvd0on bit in the ofs register is set to 0, and hardware reset. 5. software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3. 6. the csproini bit in the ofs register is set to 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 01101000b 0007h system clock control register 1 cm1 00100000b 0008h 0009h 000ah protect register prcr 00h 000bh 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00x11111b 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h 00h 0013h address match interrupt enable register aier 00h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h 00h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (6) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h high-speed on-chip oscillator control register 4 fra4 when shipping 002ah 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch high-speed on-chip oscillator control register 7 fra7 when shipping 0030h 0031h voltage detection register 1 (2) vca1 00001000b 0032h voltage detection register 2 (2) vca2 00h (3) 00100000b (4) 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register (5) vw1c 00001000b 0037h voltage monitor 2 circuit control register (5) vw2c 00h 0038h voltage monitor 0 circuit control register (2) vw0c 0000x000b (3) 0100x001b (4) 0039h 003ah 003eh 003fh free datasheet http:///
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 19 of 485 rej09b0244-0300 table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h timer rd0 interrupt control register trd0ic xxxxx000b 0049h timer rd1 interrupt control register trd1ic xxxxx000b 004ah timer re interrupt control register treic xxxxx000b 004bh 004ch 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu/iic interrupt control register (2) ssuic / iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h int2 interrupt control register int2ic xx00x000b 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh free datasheet http:///
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 20 of 485 rej09b0244-0300 table 4.3 sfr information (3) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart1 transmit/receive mode register u1mr 00h 00a9h uart1 bit rate register u1brg xxh 00aah uart1 transmit buffer register u1tb xxh 00abh xxh 00ach uart1 transmit/receive control register 0 u1c0 00001000b 00adh uart1 transmit/receive control register 1 u1c1 00000010b 00aeh uart1 receive buffer register u1rb xxh 00afh xxh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 00b9h ss control register l / iic bus control register 2 (2) sscrl / iccr2 0 1111101b 00bah ss mode register / iic bus mode register (2) ssmr / icmr 00011000b 00bbh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 00bch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 00bdh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 00beh ss transmit data register / iic bus transmit data register (2) sstdr / icdrt ffh 00bfh ss receive data register / iic bus receive data register (2) ssrdr / icdrr ffh free datasheet http:///
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 21 of 485 rej09b0244-0300 table 4.4 sfr information (4) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 00c0h a/d register ad xxh 00c1h xxh 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d control register 2 adcon2 00h 00d5h 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h 00eah port p4 direction register pd4 00h 00ebh 00ech port p6 register p6 xxh 00edh 00eeh port p6 direction register pd6 00h 00efh 00f0h 00f1h 00f2h 00f3h 00f4h port p2 drive capacity control register p2drr 00h 00f5h uart1 function select register u1sr xxh 00f6h 00f7h 00f8h port mode register pmr 00h 00f9h external input enable register inten 00h 00fah int input filter select register intf 00h 00fbh key input enable register kien 00h 00fch pull-up control register 0 pur0 00h 00fdh pull-up control register 1 pur1 xx00xx00b 00feh 00ffh free datasheet http:///
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 22 of 485 rej09b0244-0300 table 4.5 sfr information (5) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register trehr 00h 011bh timer re day of week data register trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re count source select register trecsr 00001000b 011fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012ah 012bh 012ch 012dh 012eh 012fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h timer rd start register trdstr 11111100b 0138h timer rd mode register trdmr 00001110b 0139h timer rd pwm mode register trdpmr 10001000b 013ah timer rd function control register trdfcr 10000000b 013bh timer rd output master enable register 1 trdoer1 ffh 013ch timer rd output master enable register 2 trdoer2 0 1111111b 013dh timer rd output control register trdocr 00h 013eh timer rd digital filter function select register 0 trddf0 00h 013fh timer rd digital filter function select register 1 trddf1 00h free datasheet http:///
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 23 of 485 rej09b0244-0300 table 4.6 sfr information (6) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0140h timer rd control register 0 trdcr0 00h 0141h timer rd i/o control register a0 trdiora0 10001000b 0142h timer rd i/o control register c0 trdiorc0 10001000b 0143h timer rd status register 0 trdsr0 11100000b 0144h timer rd interrupt enable register 0 trdier0 11100000b 0145h timer rd pwm mode output level control register 0 trdpocr0 1111 1000b 0146h timer rd counter 0 trd0 00h 0147h 00h 0148h timer rd general register a0 trdgra0 ffh 0149h ffh 014ah timer rd general register b0 trdgrb0 ffh 014bh ffh 014ch timer rd general register c0 trdgrc0 ffh 014dh ffh 014eh timer rd general register d0 trdgrd0 ffh 014fh ffh 0150h timer rd control register 1 trdcr1 00h 0151h timer rd i/o control register a1 trdiora1 10001000b 0152h timer rd i/o control register c1 trdiorc1 10001000b 0153h timer rd status register 1 trdsr1 11000000b 0154h timer rd interrupt enable register 1 trdier1 11100000b 0155h timer rd pwm mode output level control register 1 trdpocr1 1111 1000b 0156h timer rd counter 1 trd1 00h 0157h 00h 0158h timer rd general register a1 trdgra1 ffh 0159h ffh 015ah timer rd general register b1 trdgrb1 ffh 015bh ffh 015ch timer rd general register c1 trdgrc1 ffh 015dh ffh 015eh timer rd general register d1 trdgrd1 ffh 015fh ffh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh free datasheet http:///
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 24 of 485 rej09b0244-0300 table 4.7 sfr information (7) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the ofs register cannot be changed by a pr ogram. use a flash programmer to write to it. address register symbol after reset 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h 01b3h flash memory control register 4 fmr4 01000000b 01b4h 01b5h flash memory control register 1 fmr1 1000000xb 01b6h 01b7h flash memory control register 0 fmr0 00000001b 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh ffffh option function select register ofs (note 2) free datasheet http:///
r8c/24 group, r8c/25 group 5. resets rev.3.00 feb 29, 2008 page 25 of 485 rej09b0244-0300 5. resets the following resets are implemented: hardware reset, power -on reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. table 5.1 lists the reset names and sources. figure 5.1 block diagram of reset circuit table 5.1 reset names and sources reset name source hardware reset input voltage of reset pin is held ?l? power-on reset vcc rises voltage monitor 0 reset vcc falls (monitor voltage: vdet0) voltage monitor 1 reset vcc falls (monitor voltage: vdet1) voltage monitor 2 reset vcc falls (monitor voltage: vdet2) watchdog timer reset underflow of watchdog timer software reset write 1 to pm03 bit in pm0 register reset power-on reset circuit voltage detection circuit watchdog timer cpu voltage monitor 0 reset sfrs bits vca25, vw0c0, and vw0c6 sfrs bits vca13, vca26, vca27, vw1c2, vw1c3, vw2c2, vw2c3, vw0c1, vw0f0, vw0f1, and vw0c7 pin, cpu, and sfr bits other than those listed above vcc hardware reset power-on reset voltage monitor 1 reset watchdog timer reset software reset vca13: bit in vca1 register vca25, vca26, vca27: bits in vca2 register vw0c0, vw0c1, vw0c6, vw0f0, vw0f1, vw0c7: bits in vw0c register vw1c2, vw1c3: bits in vw1c register vw2c2, vw2c3: bits in vw2c register voltage monitor 2 reset sfrs bits vca25, vw0c0, and vw0c6 free datasheet http:///
r8c/24 group, r8c/25 group 5. resets rev.3.00 feb 29, 2008 page 26 of 485 rej09b0244-0300 table 5.2 shows the pin functions while reset pin level is ?l?, figure 5.2 sh ows the cpu register status after reset, figure 5.3 shows the reset sequence, and figure 5.4 shows the ofs register. figure 5.2 cpu register status after reset table 5.2 pin functions while reset pin level is ?l? pin name pin functions p0, p1, p2 input port p3_0, p3_1, p3_3 to p3_5, p3_7 input port p4_2 to p4_7 input port p6 input port b19 b0 interrupt table register(intb) program counter(pc) user stack pointer(usp) interrupt stack pointer(isp) static base register(sb) content of addresses 0fffeh to 0fffch flag register(flg) c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 b15 b0 0000h 0000h 0000h 0000h 0000h 0000h 0000h data register(r0) data register(r1) data register(r2) data register(r3) address register(a0) address register(a1) frame base register(fb) 00000h 0000h 0000h 0000h 0000h free datasheet http:///
r8c/24 group, r8c/25 group 5. resets rev.3.00 feb 29, 2008 page 27 of 485 rej09b0244-0300 figure 5.3 reset sequence figure 5.4 ofs register start time of flash memory (cpu clock 14 cycles) 0fffch 0fffeh 0fffdh content of reset vector cpu clock address (internal address signal) notes: 1. hardware reset. 2. when the ?l? input width to the reset pin is set to foco-s clock 32 cycles or more, setting the reset pin to ?h? also sets the internal reset signal to ?h? at the same. cpu clock 28 cycles foco-s clock 32 cycles (2) foco-s internal reset signal reset pin 10 cycles or more are needed (1) option function select register (1) symbol address when shipping ofs 0ffffh ffh (3) bit symbol bit name function rw notes: 1. 2. 3. if the block including the ofs register is erased, ffh is set to the ofs register. ? (b6) reserved bit set to 1. rw csproini count source protect mode after reset select bit 0 : count source protect mode enabled after reset 1 : count source protect mode disabled after reset rw to use the pow er-on reset, set the lvd0on bit to 0 (voltage monitor 0 reset enabled after reset). romcp1 rom code protect bit 0 : rom code protect enabled 1 : rom code protect disabled rw romcr rom code protect disabled bit 0 : rom code protect disabled 1 : romcp1 enabled rw ? (b1) rw reserved bit set to 1. wdton rw watchdog timer start select bit 0 : starts w atchdog timer automatically after reset 1 : watchdog timer is inactive after reset 1 11 b7 b6 b5 b4 b3 b2 b1 b0 ? (b4) reserved bit set to 1. rw the ofs register is on the flash memory. write to the ofs register w ith a program. after w riting is completed, do not w rite additions to the ofs register. lvd0on voltage detection 0 circuit start bit (2) 0 : voltage monitor 0 reset enabled after hardw are reset 1 : voltage monitor 0 reset disabled after hardw are reset rw free datasheet http:///
r8c/24 group, r8c/25 group 5. resets rev.3.00 feb 29, 2008 page 28 of 485 rej09b0244-0300 5.1 hardware reset a reset is applied using the reset pin. when an ?l? signal is applied to the reset pin while the supply voltage meets the recommended operating conditions, pins, cpu, and sf rs are all reset (refer to table 5.2 pin functions while reset pin level is ?l? ). when the input level applied to the reset pin changes from ?l? to ?h?, a program is executed beginning with the address indicated by the reset vector. after reset, the low-speed on-chip oscillator clock divided by 8 is automa tically selected as the cpu clock. refer to 4. special function registers (sfrs) for the state of the sfrs after reset. the internal ram is not reset. if the reset pin is pulled ?l? while writing to the internal ram is in progress, the contents of internal ram will be undefined. figure 5.5 shows an example of hardware reset circuit and operation and figure 5.6 shows an example of hardware reset circuit (usage example of external supply voltage detectio n circuit) and operation. 5.1.1 when power supply is stable (1) apply ?l? to the reset pin. (2) wait for 10 s or more. (3) apply ?h? to the reset pin. 5.1.2 power on (1) apply ?l? to the reset pin. (2) let the supply voltage increase until it meets the recommended operating conditions. (3) wait for td(p-r) or more to allow the in ternal power supply to stabilize (refer to 20. electrical characteristics ). (4) wait for 10 s or more. (5) apply ?h? to the reset pin. free datasheet http:///
r8c/24 group, r8c/25 group 5. resets rev.3.00 feb 29, 2008 page 29 of 485 rej09b0244-0300 figure 5.5 example of hardware reset circuit and operation figure 5.6 example of hardware reset circuit (usage example of external supply voltage detection circuit) and operation reset vcc vcc reset 2.2 v 0 v 0.2 vcc or below td(p-r) + 10 s or more 0 v note: 1. refer to 20. electrical characteristics. reset vcc vcc reset 2.2 v 0 v 0 v 5 v 5 v example when vcc = 5 v supply voltage detection circuit note: 1. refer to 20. electrical characteristics. td(p-r) + 10 s or more free datasheet http:///
r8c/24 group, r8c/25 group 5. resets rev.3.00 feb 29, 2008 page 30 of 485 rej09b0244-0300 5.2 power-on reset function when the reset pin is connected to the vcc pin via a pull-up resistor, and the vcc pin voltage level rises while the rise gradient is trth or more, the power-on reset func tion is enabled and the mcu resets its pins, cpu, and sfr. when a capacitor is connected to the reset pin, too, always keep the voltage to the reset pin 0.8vcc or more. when the input voltage to the vcc pin reaches the vdet0 level or above, th e low-speed on-chip oscillator clock starts counting. when the low-speed on -chip oscillator clock count reaches 32, the internal reset signal is held ?h? and the mcu enters the reset sequence (refer to figure 5.3 ). the low-speed on-chip oscillator clock divided by 8 is automatically selected as the cpu clock after reset. refer to 4. special function registers (sfrs) for the states of the sfr after power-on reset. the voltage monitor 0 reset is enabled after power-on reset. figure 5.7 shows an example of power-on reset circuit and operation. figure 5.7 example of power-on reset circuit and operation reset vcc 4.7 k ? (reference) notes: 1. when using the voltage monitor 0 digital filter, ensure that the voltage is within the mcu operation voltage range (2.2 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit for details. 3. vdet0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit for details. 4. refer to 20. electrical characteristics. 5. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 respectively, and the vca25 bit in the vca2 register to 1. v det0 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det0 (3) 1 f oco-s 32 1 f oco-s 32 v por2 2.2v external power v cc t rth t rth free datasheet http:///
r8c/24 group, r8c/25 group 5. resets rev.3.00 feb 29, 2008 page 31 of 485 rej09b0244-0300 5.3 voltage monitor 0 reset a reset is applied using the on-chip voltage detection 0 ci rcuit. the voltage detection 0 circuit monitors the input voltage to the vcc pin. the voltage to monitor is vdet0. when the input voltage to the vcc pin reaches the vdet0 level or below, the pins, cpu, and sfr are reset. when the input voltage to the vcc pin reaches the vdet0 level or above, th e low-speed on-chip oscillator clock start counting. when the low-speed on-chip osci llator clock count reaches 32, the in ternal reset signal is held ?h? and the mcu enters the reset sequence (refer to figure 5.3 ). the low-speed on-chip oscillator clock divided by 8 is automatically selected as the cpu clock after reset. the lvd0on bit in the ofs register can be used to enable or disable voltage monitor 0 reset after a hardware reset. setting the lvd0on bit is only valid after a hardware reset. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 respectively, and the vca25 bit in the vca2 register to 1. the lvd0on bit cannot be changed by a program. to set the lvd0on bit, write 0 (voltage monitor 0 reset enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0ffffh using a flash programmer. refer to figure 5.4 ofs register for details of the ofs register. refer to 4. special function registers (sfrs) for the status of the sfr after voltage monitor 0 reset. the internal ram is not reset. when the input voltage to the vcc pin reaches the vdet0 level or below while writing to the internal ram is in progress, the contents of internal ram are undefined. refer to 6. voltage detection circuit for details of voltage monitor 0 reset. 5.4 voltage monitor 1 reset a reset is applied using the on-chip voltage detection 1 ci rcuit. the voltage detection 1 circuit monitors the input voltage to the vcc pin. the voltage to monitor is vdet1. when the input voltage to the vcc pin reaches the vdet1 level or below, the pins, cpu, and sfr are reset and a program is executed beginning with the address indicated by the reset vector. after reset, the low-speed on-chip oscillator clock divided by 8 is automa tically selected as the cpu clock. the voltage monitor 1 does not reset so me portions of the sfr. refer to 4. special function registers (sfrs) for details. the internal ram is not reset. when the input voltage to the vcc pin reaches the vdet1 level or below while writing to the internal ram is in progress, the contents of internal ram are undefined. refer to 6. voltage detection circuit for details of voltage monitor 1 reset. 5.5 voltage monitor 2 reset a reset is applied using the on-chip voltage detection 2 ci rcuit. the voltage detection 2 circuit monitors the input voltage to the vcc pin. the voltage to monitor is vdet2. when the input voltage to the vcc pin reaches the vdet2 level or below, the pins, cpu, and sfr are reset and the program beginning with the address indicated by the reset vector is executed. after reset, the low-speed on-chip oscillator clock divided by 8 is automa tically selected as the cpu clock. the voltage monitor 2 does not reset some sfrs. refer to 4. special function registers (sfrs) for details. the internal ram is not reset. when the input voltage to the vcc pin reaches the vdet2 level or below while writing to the internal ram is in progress, the contents of internal ram are undefined. refer to 6. voltage detection circuit for details of voltage monitor 2 reset. free datasheet http:///
r8c/24 group, r8c/25 group 5. resets rev.3.00 feb 29, 2008 page 32 of 485 rej09b0244-0300 5.6 watchdog timer reset when the pm12 bit in the pm1 register is set to 1 (reset when watchdog timer underflows), the mcu resets its pins, cpu, and sfr if the watchdog timer underflows. then the program beginning with the address indicated by the reset vector is executed. after reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the cpu clock. the watchdog timer reset does not reset some sfrs. refer to 4. special function registers (sfrs) for details. the internal ram is not reset. when the watchdog timer underflows, the contents of internal ram are undefined. refer to 13. watchdog timer for details of the watchdog timer. 5.7 software reset when the pm03 bit in the pm0 register is set to 1 (mcu reset), the mcu resets its pins, cpu, and sfr. the program beginning with the address indicated by the reset vector is executed. after reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the cpu clock. the software reset does not reset some sfrs. refer to 4. special function registers (sfrs) for details. the internal ram is not reset. free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 33 of 485 rej09b0244-0300 6. voltage detection circuit the voltage detection circuit monitors th e input voltage to the vcc pin. this circuit can be used to monitor the vcc input voltage by a program. alternately, voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used. table 6.1 lists the specifications of voltage detection circuit and figures 6.1 to 6.4 show the block diagrams. figures 6.5 to 6.8 show the associated registers. table 6.1 specifications of voltage detection circuit item voltage detection 0 voltage detection 1 voltage detection 2 vcc monitor voltage to monitor vdet0 vdet1 vdet2 detection target whether passing through vdet0 by rising or falling passing through vdet1 by rising or falling passing through vdet2 by rising or falling monitor none vw1c3 bit in vw1c register vca13 bit in vca1 register whether vcc is higher or lower than vdet1 whether vcc is higher or lower than vdet2 process when voltage is detected reset voltage monitor 0 reset voltage monitor 1 reset voltage monitor 2 reset reset at vdet0 > vcc; restart cpu operation at vcc > vdet0 reset at vdet1 > vcc; restart cpu operation after a specified time reset at vdet2 > vcc; restart cpu operation after a specified time interrupt none voltage monitor 1 interrupt voltage monitor 2 interrupt interrupt request at vdet1 > vcc and vcc > vdet1 when digital filter is enabled; interrupt request at vdet1 > vcc or vcc > vdet1 when digital filter is disabled interrupt request at vdet2 > vcc and vcc > vdet2 when digital filter is enabled; interrupt request at vdet2 > vcc or vcc > vdet2 when digital filter is disabled digital filter switch enabled/disabled available available available sampling time (divide-by-n of foco-s) 4 n: 1, 2, 4, and 8 (divide-by-n of foco-s) 4 n: 1, 2, 4, and 8 (divide-by-n of foco-s) 4 n: 1, 2, 4, and 8 free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 34 of 485 rej09b0244-0300 figure 6.1 block diagram of voltage detection circuit figure 6.2 block diagram of voltage monitor 0 reset generation circuit vdet2 vca27 + - vcc b3 vca13 bit vca1 register voltage detection 2 signal voltage detection 1 signal internal reference voltage vca26 + - vdet1 vca25 + - vdet0 voltage detection 0 signal b3 vw1c3 bit vw1c register noise filter noise filter + - 1/2 1/2 1/2 voltage detection 0 circuit vca25 vcc internal reference voltage voltage detection 0 signal is held ?h? when vca25 bit is set to 0 (disabled) voltage detection 0 signal foco-s vw0f1 to vw0f0 = 00b = 01b = 10b = 11b vw0c7 voltage monitor 0 reset signal voltage monitor 0 reset generation circuit vw0c0 to vw0c1, vw0f0 to vw0f1, vw 0c6, vw0c7: bits in vw0c register vca25: bit in vca2 register vw0c0 vw0c6 vw0c1 vw0c1 digital filter free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 35 of 485 rej09b0244-0300 figure 6.3 block diagram of voltage monitor 1 interrupt/reset generation circuit figure 6.4 block diagram of voltage monitor 2 interrupt/reset generation circuit + - 1/2 1/2 1/2 voltage detection 1 circuit vca26 vcc internal reference voltage vw1c3 noise filter (filter width: 200 ns) voltage detection 1 signal is held ?h? when vca26 bit is set to 0 (disabled) voltage detection 1 signal digital filter foco-s vw1f1 to vw1f0 = 00b = 01b = 10b = 11b vw1c2 bit is set to 0 (not detected) by writing 0 by a program. when vca26 bit is set to 0 (voltage detection 1 circuit disabled), vw1c2 bit is set to 0 voltage monitor 1 interrupt/reset generation circuit vw1c0 to vw1c3, vw1f0, vw1f1, vw1c6, vw1c7: bits in vw1c register vca26: bit in vca2 register vw1c1 vw1c1 vw1c2 vw1c7 vw1c0 vw1c6 non-maskable interrupt signal voltage monitor 1 interrupt signal watchdog timer interrupt signal oscillation stop detection interrupt signal voltage monitor 1 reset signal + - 1/2 1/2 1/2 voltage detection 2 circuit vca27 vcc internal reference voltage vca13 noise filter (filter width: 200 ns) voltage detection 2 signal is held ?h? when vca27 bit is set to 0 (disabled) voltage detection 2 signal digital filter foco-s vw2f1 to vw2f0 = 00b = 01b = 10b = 11b vw2c2 bit is set to 0 (not detected) by writing 0 by a program. when vca27 bit is set to 0 (voltage detection 2 circuit disabled), vw2c2 bit is set to 0 vw2c3 watchdog timer block watchdog timer underflow signal this bit is set to 0 (not detected) by writing 0 by a program. voltage monitor 2 interrupt/reset generation circuit vw2c0 to vw2c3, vw2f0, vw2f1, vw2c6, vw2c7: bits in vw2c register vca13: bit in vca1 register vca27: bit in vca2 register vw2c1 vw2c1 vw2c2 vw2c7 vw2c0 vw2c6 non-maskable interrupt signal voltage monitor 2 interrupt signal watchdog timer interrupt signal oscillation stop detection interrupt signal voltage monitor 2 reset signal free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 36 of 485 rej09b0244-0300 figure 6.5 registers vca1 and vca2 voltage detection register 1 symbol address after reset (2) vca1 0031h 00001000b bit symbol bit name function rw notes: 1. 2. the vca13 bit is enabled w hen the vca27 bit in the vca2 register is set to 1 (voltage detection 2 circuit enabled). the vca13 bit is set to 1 (vcc vdet 2) w hen the vca27 bit in the vca2 register is set to 0 (voltage detection 2 circuit disabled). ? (b7-b4) reserved bits set to 0. rw set to 0. 0 b7 b6 b5 b4 b3 b2 b1 b0 0000 the softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. vca13 voltage detection 2 signal monitor flag (1) 00 ? (b2-b0) rw 0 : vcc < vdet2 1 : vcc vdet2 or voltage detection 2 circuit disabled ro reserved bits voltage detection register 2 (1) symbol address after reset (5) vca2 0032h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. use the vca20 bit only w hen entering to w ait mode. to set the vca20 bit, follow the procedure show n in figu r e 10.9 procedure for enabling reduced internal pow er consumption using vca20 bit . vca20 internal pow er low consumption enable bit (6) 0 : disables low consumption 1 : enables low consumption rw set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vca2 register. to use the voltage monitor 1 interrupt/reset or the vw1c3 bit in the vw1c register, set the vca26 bit to 1. after the vca26 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. to use the voltage monitor 2 interrupt/reset or the vca13 bit in the vca1 register, set the vca27 bit to 1. after the vca27 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. to use the voltage monitor 0 reset, set the vca25 bit to 1. after the vca25 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. vca27 voltage detection 2 enable bit (4) 0 : voltage detection 2 circuit disabled 1 : voltage detection 2 circuit enabled rw vca26 voltage detection 1 enable bit (3) 0 : voltage detection 1 circuit disabled 1 : voltage detection 1 circuit enabled rw 000 0 b3 b2 b1 b0 b7 b6 b5 b4 the lvd0on bit in the ofs register is set to 1 and hardw are reset : 00h pow er-on reset, voltage monitor 0 reset or lvd0on bit in the ofs register is set to 0, and hardw are reset : 00100000b vca25 voltage detection 0 enable bit (2) 0 : voltage detection 0 circuit disabled 1 : voltage detection 0 circuit enabled rw ? (b4-b1) reserved bits set to 0. rw free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 37 of 485 rej09b0244-0300 figure 6.6 vw0c register voltage monitor 0 circuit control register (1) symbol address vw0c 0038h bit symbol bit name function rw notes: 1. 2. 3. 4. the vw0c7 bit is enabled w hen the vw0c1 bit set to 1 (digital filter disabled mode). b3 b2 set to 0. rw b1 b0 0 b7 b6 b5 b4 vw0c0 rw voltage monitor 0 reset enable bit (3) 0 : disable 1 : enable vw0c2 res er v ed bit vw0c1 voltage monitor 0 digital filter disable mode select bit when read, the content is undefined. ro 0 : digital filter enabled mode (digital filter circuit enabled) 1 : digital filter disabled mode (digital filter circuit disabled) rw vw0f1 rw sampling clock select bits b5 b4 0 0 : foco-s divided by 1 0 1 : foco-s divided by 2 1 0 : foco-s divided by 4 1 1 : foco-s divided by 8 vw0f0 rw the vw0c0 bit is enabled w hen the vca25 bit in the vca2 register is set to 1 (voltage detection 0 circuit enabled). set the vw0c0 bit to 0 (disable), w hen the vca25 bit is set to 0 (voltage detection 0 circuit disabled). vw0c7 voltage monitor 0 reset generation condition select bit (4) when the vw0c1 bit is set to 1 (digital filter disabled mode), set to 1. rw the lvd0on bit in the ofs register is set to 1 and hardw are reset : 0000x000b pow er-on reset, voltage monitor 0 reset or lvd0on bit in the ofs register is set to 0, and hardw are reset : 0100x001b after reset (2) set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vw0c register. the value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset. vw0c6 voltage monitor 0 circuit mode select bit when the vw0c0 bit is set to 1 (voltage monitor 0 reset enabled), set to 1. rw ? (b3) res er v ed bit free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 38 of 485 rej09b0244-0300 figure 6.7 vw1c register voltage monitor 1 circuit control register (1) symbol address after reset (8) vw1c 0036h 00001000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. when the vw1c6 bit is set to 1 (voltage monitor 1 reset mode), set the vw1c7 bit to 1 (w hen vcc reaches vdet1 or below ). (do not set to 0.) set the prc3 bit in the prcr register to 1 (rew rite enable) before w riting to the vw1c register. to use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the vw1c1 bit before w riting 1. bits vw1c2 and vw1c3 are enabled w hen the vca26 bit in the vca2 register is set to 1 (voltage detection 1 circuit enabled). set this bit to 0 by a program. when 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). the vw1c6 bit is enabled w hen the vw1c0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset). the vw1c0 bit is enabled w hen the vca26 bit in the vca2 register is set to 1 (voltage detection 1 circuit enabled). set the vw1c0 bit to 0 (disable) w hen the vca26 bit is set to 0 (voltage detection 1 circuit disabled). the vw1c7 bit is enabled w hen the vw1c1 bit is set to 1 (digital filter disabled mode). bits vw1c2 and vw1c3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset. vw1c7 voltage monitor 1 interrupt/reset generation condition select bit (7, 9) 0 : when vcc reaches vdet1 or above 1 : when vcc reaches vdet1 or below rw vw1c6 voltage monitor 1 circuit mode select bit (5) 0 : voltage monitor 1 interrupt mode 1 : voltage monitor 1 reset mode rw vw1c3 voltage detection 1 signal monitor flag (3, 8) vw1f1 rw sampling clock select bits b5 b4 0 0 : foco-s divided by 1 0 1 : foco-s divided by 2 1 0 : foco-s divided by 4 1 1 : foco-s divided by 8 vw1f0 rw 0 : v cc < v det1 1 : v cc vdet1 or voltage detection 1 circuit disabled ro 0 : digital filter enabled mode (digital filter circuit enabled) 1 : digital filter disabled mode (digital filter circuit disabled) rw vw1c2 voltage change detection flag (3, 4, 8) vw1c1 voltage monitor 1 digital filter disable mode select bit (2) vw1c0 rw voltage monitor 1 interrupt/reset enable bit (6) 0 : disable 1 : enable b7 b6 b5 b4 b2 0 : not detected 1 : vdet1 crossing detected rw b1 b0 b3 free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 39 of 485 rej09b0244-0300 figure 6.8 vw2c register volta g e monitor 2 circuit control re g ister (1) symbol address after reset (8) vw2c 0037h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. b3 b2 0 : not detected 1 : vcc has crossed vdet2 rw b1 b0 b7 b6 b5 b4 vw2c0 rw voltage monitor 2 interrupt/reset enable bit (6) 0 : disable 1 : enable 0 : digital f ilter enabled mode (digital filter circuit enabled) 1 : digital f ilter disabled mode (digital filter circuit disabled) rw vw2c2 voltage change detection flag (3, 4, 8) vw2c1 voltage monitor 2 digital filter disable mode select bit (2) vw2c3 wdt detection flag (4, 8) vw2f1 rw sampling clock select bits b5 b4 0 0 : f oco-s divided by 1 0 1 : f oco-s divided by 2 1 0 : f oco-s divided by 4 1 1 : f oco-s divided by 8 vw2f0 rw 0 : not detected 1 : detected rw vw2c6 voltage monitor 2 circuit mode select bit (5) 0 : voltage monitor 2 interrupt mode 1 : voltage monitor 2 reset mode rw vw2c7 voltage monitor 2 interrupt/reset generation condition select bit (7, 9) 0 : when vcc reaches vdet2 or above 1 : when vcc reaches vdet2 or below rw when the vw2c6 bit is set to 1 (voltage monitor 2 reset mode), set the vw2c7 bit to 1 (w hen vcc reaches vdet2 or below ). (do not set to 0.) set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vw2c register. to use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the vw2c1 bit before w riting 1. the vw2c2 bit is enabled w hen the vca27 bit in the vca2 register is set to 1 (voltage detection 2 circuit enabled). set this bit to 0 by a program. when 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). the vw2c6 bit is enabled w hen the vw2c0 bit is set to 1 (voltage monitor 2 interrupt/enables reset). the vw2c0 bit is enabled w hen the vca27 bit in the vca2 register is set to 1 (voltage detection 2 circuit enabled). set the vw2c0 bit to 0 (disable) w hen the vca27 bit is set to 0 (voltage detection 2 circuit disabled). the vw2c7 bit is enabled w hen the vw2c1 bit is set to 1 (digital filter disabled mode). bits vw2c2 and vw2c3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset. free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 40 of 485 rej09b0244-0300 6.1 vcc input voltage 6.1.1 monitoring vdet0 vdet0 cannot be monitored. 6.1.2 monitoring vdet1 set the vca26 bit in the vca2 register to 1 (voltage detection 1 circuit enabled). after td(e-a) has elapsed (refer to 20. electrical characteristics ), vdet1 can be monitored by the vw1c3 bit in the vw1c register. 6.1.3 monitoring vdet2 set the vca27 bit in the vca2 register to 1 (voltage detection 2 circuit enabled). after td(e-a) has elapsed (refer to 20. electrical characteristics ), vdet2 can be monitored by the vca13 bit in the vca1 register. free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 41 of 485 rej09b0244-0300 6.2 voltage monitor 0 reset table 6.2 lists the procedure for setting bits associated with voltage monitor reset and figure 6.9 shows an example of voltage monitor 0 reset operation. to use th e voltage monitor 0 reset to exit stop mode, set the vw0c1 bit in the vw0c register to 1 (digital filter disabled). note: 1. when the vw0c0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). figure 6.9 example of voltage monitor 0 reset operation table 6.2 procedure for setting bits associated with voltage monitor reset step when using digital filter when not using digital filter 1 set the vca25 bit in the vca2 register to 1 (voltage detection 0 circuit enabled) 2 wait for td(e-a) 3 select the sampling clock of the digital filter by the vw0f0 to vw0f1 bits in the vw0c register set the vw0c7 bit in the vw0c register to 1 4 (1) set the vw0c1 bit in the vw0c register to 0 (digital filter enabled) set the vw0c1 bit in the vw0c register to 1 (digital filter disabled) 5 (1) set the vw0c6 bit in the vw0c register to 1 (voltage monitor 0 reset mode) 6 set the vw0c2 bit in the vw0c register to 0 7 set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator on) ? 8 wait for 4 cycles of the sampling clock of the digital filter ? (no wait time required) 9 set the vw0c0 bit in the vw0c register to 1 (voltage monitor 0 reset enabled) vdet0 internal reset signal vcc the above applies under the following conditions. ? vca25 bit in vca2 register = 1 (voltage detection 0 circuit enabled) ? vw0c0 bit in vw0c register = 1 (voltage monitor 0 reset enabled) ? vw0c6 bit in vw0c register = 1 (voltage monitor 0 reset mode) when the internal reset signal is held ?l?, the pins, cpu and sfr are reset. the internal reset signal level changes from ?l? to ?h?, and a program is executed beginning with the address indicated by the reset vector. refer to 4. special function registers (sfrs) for the sfr status after reset. 1 foco-s 32 sampling clock of digital filter 4 cycles when the vw0c1 bit is set to 0 (digital filter enabled) internal reset signal when the vw0c1 bit is set to 1 (digital filter disabled) and the vw0c7 bit is set to 1 1 foco-s 32 vw0c1 and vw0c7: bits in vw0c register free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 42 of 485 rej09b0244-0300 6.3 voltage monitor 1 interrupt and voltage monitor 1 reset table 6.3 lists the procedure for setting bits associated with voltage monitor 1 interrupt and reset. figure 6.10 shows an example of voltage monitor 1 interrupt and voltage monitor 1 reset operation. to use the voltage monitor 1 interrupt or voltage monitor 1 reset to exit st op mode, set the vw1c1 bit in the vw1c register to 1 (digital filter disabled). notes: 1. set the vw1c7 bit to 1 (when vcc reaches vdet1 or below) for the voltage monitor 1 reset. 2. when the vw1c0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). table 6.3 procedure for setting bits associated with voltage monitor 1 interrupt and reset step when using digital filter when not using digital filter voltage monitor 1 interrupt voltage monitor 1 reset voltage monitor 1 interrupt voltage monitor 1 reset 1 set the vca26 bit in the vca2 register to 1 (voltage detection 1 circuit enabled) 2 wait for td(e-a) 3 select the sampling clock of the digital filter by the vw1f0 to vw1f1 bits in the vw1c register select the timing of the interrupt and reset request by the vw1c7 bit in the vw1c register (1) 4 (2) set the vw1c1 bit in the vw1c register to 0 (digital filter enabled) set the vw1c1 bit in the vw1c register to 1 (digital filter disabled) 5 (2) set the vw1c6 bit in the vw1c register to 0 (voltage monitor 1 interrupt mode) set the vw1c6 bit in the vw1c register to 1 (voltage monitor 1 reset mode) set the vw1c6 bit in the vw1c register to 0 (voltage monitor 1 interrupt mode) set the vw1c6 bit in the vw1c register to 1 (voltage monitor 1 reset mode) 6 set the vw1c2 bit in the vw1c register to 0 (passing of vdet1 is not detected) 7 set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator on) ? 8 wait for 4 cycles of the sampling clock of the digital filter ? (no wait time required) 9 set the vw1c0 bit in the vw1c register to 1 (voltage monitor 1 interrupt/reset enabled) free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 43 of 485 rej09b0244-0300 figure 6.10 example of voltage monitor 1 interrupt and voltage monitor 1 reset operation vdet1 vw1c3 bit internal reset signal (vw1c6 = 1) vcc the above applies under the following conditions. ? vca26 bit in vca2 register = 1 (voltage detection 1 circuit enabled) ? vw1c0 bit in vw1c register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled) note: 1. if voltage monitor 0 reset is not used, set the power supply to vcc 2.2. 2.2 v (1) 0 1 vw1c2 bit 0 1 when the vw1c1 bit is set to 0 (digital filter enabled) vw1c2 bit 0 1 when the vw1c1 bit is set to 1 (digital filter disabled) and the vw1c7 bit is set to 0 (vdet1 or above) vw1c1, vw1c2, vw1c3, vw1c6, vw1c7: bit in vw1c register set to 0 by interrupt request acknowledgement set to 0 by a program voltage monitor 1 interrupt request (vw1c6 = 0) voltage monitor 1 interrupt request (vw1c6 = 0) vw1c2 bit 0 1 when the vw1c1 bit is set to 1 (digital filter disabled) and the vw1c7 bit is set to 1 (vdet1 or below) voltage monitor 1 interrupt request (vw1c6 = 0) internal reset signal (vw1c6 = 1) 4 cycles of sampling clock of digital filter set to 0 by a program set to 0 by interrupt request acknowledgement set to 0 by a program set to 0 by interrupt request acknowledgement 4 cycles of sampling clock of digital filter free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 44 of 485 rej09b0244-0300 6.4 voltage monitor 2 interrupt and voltage monitor 2 reset table 6.4 lists the procedure for setting bits associated with voltage monitor 2 interrupt and reset. figure 6.11 shows an example of voltage monitor 2 interrupt and voltage monitor 2 reset operation. to use the voltage monitor 2 interrupt or voltage monitor 2 reset to exit st op mode, set the vw2c1 bit in the vw2c register to 1 (digital filter disabled). notes: 1. set the vw2c7 bit to 1 (when vcc reaches vdet2 or below) for the voltage monitor 2 reset. 2. when the vw2c0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). table 6.4 procedure for setting bits associated with voltage monitor 2 interrupt and reset step when using digital filter when not using digital filter voltage monitor 2 interrupt voltage monitor 2 reset voltage monitor 2 interrupt voltage monitor 2 reset 1 set the vca27 bit in the vca2 register to 1 (voltage detection 2 circuit enabled) 2 wait for td(e-a) 3 select the sampling clock of the digital filter by the vw2f0 to vw2f1 bits in the vw2c register select the timing of the interrupt and reset request by the vw2c7 bit in the vw2c register (1) 4 set the vw2c1 bit in the vw2c register to 0 (digital filter enabled) set the vw2c1 bit in the vw2c register to 1 (digital filter disabled) 5 (2) set the vw2c6 bit in the vw2c register to 0 (voltage monitor 2 interrupt mode) set the vw2c6 bit in the vw2c register to 1 (voltage monitor 2 reset mode) set the vw2c6 bit in the vw2c register to 0 (voltage monitor 2 interrupt mode) set the vw2c6 bit in the vw2c register to 1 (voltage monitor 2 reset mode) 6 set the vw2c2 bit in the vw2c register to 0 (passing of vdet2 is not detected) 7 set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator on) ? 8 wait for 4 cycles of the sampling clock of the digital filter ? (no wait time required) 9 set the vw2c0 bit in the vw2c register to 1 (voltage monitor 2 interrupt/reset enabled) free datasheet http:///
r8c/24 group, r8c/25 group 6 . voltage detection circuit rev.3.00 feb 29, 2008 page 45 of 485 rej09b0244-0300 figure 6.11 example of voltage monitor 2 interrupt and voltage monitor 2 reset operation vdet2 vca13 bit internal reset signal (vw2c6 = 1) vcc the above applies under the following conditions. ? vca27 bit in vca2 register = 1 (voltage detection 2 circuit enabled) ? vw2c0 bit in vw2c register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled) note: 1. when voltage monitor 0 reset is not used, set the power supply to vcc 2.2. 2.2 v (1) 0 1 vw2c2 bit 0 1 when the vw2c1 bit is set to 0 (digital filter enabled) vw2c2 bit 0 1 when the vw2c1 bit is set to 1 (digital filter disabled) and the vw2c7 bit is set to 0 (vdet2 or above) vca13: bit in vca1 register vw2c1, vw2c2, vw2c6, vw2c 7: bits in vw2c register set to 0 by interrupt request acknowledgement set to 0 by a program voltage monitor 2 interrupt request (vw2c6 = 0) voltage monitor 2 interrupt request (vw2c6 = 0) vw2c2 bit 0 1 when the vw2c1 bit is set to 1 (digital filter disabled) and the vw2c7 bit is set to 1 (vdet2 or below) voltage monitor 2 interrupt request (vw2c6 = 0) internal reset signal (vw2c6 = 1) 4 cycles of sampling clock of digital filter set to 0 by a program set to 0 by interrupt request acknowledgement set to 0 by a program set to 0 by interrupt request acknowledgement 4 cycles of sampling clock of digital filter free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 46 of 485 rej09b0244-0300 7. programmable i/o ports there are 41 programmable input/output ports (i/o ports) p0 to p2, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5, and p6. also, p4_6 and p4_7 can be used as input-only ports if the xin clock oscillation circuit is not used, and the p4_2 can be used as an input-only port if the a/d converter is not used. table 7.1 lists an overview of programmable i/o ports. notes: 1. in input mode, whether an internal pull-up resistor is connected or not can be selected by registers pur0 and pur1. 2. when the a/d converter is not used, this port can be used as the input-only port. 3. when the xin clock oscillation circuit is not used, these ports can be used as the input-only ports. 7.1 functions of progr ammable i/o ports the pdi_j (j = 0 to 7) bit in the pdi (i = 0 to 4, 6) regi ster controls i/o of the ports p0 to p2, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5, and p6. the pi register consists of a port latch to hold output data and a circuit to read pin states. figures 7.1 to 7.7 show the configurations of progr ammable i/o ports. table 7.2 lists the functions of programmable i/o ports. also, figure 7.9 shows the pdi (i = 0 to 4 and 6) registers. figure 7.10 shows the pi (i = 0 to 4 and 6) registers, figure 7.11 shows registers pur0 and pur1, figure 7.12 shows the pmr register, figure 7.13 shows the p2drr register. i = 0 to 4, 6 j = 0 to 7 note: 1. nothing is assigned to bits pd3_2, pd 3_6, pd4_0 to pd4_2, pd4_6, and pd4_7. table 7.1 overview of programmable i/o ports ports i/o type of output i/o setting internal pull-up resister p0 to p2, p6 i/o cmos3 state set per bit set every 4 bits (1) p3_0, p3_1, p3_3 to p3_4, p3_5, p3_7 i/o cmos3 state set per bit set every 3 bits (1) p4_3 i/o cmos3 state set per bit set every bit (1) p4_4, p4_5 i/o cmos3 state set per bit set every 2 bits (1) p4_2 (2) p4_6, p4_7 (3) i (no output function) none none table 7.2 functions of programmable i/o ports operation when accessing pi register value of pdi_j bit in pdi register (1) when pdi_j bit is set to 0 (input mode) w hen pdi_j bit is set to 1 (output mode) reading read pin input level read the port latch writing write to the port latch write to the port latch. the value written to the port latch is output from the pin. free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 47 of 485 rej09b0244-0300 7.2 effect on peripheral functions programmable i/o ports function as i/o ports for peripheral functions (refer to table 1.6 pin name information by pin number ). table 7.3 lists the setting of pdi_j bit when functioning as i/o ports for peripheral functions (i = 0 to 4, 6 j = 0 to 7). refer to the description of each function for information on how to set peripheral functions. 7.3 pins other than programmable i/o ports figure 7.8 shows the configuration of i/o pins. table 7.3 setting of pdi_j bit when functioning as i/o ports for peripheral functions (i = 0 to 4, 6 j = 0 to 7) i/o of peripheral functions pdi_j bit settings for shared pin functions input set this bit to 0 (input mode). output this bit can be set to either 0 or 1 (output regardless of the port setting) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 48 of 485 rej09b0244-0300 figure 7.1 configuration of programmable i/o ports (1) p1_0 to p1_3 1 output from individual peripheral function analog input port latch data bus pull-up selection input to individual peripheral function p1_4 1 port latch data bus pull-up selection output from individual peripheral function p0 direction register direction register port latch data bus pull-up selection analog input direction register note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 49 of 485 rej09b0244-0300 figure 7.2 configuration of programmable i/o ports (2) p1_6 direction register data bus pull-up selection input to individual peripheral function ?1? output from individual peripheral function p1_5 and p1_7 direction register data bus pull-up selection input to individual peripheral function ?1? int1 input digital filter direction register ?1? data bus pull-up selection input to individual peripheral function output from individual peripheral function p2 drive capacity select drive capacity select output from individual peripheral function port latch port latch port latch note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 50 of 485 rej09b0244-0300 figure 7.3 configuration of programmable i/o ports (3) p3_3, p3_4, p3_5, and p3_7 1 data bus pull-up selection input to individual peripheral function output from individual peripheral function p3_0 and p3_1 data bus pull-up selection 1 output from individual peripheral function direction register direction register port latch port latch note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) (note 1) (note 1) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 51 of 485 rej09b0244-0300 figure 7.4 configuration of programmable i/o ports (4) p4_2/vref data bus p4_3/xcin port latch data bus pull-up selection direction register p4_4/xcout port latch data bus pull-up selection direction register clocked inverter (2) (note 3) notes: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. 2. when cm10 = 1 or cm04 = 0, the clocked inverter is cut off. 3. when cm04 = 0 the feedback resistor is disconnected. (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 52 of 485 rej09b0244-0300 figure 7.5 configuration of programmable i/o ports (5) p4_5 int0 and input to individual peripheral function port latch data bus pull-up selection digital filter p4_6/xin data bus clocked inverter (2) p4_7/xout data bus (note 3) (note 4) direction register notes: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. 2. when cm05 = 1, cm10 = 1, or cm13 = 0, the clocked inverter is cut off. 3. when cm10 = 1 or cm13 = 0, the feedback resistor is disconnected. 4. when cm05 = cm13 = 1 or cm10 = cm13 = 1, this pin is pulled up. (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 53 of 485 rej09b0244-0300 figure 7.6 configuration of programmable i/o ports (6) p6_1, p6_2, p6_3, and p6_4 port latch data bus pull-up selection direction register p6_0 1 direction register data bus pull-up selection output from individual peripheral function p6_5 data bus pull-up selection input to individual peripheral function 1 direction register port latch output from individual peripheral function port latch note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 54 of 485 rej09b0244-0300 figure 7.7 configuration of programmable i/o ports (7) p6_6 int2 input data bus pull-up selection digital filter 1 direction register p6_7 direction register int3 input port latch data bus pull-up selection digital filter input to individual peripheral function output from individual peripheral function port latch note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) (note 1) (note 1) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 55 of 485 rej09b0244-0300 figure 7.8 configuration of i/o pins mode mode signal input reset reset signal input note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) (note 1) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 56 of 485 rej09b0244-0300 figure 7.9 pdi (i = 0 to 4 and 6) registers figure 7.10 pi (i = 0 to 4 and 6) registers port pi direction register (i = 0 to 4, 6) (1, 2) symbol address after reset pd0 (3) 00e2h 00h pd1 00e3h 00h pd2 00e6h 00h pd3 00e7h 00h pd4 00eah 00h pd6 00eeh 00h bit symbol bit name function rw notes: 1. 2. 3. write to the pd0 register w ith the next instruction after that used to set the prc2 bit in the prcr register to 1 (w rite enabled). pdi_ 6 rw bits pd4_0 to pd4_2, pd4_6, and pd4_7 in the pd4 register are unavailable on this mcu. if it is necessary to set bits pd4_0 to pd4_2, pd4_6 and pd4_7 in the pd4 register, set to 0 (input mode). when read, the content is 0. pdi_7 port pi_7 direction bit rw bits pd3_2 and pd3_6 in the pd3 register are unavailable on this mcu. if it is necessary to set bits pd3_2 and pd3_6, set to 0 (input mode). when read, the content is 0. b3 b2 pdi_ 2 b1 b0 pdi_ 1 pdi_ 0 b7 b6 b5 b4 rw rw port pi_5 direction bit rw 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) rw rw port pi_6 direction bit rw pdi_3 port pi_3 direction bit pdi_ 5 port pi_0 direction bit port pi_1 direction bit port pi_4 direction bit port pi_2 direction bit pdi_ 4 port pi register (i = 0 to 4, 6) (1, 2) symbol address after reset p0 00e0h undefined p1 00e1h undefined p2 00e4h undefined p3 00e5h undefined p4 00e8h undefined p6 00ech undefined bit symbol bit name function rw notes: 1. 2. rw po r t pi_ 6 b it rw po r t pi_ 2 b it rw the pin level of any i/o port w hich is set to input mode can be read by reading the corresponding bit in this register. the pin level of any i/o port w hich is set to output mode can be controlled by w riting to the corresponding bit in this register. 0 : ?l? level 1 : ?h? level rw rw rw rw po r t pi_ 0 b it po r t pi_ 1 b it po r t pi_ 7 b it po r t pi_ 5 b it po r t pi_ 4 b it po r t pi_ 3 b it b7 b6 b5 b4 b0 pi_ 1 pi_ 5 pi_ 0 pi_ 2 pi_ 4 pi_ 3 b3 b2 b1 bits p4_0 and p4_1 in the p4 register are unavailable on this mcu. if it is necessary to set bits p4_0 and p4_1, set to 0 (?l? level). when read, the content is 0. bits p3_2 and p3_6 in the p3 register are unavailable on this mcu. if it is necessary to set bits p3_2 and p3_6, set to 0 (?l? level). when read, the content is 0. pi_ 7 pi_ 6 rw free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 57 of 485 rej09b0244-0300 figure 7.11 registers pur0 and pur1 pull-up control register 0 symbol address after reset pur0 00fch 00h bit symbol bit name function rw note: 1. rw p2_4 to p2_7 pull-up (1) rw rw rw rw 0 : not pulled up 1 : pulled up 0 : not pulled up 1 : pulled up 0 : not pulled up 1 : pulled up p2_0 to p2_3 pull-up (1) rw p0_4 to p0_7 pull-up (1) p0_0 to p0_3 pull-up (1) pu03 p1_4 to p1_7 pull-up (1) p1_0 to p1_3 pull-up (1) pu0 1 pu0 0 b7 b6 b5 b4 p3_0, p3_1, and p3_3 pll-up (1) rw b3 b2 b1 b0 pu0 4 0 : not pulled up 1 : pulled up pu0 2 when this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up. pu0 7 pu0 5 rw 0 : not pulled up 1 : pulled up p3_4 to p3_5, and p3_7 pll-up (1) pu0 6 pull-up control register 1 symbol address after reset pur1 00fdh xx00xx00b bit symbol bit name function rw note: 1. rw pu14 p6_0 to p6_3 pull-up (1) rw 0 : not pulled up 1 : pulled up b0 ? when this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up. b3 b2 0 b1 0 b7 b6 b5 b4 ? (b7-b6) nothing is assigned. if necessary, set to 0. when read, the content is 0. pu1 0 p4_3 pull-up (1) 0 : not pulled up 1 : pulled up reserved bits rw pu15 p6_4 to p6_7 pull-up (1) rw pu1 1 p4_4 and p4_5 pull-up (1) 0 : not pulled up 1 : pulled up rw ? (b3-b2) set to 0. free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 58 of 485 rej09b0244-0300 figure 7.12 pmr register figure 7.13 p2drr register port mode registe r symbol address after reset pmr 00f8h 00h bit symbol bit name function rw iicsel rw 0 : selects ssu function 1 : selects i 2 c bus function set to 0. 0 : i/o ports p6_5, p6_6, p6_7 1 : clk1, txd1, rxd1 set to 0. ? res er v ed bits ssu / i 2 c bus sw itch bit rw b0 0 ? res er v ed bits u1 pinsel port clk1/txd1/rxd1 sw itch bit ? (b3-b0) ? (b6-b5) b3 b2 0 b1 0 0 b7 b6 b5 b4 00 port p2 drive capacity control register symbol address after reset p2 drr 00f4h 00h bit symbol bit name function rw note: 1. p2drr4 rw p2_4 drive capacity rw p2_5 drive capacity rw rw p2_1 drive capacity p2_0 drive capacity p2drr3 p2_2 drive capacity p2drr1 rw rw rw b0 p2drr0 b7 b6 b5 b4 b3 b2 b1 both ?h? and ?l? output are set to high drive capacity. p2drr7 p2drr5 rw set p2 output transistor drive capacity 0 : low 1 : high (1) p2drr2 p2_7 drive capacity p2_3 drive capacity p2drr6 p2_6 drive capacity free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 59 of 485 rej09b0244-0300 7.4 port settings tables 7.4 to 7.47 list the port settings. x: 0 or 1 note: 1. pulled up by setting the pu00 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu00 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu00 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu00 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu01 bit in the pur0 register to 1. table 7.4 port p0_0/an7 register pd0 adcon0 function bit pd0_0 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 1 1 1 0 a/d converter input (an7) table 7.5 port p0_1/an6 register pd0 adcon0 function bit pd0_1 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 1 1 0 0 a/d converter input (an6) table 7.6 port p0_2/an5 register pd0 adcon0 function bit pd0_2 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 1 0 1 0 a/d converter input (an5) table 7.7 port p0_3/an4 register pd0 adcon0 function bit pd0_3 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 1 0 0 0 a/d converter input (an4) table 7.8 port p0_4/an3 register pd0 adcon0 function bit pd0_4 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 0 1 1 0 a/d converter input (an3) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 60 of 485 rej09b0244-0300 x: 0 or 1 note: 1. pulled up by setting the pu01 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu01 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu01 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu02 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu02 bit in the pur0 register to 1. table 7.9 port p0_5/an2 register pd0 adcon0 function bit pd0_5 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 0 1 0 0 a/d converter input (an2) table 7.10 port p0_6/an1 register pd0 adcon0 function bit pd0_6 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 0 0 1 0 a/d converter input (an1) table 7.11 port p0_7/an0 register pd0 adcon0 function bit pd0_7 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 0 0 0 0 a/d converter input (an0) table 7.12 port p1_0/ki0 /an8 register pd1 kien adcon0 function bit pd1_0 ki0en ch2 ch1 ch0 adgsel0 setting value 0xxxxx input port (1) 1 x x x x x output port 01xxxx ki 0 input 0 x 1 0 0 1 a/d converter input (an8) table 7.13 port p1_1/ki1 /an9 register pd1 kien adcon0 function bit pd1_1 ki1en ch2 ch1 ch0 adgsel0 setting value 0xxxxx input port (1) 1 x x x x x output port 01xxxx ki 1 input 0 x 1 0 1 1 a/d converter input (an9) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 61 of 485 rej09b0244-0300 x: 0 or 1 note: 1. pulled up by setting the pu02 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu02 bit in the pur0 register to 1. x: 0 or 1 notes: 1. pulled up by setting the pu03 bit in the pur0 register to 1. 2. n-channel open drain output by setting the nch bit in the u0c0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu03 bit in the pur0 register to 1. table 7.14 port p1_2/ki2 /an10 register pd1 kien adcon0 function bit pd1_2 ki2en ch2 ch1 ch0 adgsel0 setting value 0xxxxx input port (1) 1 x x x x x output port 01xxxx ki 2 input 0 x 1 1 0 1 a/d converter input (an10) table 7.15 port p1_3/ki3 /an11 register pd1 kien adcon0 function bit pd1_3 ki3en ch2 ch1 ch0 adgsel0 setting value 0xxxxx input port (1) 1 x x x x x output port 01xxxx ki3 input 0 x 1 1 1 1 a/d converter input (an11) table 7.16 port p1_4/txd0 register pd1 u0mr function bit pd1_4 smd2 smd1 smd0 setting value 0000 input port (1) 1 0 0 0 output port x 001 txd0 output (2) 100 101 110 table 7.17 port p1_5/rxd0/(traio)/(int1 ) register pd1 traioc tramr inten function bit pd1_5 tiosel topcr tmod2 tmod1 tmod0 int1en setting value 0 0xxxx x input port (1) x1xxx x x other than 001b 1 0xxxx x output port x1xxx x x other than 001b 0 x x other than 001b x rxd0 input 0001 0 1 x other than 001b x traio input 0 1 x other than 001b 1 traio/int1 input x 1 0 0 0 1 x traio pulse output free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 62 of 485 rej09b0244-0300 x: 0 or 1 note: 1. pulled up by setting the pu03 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu03 bit in the pur0 register to 1. x: 0 or 1 notes: 1. pulled up by setting the pu04 bit in the pur0 register to 1. 2. output drive capacity high by setting the p2drr0 bit in the p2drr register to 1. table 7.18 port p1_6/clk0 register pd1 u0mr function bit pd1_6 smd2 smd1 smd0 ckdir setting value 0 other than 001b x input port (1) xxx1 1 other than 001b x output port 0 x x x 1 clk0 (external clock) input x 0 0 1 0 clk0 (internal clock) output table 7.19 port p1_7/traio/int1 register pd1 traioc tramr inten function bit pd1_7 tiosel topcr tmod2 tmod1 tmod0 int1en setting value 0 1xxxx x input port (1) x1xxx x x other than 001b 1 1xxxx x output port x1xxx x x other than 001b 0 0 x other than 001b x traio input 0 0 x other than 001b 1 traio/int1 input x 0 0 0 0 1 x traio pulse output table 7.20 port p2_0/trdioa0/trdclk register pd2 trdoer1 trdfcr trdiora0 function bit pd2_0 ea0 cmd1 cmd0 stclk pwm3 ioa2 ioa1 ioa0 setting value 0 1 xxxxxxx input port (1) 1 1 xxxxxxx output port (2) 0 x 0 0 0 1 1 x x timer mode (input capture function) 0 x xx 1 1000external clock input (t rdclk) x00000xxx pwm3 mode waveform output (2) x00001 001 timer mode waveform output (output compare function) (2) 01x free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 63 of 485 rej09b0244-0300 x: 0 or 1 notes: 1. pulled up by setting the pu04 bit in the pur0 register to 1. 2. output drive capacity high by setting the p2drr1 bit in the p2drr register to 1. x: 0 or 1 notes: 1. pulled up by setting the pu04 bit in the pur0 register to 1. 2. output drive capacity high by setting the p2drr2 bit in the p2drr register to 1. x: 0 or 1 notes: 1. pulled up by setting the pu04 bit in the pur0 register to 1. 2. output drive capacity high by setting the p2drr3 bit in the p2drr register to 1. table 7.21 port p2_1/trdiob0 register pd2 trdoer1 trdfcr trdpmr trdiora0 function bit pd2_1 eb0 cmd1 cmd0 pwm3 pwmb0 iob2 iob1 iob0 setting value 01xxxxxxx input port (1) 11xxxxxxx output port (2) 0 x 0 0 1 0 1 x x timer mode (input capture function) x0 10 x x x x x complementary pwm mode waveform output 11 x001xxxxx reset synchronous pwm mode waveform output x0000xxxx pwm3 mode waveform output (2) x00011xxx pwm mode waveform output (2) x00010 001 timer mode waveform output (output compare function) (2) 01x table 7.22 port p2_2/trdioc0 register pd2 trdoer1 trdfcr trdpmr trdiorc0 function bit pd2_2 ec0 cmd1 cmd0 pwm3 pwmc0 ioc2 ioc1 ioc0 setting value 0 1 xxx x xxx input port (1) 1 1 xxx x xxx output port (2) 0 x 0 0 1 0 1 x x timer mode (input capture function) x0 10 xxxxx complementary pwm mode waveform output (2) 11 x001xxxxx reset synchronous pwm mode waveform output (2) x 0 001 1 xxx pwm mode wave form output (2) x 0 001 0 001 timer mode waveform output (output compare function) (2) 01x table 7.23 port p2_3/trdiod0 register pd2 trdoer1 trdfcr trdpmr trdiorc0 function bit pd2_3 ed0 cmd1 cmd0 pwm3 pwmd0 iod2 iod1 iod0 setting value 0 1 xxx x xxx input port (1) 1 1 xxx x xxx output port (2) 0 x 0 0 1 0 1 x x timer mode (input capture function) x0 10 xxxxx complementary pwm mode waveform output (2) 11 x001xxxxx reset synchronous pwm mode waveform output (2) x 0 001 1 xxx pwm mode wave form output (2) x 0 001 0 001 timer mode waveform output (output compare function) (2) 01x free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 64 of 485 rej09b0244-0300 x: 0 or 1 notes: 1. pulled up by setting the pu05 bit in the pur0 register to 1. 2. output drive capacity high by setting the p2drr4 bit in the p2drr register to 1. x: 0 or 1 notes: 1. pulled up by setting the pu05 bit in the pur0 register to 1. 2. output drive capacity high by setting the p2drr5 bit in the p2drr register to 1. x: 0 or 1 notes: 1. pulled up by setting the pu05 bit in the pur0 register to 1. 2. output drive capacity high by setting the p2drr6 bit in the p2drr register to 1. table 7.24 port p2_4/trdioa1 register pd2 trdoer1 trdfcr trdiora1 function bit pd2_4 ea1 cmd1 cmd0 pwm3 ioa2 ioa1 ioa0 setting value 0 1 xxxxxx input port (1) 1 1 xxxxxx output port (2) 0 x 0 0 1 1 x x timer mode (input capture function) x0 10 xxxx complementary pwm mo de waveform output (2) 11 x001xxxx reset synchronous pwm mode waveform output (2) x 0 001 001 timer mode waveform output (output compare function) (2) 01x table 7.25 port p2_5/trdiob1 register pd2 trdoer1 trdfcr trdpmr trdiora1 function bit pd2_5 eb1 cmd1 cmd0 pwm3 pwmb1 iob2 iob1 iob0 setting value 0 1 xxx x xxx input port (1) 1 1 xxx x xxx output port (2) 0 x 0 0 1 0 1 x x timer mode (input capture function) x0 10 xxxxx complementary pwm mode waveform output (2) 11 x001xxxxx reset synchronous pwm mode waveform output (2) x 0 001 1 xxx pwm mode waveform output (2) x 0 001 0 001 timer mode waveform output (output compare function) (2) 01x table 7.26 port p2_6/trdioc1 register pd2 trdoer1 trdfcr trdpmr trdiorc1 function bit pd2_6 ec1 cmd1 cmd0 pwm3 pwmc1 ioc2 ioc1 ioc0 setting value 0 1 xxx x xxx input port (1) 1 1 xxx x xxx output port (2) 0 x 0 0 1 0 1 x x timer mode (input capture function) x0 10 xxxxx complementary pwm mode waveform output (2) 11 x001xxxxx reset synchronous pwm mode waveform output (2) x 0 001 1 xxx pwm mode waveform output (2) x 0 001 0 001 timer mode waveform output (output compare function) (2) 01x free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 65 of 485 rej09b0244-0300 x: 0 or 1 notes: 1. pulled up by setting the pu05 bit in the pur0 register to 1. 2. output drive capacity high by setting the p2drr7 bit in the p2drr register to 1. x: 0 or 1 note: 1. pulled up by setting the pu06 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu06 bit in the pur0 register to 1. x: 0 or 1 notes: 1. pulled up by setting the pu06 bit in the pur0 register to 1. 2. n-channel open drain output by setting the soos bit in t he ssmr2 register to 1 when this pin functions as output. table 7.27 port p2_7/trdiod1 register pd2 trdoer1 trdfcr trdpmr trdiorc1 function bit pd2_7 ed1 cmd1 cmd0 pwm3 pwmd1 iod2 iod1 iod0 setting value 0 1 xxx x xxx input port (1) 1 1 xxx x xxx output port (2) 0 x 0 0 1 0 1 x x timer mode (input capture function) x0 10 xxxxx complementary pwm mode waveform output (2) 11 x001xxxxx reset synchronous pwm mode waveform output (2) x 0 001 1 xxx pwm mode waveform output (2) x 0 001 0 001 timer mode wave form output (output compare function) (2) 01x table 7.28 port p3_0/trao register pd3 traioc function bit pd3_0 toena setting value 00 input port (1) 1 0 output port x 1 trao output table 7.29 port p3_1/trbo register pd3 trbmr trbioc function bit pd3_1 tmod1 tmod0 tocnt setting value 000x input port (1) 100x output port x 01b 1 x other than 00b 0 trbo output table 7.30 port p3_3/ssi register pd3 clock synchronous serial i/o with chip select (refer to table 16.4 association between communication modes and i/o pins .) pmr function bit pd3_3 ssi output control ssi input control iicsel setting value 0 000 input port (1) xx1 1 000 output port (2) xx1 x 0 1 0 ssi input x1 00 ssi output (2) free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 66 of 485 rej09b0244-0300 x: 0 or 1 notes: 1. pulled up by setting the pu07 bit in the pur0 register to 1. 2. n-channel open drain output by setting the csos bit in t he ssmr2 register to 1 when this pin functions as output. x: 0 or 1 notes: 1. pulled up by setting the pu07 bit in the pur0 register to 1. 2. n-channel open drain output by setting the csos bit in t he ssmr2 register to 1 when this pin functions as output. x: 0 or 1 note: 1. pulled up by setting the pu07 bit in the pur0 register to 1. table 7.31 port p3_4/sda/scs register pd3 ssmr2 pmr iccr1 function bit pd3_4 css1 css0 iicsel ice setting value 0000x input port (1) 000x0 1000x output port (2) 100x0 x010x scs input x 10 0x scs output (2) 11 x x x 1 1 sda input/output table 7.32 port p3_5/scl/ssck register pd3 clock synchronous serial i/o with chip select (refer to table 16.4 association between communication modes and i/o pins .) pmr iccr1 function bit pd3_5 ssck output control ssck input control iicsel ice setting value 00 00x input port (1) 00 0x0 10 00x output port (2) 10 0x0 x 0 1 0 0 ssck input x1 0 00 ssck output (2) x 1 0 1 1 scl input/output table 7.33 port p3_7/sso register pd3 clock synchronous serial i/o with chip select (refer to table 16.4 association between communication modes and i/o pins .) ssmr2 pmr function bit pd3_7 sso output control sso input control soos iicsel setting value 00 0 x0 input port (1) 0x x x1 10 0 00 output port 1x x 01 x 0 1 0 0 sso input x 1 0 0 0 sso output (cmos output) x1 0 10 sso output (n-channel open-drain output) table 7.34 port p4_2/vref register adcon1 function bit vcut setting value 0 input port 1 input port/vref input free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 67 of 485 rej09b0244-0300 x: 0 or 1 note: 1. pulled up by setting the pu10 bit in the pur1 register to 1. x: 0 or 1 notes: 1. pulled up by setting the pu11 bit in the pur1 register to 1. 2. since the xcin-xcout oscillation buffer operates with internal step-down power, the xcout output level cannot be used as the cmos level signal directly. x: 0 or 1 note: 1. pulled up by setting the pu11 bit in the pur1 register to 1. table 7.35 port p4_3/xcin register pd4 cm0 cm1 circuit specifications function bit pd4_3 cm04 cm10 cm12 oscillation buffer feedback resistor setting value 00xxoffoff input port (1) 1 0 x x off off output port x 1 0 0 on on xcin-xcout oscillation (o n-chip feedback resistor enabled) x 1 0 1 on off xcin-xcout oscillation (o n-chip feedback resistor disabled) x11 0offon xcin-xcout oscillation stop 1offoff x10 0onon external xcin input 1onoff table 7.36 port p4_4/xcout register pd4 cm0 cm1 circuit specifications function bit pd4_4 cm04 cm10 cm12 oscillation buffer feedback resistor setting value 00xx offoff input port (1) 1 0 x x off off output port x 1 0 0 on on xcin-xcout oscillation ( on-chip feedback resistor enabled) x 1 0 1 on off xcin-xcout oscillation ( on-chip feedback resistor disabled) x11 0offon xcin-xcout oscillation stop 1offoff x10 0onon external xcout output (inverted output of xcin) (2) 1onoff table 7.37 port p4_5/int0 register pd4 inten function bit pd4_5 int0en setting value 0x input port (1) 1 x output port 01 int0 input free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 68 of 485 rej09b0244-0300 x: 0 or 1 x: 0 or 1 x: 0 or 1 note: 1. pulled up by setting the pu14 bit in the pur1 register to 1. note: 1. pulled up by setting the pu14 bit in the pur1 register to 1. note: 1. pulled up by setting the pu14 bit in the pur1 register to 1. note: 1. pulled up by setting the pu14 bit in the pur1 register to 1. table 7.38 port p4_6/xin register cm1 cm0 circuit specifications function bit cm13 cm10 cm05 oscillation buffer feedback resistor setting value 0 x x off off input port 1 0 0 on on xin-xout oscillation 1 0 1 off on external xin input 1 1 0 off off xin-xout oscillation stop 1 1 1 off off xin-xout oscillation stop table 7.39 port p4_7/xout register cm1 cm0 circuit specifications function bit cm13 cm10 cm05 oscillation buffer feedback resistor setting value 0 x x off off input port 1 0 0 on on xin-xout oscillation 1 0 1 off on xout is ?h? pull-up 1 1 0 off off xin-xout oscillation stop 1 1 1 off off xin-xout oscillation stop table 7.40 port p6_0/treo register pd6 trecr1 function bit pd6_0 toena setting value 00 input port (1) 1 0 output port x 1 treo output table 7.41 port p6_1 register pd6 function bit pd6_1 setting value 0 input port (1) 1 output port table 7.42 port p6_2 register pd6 function bit pd6_2 setting value 0 input port (1) 1 output port table 7.43 port p6_3 register pd6 function bit pd6_3 setting value 0 input port (1) 1 output port free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 69 of 485 rej09b0244-0300 note: 1. pulled up by setting the pu15 bit in the pur1 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu15 bit in the pur1 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu15 bit in the pur1 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu15 bit in the pur1 register to 1. table 7.44 port p6_4 register pd6 function bit pd6_4 setting value 0 input port (1) 1 output port table 7.45 port p6_5/clk1 register pd6 pmr u1mr function bit pd6_5 u1pinsel smd2 smd1 smd0 ckdir setting value 0 x other than 001b x input port (1) 0 xxxx xxxx1 1 x other than 001b x output port 0xxx xxxx0 0 1 x x x 1 clk1 (external clock) input x 1 0 0 1 0 clk1 (internal clock) output table 7.46 port p6_6/int2 /txd1 register pd6 pmr u1mr u1c0 inten function bit pd6_6 u1pinsel smd2 smd1 smd0 nch int2en setting value 0 x 000 xx input port (1) 0xxx 1 x 000 x x output port 0xxx 0xxxxx1 int2 input x1 001 0 x txd1 output (cmos output) 100 101 110 x1 001 1 x txd1 output (n-channel open-drain output) 100 101 110 table 7.47 port p6_7/int3 /rxd1 register pd6 pmr inten function bit pd6_7 u1pinsel int3en setting value 0xx input port (1) 1 x x output port 0x1 int3 input 0 1 x rxd1 input free datasheet http:///
r8c/24 group, r8c/25 group 7. programmable i/o ports rev.3.00 feb 29, 2008 page 70 of 485 rej09b0244-0300 7.5 unassigned pin handling table 7.48 lists the unassigned pin handling. notes: 1. if these ports are set to output mode and left open, they remain in input mode until they are switched to output mode by a program. the voltage level of these pins may be undefined and the power current may increase while the ports remain in input mode. the content of the direction regi sters may change due to noise or program runaway caused by noise. in order to enhance progra m reliability, the program should periodically repeat the setting of the direction registers. 2. connect these unassigned pins to the mcu using th e shortest wire length (2 cm or less) possible. 3. when the power-on reset function is in use. figure 7.14 unassigned pin handling table 7.48 unassigned pin handling pin name connection ports p0 to p2, p3_0, p3_1, p3_3 to p3_7, p4_3 to p4_5, p6 ? after setting to input mode, connect each pin to vss via a resistor (pull- down) or connect each pin to vcc via a resistor (pull-up). (2) ? after setting to output mode, leave these pins open. (1,2) ports p4_6, p4_7 connect to vcc via a pull-up resistor (2) port p4_2, vref connect to vcc reset (3) connect to vcc via a pull-up resistor (2) nc open or connect to vcc and vss note: 1. when the power-on reset function is in use. mcu port p0 to p2, p3_0, p3_1, p3_3 to p3_7, p4_3 to p4_5, p6 (input mode ) : : (input mode) (output mode) port p4_6, p4_7 reset (1) port p4_2/vref : : open free datasheet http:///
r8c/24 group, r8c/25 group 8. processor mode rev.3.00 feb 29, 2008 page 71 of 485 rej09b0244-0300 8. processor mode 8.1 processor modes single-chip mode can be sel ected as the processor mode. table 8.1 lists features of processor mode. figure 8. 1 shows the pm0 register and figure 8.2 shows the pm1 register. figure 8.1 pm0 register figure 8.2 pm1 register table 8.1 features of processor mode processor mode accessible areas pin s assignable as i/o port pins single-chip mode sfr, internal ram, intern al rom all pins are i/o ports or peripheral function i/o pins processor mode register 0 (1) symbol address after reset pm0 0004h 00h bit symbol bit name function rw note: 1. b3 b2 ? b1 b0 00 0 ? (b2-b0) b7 b6 b5 b4 rw reserved bits set to 0. set the prc1 bit in the prcr register to 1 (w rite enable) before rew riting the pm0 register. the mcu is reset w hen this bit is set to 1. when read, the content is 0. rw ? (b7-b4) pm0 3 softw are reset bit nothing is assigned. if necessary, set to 0. when read, the content is 0. processor mode register 1 (1) symbol address after reset pm1 0005h 00h bit symbol bit name function rw notes: 1. 2. ? (b6-b3) pm1 2 wdt interrupt/reset sw itch bit nothing is assigned. if necessary, set to 0. when read, the content is 0. the pm12 bit is set to 1 by a program (and remains unchanged even if 0 is w ritten to it). when the cspro bit in the cspr register is set to 1 (count source protect mode enabled), the pm12 bit is automatically set to 1. reserved bit set to 0. set the prc1 bit in the prcr register to 1 (w rite enable) before rew riting the pm1 register. ? (b7) rw b3 b2 ? b1 b0 00 0 : watchdog timer interrupt 1 : watchdog timer reset (2) rw b7 b6 b5 b4 0 ? (b1-b0) rw reserved bits set to 0. free datasheet http:///
r8c/24 group, r8c/25 group 9. bus rev.3.00 feb 29, 2008 page 72 of 485 rej09b0244-0300 9. bus the bus cycles differ when accessing rom/ram, and when accessing sfr. table 9.1 lists bus cycles by access space of the r8c/24 group and table 9.2 lists bus cycles by access space of the r8c/25 group. rom/ram and sfr are connected to the cp u by an 8-bit bus. when accessing in word (16-bit) units, these areas are accessed twice in 8-bit units. table 9.3 lists access un its and bus operations. table 9.3 access units and bus operations however, only following sfrs are connected with the 16-bit bus: timer rd: registers trdi (i = 0,1), trdgrai, trdgrbi, trdgrci, and trdgrdi therefore, they are accessed once in 16-bit units. the bus operation is the same as ?area: sfr, data fl ash, even address byte access? in table 9.3 access units and bus op erations, and 16-bit data is accessed at a time. table 9.1 bus cycles by access space of the r8c/24 group access area bus cycle sfr 2 cycles of cpu clock rom/ram 1 cycle of cpu clock table 9.2 bus cycles by access space of the r8c/25 group access area bus cycle sfr/data flash 2 cycles of cpu clock program rom/ram 1 cycle of cpu clock area sfr, data flash even address byte access rom (program rom), ram odd address byte access even address word access odd address word access cpu clock data data data data data data data data data even even odd odd even+1 even odd+1 odd address even+1 odd+1 odd data data even data cpu clock data address cpu clock data address cpu clock data address data cpu clock address data cpu clock address data cpu clock address data cpu clock address data free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 73 of 485 rej09b0244-0300 10. clock generation circuit the clock generation circuit has: ? xin clock oscillation circuit ? xcin clock oscillation circuit ? low-speed on-chip oscillator ? high-speed on-chip oscillator table 10.1 lists the specifications of clock generation circ uit. figure 10.1 shows a clock generation circuit. figures 10.2 to 10.8 show clock associated registers. figure 10. 9 shows the procedure for enabling reduced internal power consumption using vca20 bit. notes: 1. these pins can be used as p4_6 or p4_7 when using the on-chip oscillator clock as the cpu clock while the xin clock oscillation circuit is not used. 2. these pins can be used as p4_3 and p4_4 when using th e xin clock oscillation circuit and on-chip oscillator clock for a cpu clock while the xcin cl ock oscillation circuit is not used. 3. set the cm05 bit in the cm0 register to 1 (xin cloc k stopped) and the cm13 bit in t he cm1 register to 1 (xin- xout pin) when an external clock is input. 4. the clock frequency is automatically set to up to 20 mhz by a divider when using the high-speed on-chip oscillator as the cpu clock source. table 10.1 specifications of clock generation circuit item xin clock oscillation circuit xcin clock oscillation circuit on-chip oscillator high-speed on-chip oscillator low-speed on-chip oscillator applications ? cpu clock source ? peripheral function clock source ? cpu clock source ? timer ra and timer re clock source ? cpu clock source ? peripheral function clock source ? cpu and peripheral function clock sources when xin clock stops oscillating ? cpu clock source ? peripheral function clock source ? cpu and peripheral function clock sources when xin clock stops oscillating clock frequency 0 to 20 mhz 32.768 khz approx. 40 mhz (4) approx. 125 khz connectable oscillator ? ceramic resonator ? crystal oscillator ? crystal oscillator ?? oscillator connect pins xin, xout (1) xcin, xcout (2) ? (1) ? (1) oscillation stop, restart function usable usable usable usable oscillator status after reset stop stop stop oscillate others externally generated clock can be input (3) ? externally generated clock can be input ? on-chip feedback resistor rf (connected/ not connected, selectable) ?? free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 74 of 485 rej09b0244-0300 figure 10.1 clock generation circuit divider s q r 1/2 1/2 1/2 1/2 1/2 s q r fra00 fra01 = 1 fra01 = 0 cm14 voltage detection circuit cpu clock a b c d e ocd2 = 0 ocd2 = 1 oscillation stop detection xin clock cm02 wait instruction cm10 = 1 (stop mode) a d c h b cm06 = 0 cm17 to cm16 = 11b cm06 = 1 cm06 = 0 cm17 to cm16 = 10b cm06 = 0 cm17 to cm16 = 01b cm06 = 0 cm17 to cm16 = 00b detail of divider oscillation stop detection circuit pulse generation circuit for clock edge detection and charge, discharge control circuit xin clock forcible discharge when ocd0 = 0 charge, discharge circuit oscillation stop detection interrupt generation circuit detection watchdog timer interrupt ocd1 ocd2 bit switch signal cm14 bit switch signal oscillation stop detection, watchdog timer, voltage monitor 1 interrupt, voltage monitor 2 interrupt cm02, cm04, cm05, cm06, cm07: bits in cm0 register cm10, cm13, cm14, cm16, cm17: bits in cm1 register ocd0, ocd1, ocd2: bits in ocd register fra00, fra01: bits in fra0 register e g uart0 a/d converter timer rd timer rb timer ra power-on reset circuit fra2 register foco foco-s g f1 f2 f4 f8 f32 h int0 ssu / i 2 c bus voltage monitor 2 interrupt watchdog timer system clock low-speed on-chip oscillator fra1 register frequency adjustable uart1 divider foco40m on-chip oscillator clock timer re xout cm13 cm05 xin cm13 xcout cm04 xcin fc cm07 = 0 cm07 = 1 high-speed on-chip oscillator foco-f voltage monitor 1 interrupt divider (1/128) foco128 reset power-on reset software reset interrupt request fc4 fc32 fc 1/8 1/4 clock prescaler free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 75 of 485 rej09b0244-0300 figure 10.2 cm0 register system clock control register 0 (1) symbol address after reset cm0 0006h 01101000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. b7 b6 b5 b4 b3 b2 b1 b0 00 ? (b1-b0) reserved bits set to 0. rw cm02 wait peripheral function clock stop bit 0 : peripheral function clock does not stop in w ait mode 1 : peripheral function clock stops in w ait mode rw cm03 xcin-xcout drive capacity select bit (9) 0 : low 1 : high rw cm04 port, xcin-xcout sw itch bit (6) 0 : i/o port p4_3, p4_4 1 : xcin-xcout pin (7) rw cm05 xin clock (xin-xout) stop bit (2, 4) 0 : xin clock oscillates 1 : xin clock stops (3) rw cm06 system clock division select bit 0 (5) 0 : cm16, cm17 enabled 1 : divide-by-8 mode rw cm07 cpu clock select bit (8) 0 : system clock 1 : xcin clock rw when entering stop mode, the cm06 bit is set to 1 (divide-by-8 mode). set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the cm0 register. the cm05 bit stops the xin clock w hen the high-speed on-chip oscillator mode, low -speed on-chip oscillator mode is selected. do not use this bit to detect w hether the xin clock is stopped. to stop the xin clock, set the bits in the follow ing order: (a) set bits ocd1 to ocd0 in the ocd register to 00b. (b) set the ocd2 bit to 1 (selects on-chip oscillator clock). during external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged. when the cm05 bit is set to 1 (xin clock stopped) and the cm13 bit in the cm1 register is set to 0 (p4_6, p4_7), p4_6 and p4_7 can be used as input ports. the mcu enters stop mode, the cm03 bit is set to 1 (high). rew rite the cm03 bit w hile the xcin clock oscillation stabilizes. the cm04 bit can be set to 1 by a program but cannot be set to 0. to use the xcin clock, set the cm04 bit to 1. also, set ports p4_3 and p4_4 as input ports w ithout pull-up. set the cm07 bit to 1 from 0 (xcin clock) after setting the cm04 bit to 1 (xcin-xcout pin) and allow ing xcin clock oscillation to stabilize. free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 76 of 485 rej09b0244-0300 figure 10.3 cm1 register system clock control register 1 (1) symbol address after reset cm1 0007h 00100000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. once the cm13 bit is set to 1 by a program, it cannot be set to 0. when entering stop mode, the cm15 bit is set to 1 (drive capacity high). set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the cm1 register. b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (4, 7, 8) 0 : clock operates 1 : stops all clocks (stop mode) rw cm11 xin-xout on-chip feedback resistor select bit 0 : on-chip feedback resistor enabled 1 : on-chip feedback resistor disabled rw cm12 xcin-xcout on-chip feedback resistor select bit 0 : on-chip feedback resistor enabled 1 : on-chip feedback resistor disabled rw cm13 por t xin- xout s w itc h bit (7, 9) 0 : input ports p4_6, p4_7 1 : xin-xout pin rw cm14 low -speed on-chip osc illation stop bit (5, 6, 8) 0 : low -speed on-chip oscillator on 1 : low -speed on-chip oscillator of f rw cm15 xin-xout drive capacity select bit (2) 0 : low 1 : high rw cm17 rw b7 b6 0 0 : no division mode 0 1 : divide-by-2 mode 1 0 : divide-by-4 mode 1 1 : divide-by-16 mode system clock division select bits 1 (3) cm16 rw when the cm10 bit is set to 1 (stop mode) and the cm13 bit is set to 1 (xin-xout pin), the xout (p4_7) pin goes ?h?. when the cm13 bit is set to 0 (input ports, p4_6, p4_7), p4_7 (xout) enters input mode. in count source protect mode (refer to 13.2 count source protection mode enabled ), the value remains unchanged even if bits cm10 and cm14 are set. when the cm06 bit is set to 0 (bits cm16, cm17 enabled), bits cm16 to cm17 are enabled. if the cm10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled. when the ocd2 bit is set to 0 (xin clock selected), the cm14 bit is set to 1 (low -speed on-chip osc illator st opped). when the ocd2 bit is set to 1 (on-chip osc illator clock selected), the cm14 bit is set to 0 (low -speed on-chip oscillator on). it remains uncha nged even if 1 is w ritten to it. when using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the cm14 bit to 0 (low -speed on-chip osc illator on). free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 77 of 485 rej09b0244-0300 figure 10.4 ocd register oscillation stop detection register (1) symbol address after reset ocd 000ch 00000100b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. the ocd3 bit remains 0 (xin clock oscillates) if bits ocd1 to ocd0 are set to 00b. the cm14 bit is set to 0 (low -speed on-chip osc illator on) if the ocd2 bit is set to 1 (on-chip oscillator clock selected). ref er to figure 10.16 procedure for sw itching clock source from low -speed on-chip oscillator to xin clock for the sw itching procedure w hen the xin clock re-oscillates after detecting an osc illation stop. set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting to the ocd register. the ocd2 bit is automatically set to 1 (on-chip oscillator clock selected) if a xin clock oscillation stop is detected w hile bits ocd1 to ocd0 are set to 11b. if the ocd3 bit is set to 1 (xin clock stopped), the ocd2 bit remains unchanged even w hen set to 0 (xin clock selected). the ocd3 bit is enabled w hen the ocd0 bit is set to 1 (osc illation stop detection f unction enabled). set bits ocd1 to ocd0 to 00b before entering stop mode, high-speed on-chip osc illator mode, or low -s peed on-chip oscillator m ode (xin clock stops). ? (b7-b4) reserved bits set to 0. rw ocd3 clock monitor bit (5, 6) 0 : xin clock oscillates 1 : xin clock stops ro ocd2 system clock select bit (4) 0 : selects xin clock (7) 1 : selects on-chip oscillator clock (3) rw ocd1 rw ocd0 rw oscillation stop detection enable bit (7) oscillation stop detection interrupt enable bit 0 : oscillation stop detection f unction disabled (2) 1 : oscillation stop detection f unction enabled 0 : disabled (2) 1 : enabled 0000 b3 b2 b1 b0 b7 b6 b5 b4 free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 78 of 485 rej09b0244-0300 figure 10.5 registers fra0 and fra1 high-speed on-chip oscillator control register 1 (1) symbol address after reset fra 1 0024h when shipping rw notes: 1. 2. when changing the values of the fra1 register, adjust the fra1 register so that the frequency of the high-speed on-chip oscillator clock w ill be 40 mhz or less. set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the fra1 register. rw function the frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7. high-speed on-chip osc illator f r equency = 40 mhz (fra1 register = value w hen shipping) setting the fra1 register to a low er value results in a higher frequency. setting the fra1 register to a higher value results in a low er frequency. (2) b3 b2 b1 b0 b7 b6 b5 b4 high-speed on-chip oscillator control register 0 (1) symbol address after reset fra 0 0023h 00h bit symbol bit name function rw notes: 1. 2. 3. change the fra01 bit under the follow ing conditions. ? fra 00 = 1 (high-speed on-chip oscillation) ? the cm14 bit in the cm1 register = 0 (low -speed on-chip oscillator on) ? bits fra22 to fra20 in the fra2 register: all divide ratio mode settings are supported w hen vcc = 3.0 v to 5.5 v 000b to 111b divide ratio of 4 or more w hen vcc = 2.7 v to 5.5 v 010b to 111b (divide by 4 or more) divide ratio of 8 or more w hen vcc = 2.2 v to 5.5 v 110b to 111b (divide by 8 or more) when setting the fra01 bit to 0 (low -speed on-chip osc illator selected), do not set the fra 00 bit to 0 (high-s peed on-chip oscillator of f ) at the same time. set the fra00 bit to 0 after setting the fra01 bit to 0. ? (b7-b2) reserved bits set to 0. rw set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the fra0 register. fra 00 rw fra 01 rw high-speed on-chip oscillator enable bit 0 : high-speed on-chip oscillator of f 1 : high-speed on-chip oscillator on high-speed on-chip oscillator select bit (2) 0 : selects low -speed on-chip osc illator (3) 1 : selects high-speed on-chip osc illator 00 0000 b3 b2 b1 b0 b7 b6 b5 b4 free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 79 of 485 rej09b0244-0300 figure 10.6 registers fra2, fra4, fra6 and fra7 high-speed on-chip oscillator control register 2 (1) symbol address after reset fra 2 0025h 00h bit symbol bit name function rw note: 1. set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the fra2 register. b7 b6 b5 b4 b3 b2 b1 b0 0 high-speed on-chip osc illator frequency sw itching bits 0000 fra 20 rw ? (b7-b3) rw reserved bits set to 0. fra 21 rw selects the dividing ratio for the high- speed on-chip osc illator clock. b2 b1 b0 0 0 0: divide-by-2 mode 0 0 1: divide-by-3 mode 0 1 0: divide-by-4 mode 0 1 1: divide-by-5 mode 1 0 0: divide-by-6 mode 1 0 1: divide-by-7 mode 1 1 0: divide-by-8 mode 1 1 1: divide-by-9 mode fra 22 rw high-speed on-chip oscillator control register 4 symbol address after reset fra 4 0029h when shipping rw b7 b6 b5 b4 b3 b2 b1 b0 ro function stores data for frequency correction w hen vcc = 2.7 to 5.5 v. (the value is the same as that of the fra1 register after a reset.) optimal frequency correction to match the voltage conditions can be achieved by transferring this value to the fra1 register. high-speed on-chip oscillator control register 6 symbol address after reset fra 6 002bh when shipping rw b7 b6 b5 b4 b3 b2 b1 b0 ro function stores data for frequency correction w hen vcc = 2.2 to 5.5 v. optimal frequency correction to match the voltage conditions can be achieved by transferring this value to the fra1 register. high-speed on-chip oscillator control register 7 symbol address after reset fra 7 002ch when shipping rw b7 b6 b5 b4 b3 b2 b1 b0 ro function 36.864 mhz frequency correction data is stored. the oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 mhz by transferring this value to the fra1 register. free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 80 of 485 rej09b0244-0300 figure 10.7 cpsrf register figure 10.8 vca2 register clock prescaler reset flag symbol address after reset cpsrf 0028h 00h bit symbol bit name function rw note: 1. only w rite 1 to this bit w hen selecting the xcin clock as the cpu clock, . cpsr clock prescaler reset flag (1) setting this bit to 1 initializes the clock prescaler. (when read, the content is 0) rw ? (b6-b0) reserved bits set to 0. rw 0000 000 b3 b2 b1 b0 b7 b6 b5 b4 voltage detection register 2 (1) symbol address after reset (5) vca2 0032h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. use the vca20 bit only w hen entering to w ait mode. to set the vca20 bit, follow the procedure show n in figu r e 10.9 procedure for enabling reduced internal pow er consumption using vca20 bit . vca20 internal pow er low consumption enable bit (6) 0 : disables low consumption 1 : enables low consumption rw set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vca2 register. to use the voltage monitor 1 interrupt/reset or the vw1c3 bit in the vw1c register, set the vca26 bit to 1. after the vca26 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. to use the voltage monitor 2 interrupt/reset or the vca13 bit in the vca1 register, set the vca27 bit to 1. after the vca27 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. to use the voltage monitor 0 reset, set the vca25 bit to 1. after the vca25 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. vca27 voltage detection 2 enable bit (4) 0 : voltage detection 2 circuit disabled 1 : voltage detection 2 circuit enabled rw vca26 voltage detection 1 enable bit (3) 0 : voltage detection 1 circuit disabled 1 : voltage detection 1 circuit enabled rw 000 0 b3 b2 b1 b0 b7 b6 b5 b4 the lvd0on bit in the ofs register is set to 1 and hardw are reset : 00h pow er-on reset, voltage monitor 0 reset or lvd0on bit in the ofs register is set to 0, and hardw are reset : 00100000b vca25 voltage detection 0 enable bit (2) 0 : voltage detection 0 circuit disabled 1 : voltage detection 0 circuit enabled rw ? (b4-b1) reserved bits set to 0. rw free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 81 of 485 rej09b0244-0300 figure 10.9 procedure for enabling reduced internal power consumption using vca20 bit notes: 1. execute this routine to handle all interrupts generated in wait mode. however, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the i nterrupt routine. 2. do not set the vca20 bit to 0 with the instruction immediately after setting the vca20 bit to 1. also, do not do the opposit e. 3. when the vca20 bit is set to 1, do not set the cm10 bit to 1 (stop mode). 4. when entering wait mode, follow 10.7.2 wait mode . vca20: bit in vca2 register handling procedure of internal power low consumption enabled by vca20 bit enter low-speed clock mode or low-speed on-chip oscillator mode stop xin clock and high-speed on-chip oscillator clock vca20 1 (internal power low consumption enabled) (2, 3) enter wait mode (4) vca20 0 (internal power low consumption disabled) (2) start xin clock or high-speed on-chip oscillator clock (wait until xin clock oscillation stabilizes) enter high-speed clock mode or high-speed on-chip oscillator mode in interrupt routine vca20 0 (internal power low consumption disabled) (2) start xin clock or high-speed on-chip oscillator clock enter high-speed clock mode or high-speed on-chip oscillator mode enter low-speed clock mode or low-speed on-chip oscillator mode exit wait mode by interrupt stop xin clock and high-speed on-chip oscillator clock vca20 1 (internal power low consumption enabled) (2, 3) interrupt handling completed step (1) step (2) step (3) step (4) step (5) step (6) step (7) step (8) step (5) step (6) step (7) step (8) (wait until xin clock oscillation stabilizes) step (1) step (2) step (3) if it is necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (7) in the interrupt routine. if the high-speed clock or high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine. (note 1) interrupt handling free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 82 of 485 rej09b0244-0300 the clocks generated by the clock generation circuits are described below. 10.1 xin clock this clock is supplied by the xin clock oscillation circuit. this clock is used as the clock source for the cpu and peripheral function clocks. the xin cloc k oscillation circuit is configured by connecting a resonator between the xin and xout pins. the xin clock oscillation circu it includes an on-chip feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. the xin clock oscillation circuit may also be configur ed by feeding an externally generated clock to the xin pin. figure 10.10 shows examples of xin clock connection circuit. in reset and after reset, the xin clock stops. the xin clock starts oscillat ing when the cm05 bit in the cm0 register is set to 0 (xin clock oscillates) after setting the cm13 bit in the cm1 register to 1 (xin- xout pin). to use the xin clock for the cpu clock source, set the ocd2 bit in the ocd register to 0 (select xin clock) after the xin clock is oscillating stably. the power consumption can be reduced by setting the cm05 bit in the cm0 register to 1 (xin clock stops) if the ocd2 bit is set to 1 (select on-chip oscillator clock). when an external clock is input to the xin pin are input, the xin clock does not stop if the cm05 bit is set to 1. if necessary, use an external circuit to stop the clock. in stop mode, all clocks including the xin clock stop. refer to 10.5 power control for details. figure 10.10 examples of xi n clock connection circuit xin xout mcu (on-chip feedback resistor) rd (1) cout cin xin xout mcu (on-chip feedback resistor) externally derived clock vcc vss note: 1. insert a damping resistor if required. the resist ance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the manufacturer of the oscillator. use high drive when oscillation starts and, if it is necessary to switch the osci llation drive capacity, do so after oscillation stabilizes. when the oscillation drive capacity is set to low, ch eck that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback re sistor be added to the chip externally, insert a feedback resistor between xin and xout following the instructions. to use this mcu with supply voltage below vcc = 2.7 v, it is recommended to set the cm11 bit in the cm1 register to 1 (on-chip feedback resistor dis abled), the cm15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally. open ceramic resonator external circuit external clock input circuit rf (1) free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 83 of 485 rej09b0244-0300 10.2 on-chip oscillator clocks these clocks are supplied by the on -chip oscillators (high-speed on-chi p oscillator and a low-speed on-chip oscillator). the on-chip oscillator clock is sel ected by the fra01 bit in the fra0 register. 10.2.1 low-speed on-chi p oscillator clock the clock generated by the low-speed on-chip oscilla tor is used as the clock source for the cpu clock, peripheral function clock, foco, and foco-s. after reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as the cpu clock. if the xin clock stops oscillating when bits ocd1 to ocd0 in the ocd register ar e set to 11b, the low-speed on-chip oscillator automatically starts operatin g, supplying the necessary clock for the mcu. the frequency of the low-speed on-chip oscillator vari es depending on the supply voltage and the operating ambient temperature. application products must be de signed with sufficient margin to allow for frequency changes. 10.2.2 high-speed on-chip oscillator clock the clock generated by the high-speed on-chip oscillato r is used as the clock source for the cpu clock, peripheral function clock, foco, foco-f, and foco40m. to use the high-speed on-chip oscillator clock as the cl ock source for the cpu clock, peripheral clock, foco, and foco-f, set bits fra20 to fra22 in the fra2 register as follows: ? all divide ratio mode settings are supported when vcc = 3.0 v to 5.5 v 000b to 111b ? divide ratio of 4 or more when vcc = 2.7 v to 5.5 v 010b to 111b (divide by 4 or more) ? divide ratio of 8 or more when vcc = 2.2 v to 5.5 v 110b to 111b (divide by 8 or more) after reset, the on-chip oscillator clock generated by the high-speed on-c hip oscillator stops. oscillation is started by setting the fra00 bit in the fra0 register to 1 (high-speed on-chip oscillator on). the frequency can be adjusted by registers fra1 and fra2. the frequency correction data (the value is the same as th at of the fra1 register af ter a reset) corresponding to the supply voltage ranges vcc = 2.7 v to 5.5 v is st ored in fra4 register. furthermore, the frequency correction data corresponding to the supply voltage range s vcc = 2.2 v to 5.5 v is stored in fra6 register. to use separate correction values to match these voltage range s, transfer them from fra4 or fra6 register to the fra1 register. the frequency correction data of 36.864 mhz is stored in the fra7 register. to set the frequency of the high- speed on-chip oscillator to 36.864 mhz, transfer the corr ection value in the fra7 register to the fra1 register before use. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in uart mode (refer to table 15.7 bit rate setting example in uart mode (internal clock selected) ). since there are differences in the amount of frequency adjustment among the bits in the fra1 register, make adjustments by changing the settings of individual bits. ad just the fra1 register so that the frequency of the high-speed on-chip oscillator clock will be 40 mhz or less. free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 84 of 485 rej09b0244-0300 10.3 xcin clock this clock is supplied by the xcin clock oscillation circuit. this clock is used as the clock source for the cpu clock, timer ra, and timer re. the xcin clock oscillation circuit is configured by connecting a resonator between the xcin and xcout pins. the xcin clock oscillation circuit includes an on-chip a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in the chip. the xcin clock oscillation circuit may also be configured by feeding an externally generated clock to the xcin pin. figure 10.11 shows examples of xcin clock connection circuits. during and after reset, the xcin clock stops. the xcin clock starts oscillating when the cm04 bit in the cm0 register is set to 1 (xcin-xcout pin). to use the xcin clock for the cpu cloc k source, set the cm07 bit in the cm0 register to 1 (xcin clock) after the xcin clock is oscillating stably. to in put an external clock to the xcin pin, set the cm04 bit in the cm0 register to 1 (xcin-xcout pin) and leave the xcout pin open. this mcu has an on-chip feedback resistor and on-chip re sistor disable/enable switching is possible by the cm12 bit in the cm1 register. in stop mode, all clocks including the xcin clock stop. refer to 10.5 power control for details. figure 10.11 examples of xcin clock connection circuits xcin xcout rd (1) cout cin xcin xcout externally derived clock vcc vss note: 1. insert a damping resistor and feedback resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by t he manufacturer of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between xcin and xcout following the instructions. open external crystal oscillator circuit external clock input circuit rf (1) mcu (on-chip feedback resistor) mcu (on-chip feedback resistor) free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 85 of 485 rej09b0244-0300 10.4 cpu clock and peri pheral function clock there are a cpu clock to operate the cpu and a peripheral function clock to operate the peripheral functions. refer to figure 10.1 clock generation circuit . 10.4.1 system clock the system clock is the clock source for the cpu and pe ripheral function clocks. either the xin clock or the on-chip oscillator cloc k can be selected. 10.4.2 cpu clock the cpu clock is an operating cl ock for the cpu and watchdog timer. when the cm07 bit in the cm0 register is set to 0 (s ystem clock), the system clock can be divided by 1 (no division), 2, 4, 8, or 16 to produce the cpu clock. use the cm06 bit in the cm0 register and bits cm16 to cm17 in the cm1 register to select the value of the division. when the cm07 bit in the cm0 register is set to 1 (x cin clock), the xcin clock is used for the cpu clock. use the xcin clock while the xcin clock oscillation stabilizes. after reset, the low-speed on-chip oscillator clock divided by 8 provides the cpu clock. when entering stop mode from high-speed clock mode , the cm06 bit is set to 1 (divide-by-8 mode). 10.4.3 peripheral function clo ck (f1, f2, f4, f8, and f32) the peripheral function clock is the operating clock for the peripheral functions. the clock fi (i = 1, 2, 4, 8, and 32) is generated by th e system clock divided by i. the clock fi is used for timers ra, rb, rd, and re, the serial interface and the a/d converter. when the wait instruction is execute d after setting the cm02 bit in the cm0 register to 1 (peripheral function clock stops in wait mode), the clock fi stop. 10.4.4 foco foco is an operating clock for the peripheral functions. foco runs at the same frequency as the on-chip oscill ator clock and can be used as the source for timer ra. when the wait instructio n is executed, the clocks foco does not stop. 10.4.5 foco40m foco40m is used as the count so urce for timer rd. foco40m is generated by the high-speed on-chip oscillator and supplied by setting the fra00 bit to 1. when the wait instructio n is executed, the clock foco40m does not stop. foco40m can be used with supply voltage vcc = 3.0 to 5.5 v. 10.4.6 foco-f foco-f is used as the count source for the a/d conv erter. foco-f is generated by the high-speed on-chip oscillator and supplied by setting the fra00 bit to 1. when the wait instructio n is executed, the clock foco-f does not stop. 10.4.7 foco-s foco-s is an operating clock for the watchdog timer a nd voltage detection circuit. foco-s is supplied by setting the cm14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed on- chip oscillator. when the wait instruction is executed or in count source protect mode of the watchdog timer, foco-s does not stop. 10.4.8 foco128 foco128 is generated by foco divided by 128. the clock foco128 is used for capture signal of timer rd (channel 0). free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 86 of 485 rej09b0244-0300 10.4.9 fc4 and fc32 the clock fc4 and fc32 are used for timer ra and timer re. use fc4 and fc32 while the xcin clock oscillation stabilizes. free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 87 of 485 rej09b0244-0300 10.5 power control there are three power control modes. al l modes other than wait mode and stop mode are referred to as standard operating mode. 10.5.1 standard operating mode standard operating mode is furt her separated into four modes. in standard operating mode, the cpu clock and the peri pheral function clock are supplied to operate the cpu and the peripheral function clocks. power consump tion control is enabled by controlling the cpu clock frequency. the higher the cpu clock frequency, the mo re processing power increases. the lower the cpu clock frequency, the more power consumption decrease s. when unnecessary oscillator circuits stop, power consumption is further reduced. before the clock sources for the cpu clock can be switch ed over, the new clock source needs to be oscillating and stable. if the new clock source is the xin clock or xcin clock, allow suffic ient wait time in a program until oscillation is stabilized before exiting. x: can be 0 or 1, no change in outcome table 10.2 settings and modes of clock associated bits modes ocd register cm1 register cm0 register fra0 register ocd2 cm17, cm16 cm14 cm13 cm07 cm06 cm05 cm04 fra01 fra00 high-speed clock mode no division 0 00b ? 1000 ??? divide-by-2 0 01b ? 1000 ??? divide-by-4 0 10b ? 1000 ??? divide-by-8 0 ?? 1010 ??? divide-by-16 0 11b ? 1000 ??? low-speed clock mode no division ? ??? 1 ?? 1 ?? high-speed on-chip oscillator mode no division 1 00b ?? 00 ?? 11 divide-by-2 1 01b ?? 00 ?? 11 divide-by-4 1 10b ?? 00 ?? 11 divide-by-8 1 ??? 01 ?? 11 divide-by-16 1 11b ?? 00 ?? 11 low-speed on-chip oscillator mode no division 1 00b 0 ? 00 ?? 0 ? divide-by-2 1 01b 0 ? 00 ?? 0 ? divide-by-4 1 10b 0 ? 00 ?? 0 ? divide-by-8 1 ? 0 ? 01 ?? 0 ? divide-by-16 1 11b 0 ? 00 ?? 0 ? free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 88 of 485 rej09b0244-0300 10.5.1.1 high-speed clock mode the xin clock divided by 1 (no division) , 2, 4, 8, or 16 provides the cpu clock. set the cm06 bit to 1 (divide- by-8 mode) when transiting to high-speed on-chip oscill ator mode, low-speed on-chip oscillator mode. if the cm14 bit is set to 0 (low-speed on-c hip oscillator on) or the fra00 bit in the fra0 register is set to 1 (high- speed on-chip oscillator on), foco can be used as timer ra. when the fra00 bit is set to 1, foco40m can be used as timer rd. when the cm14 bit is set to 0 (low-sp eed on-chip oscillator on), fo co-s can be used for the watchdog timer and voltage detection circuit. 10.5.1.2 low-speed clock mode the xcin clock divided by 1 (no division) provides the cpu clock. in this mode, stopping the xin clock and high-speed on-chip oscillator, and setting the fmr47 bit in the fmr4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. when the fra00 bit is set to 1, foco40m can be used as timer rd. when the cm14 bit is set to 0 (low-speed on-chip oscillator on), foco-s can be used for th e watchdog timer and voltage detection circuit. to enter wait mode from low-speed clock mode, setting th e vca20 bit in the vca2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. when enabling reduced internal power consumption using the vca20 bit, follow figure 10.13 procedure for enabling reduced internal pow er consumption using vca20 bit . 10.5.1.3 high-speed on -chip oscillator mode the high-speed on-chip oscillator is used as the on-chip oscillator clock when the fra00 bit in the fra0 register is set to 1 (high-speed on-chip oscillator on) and the fra01 bit in the fra0 register is set to 1. the on- chip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the cpu clock. set the cm06 bit to 1 (divide- by-8 mode) when transiting to high-speed clock mode. if the fra00 bit is set to 1, foco40m can be used as timer rd. when the cm14 bit is set to 0 (low-speed on-chip oscillator on), foco-s can be used for the watchdog timer and voltage detection circuit. 10.5.1.4 low-speed on-chip oscillator mode if the cm14 bit in the cm1 register is set to 0 (low-speed on-chip oscillator on) or the fra01bit in the fra0 register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock. the on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the cpu clock. the on-chip oscillator clock is also the clock source for the peri pheral function clocks. set the cm06 bit to 1 (divide-by-8 mode) when transiting to high-speed clock mode. when the fra00 bit is set to 1, foco40m can be used as timer rd. when the cm14 bit is set to 0 (low-speed on-chip oscillator on), foco-s can be used as the watchdog timer and voltage detection circuit. in this mode, stopping the xin clock and high-speed on-chip oscillator, and setting the fmr47 bit in the fmr4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. to enter wait mode from low-speed on-chip oscillator m ode, setting the vca20 bit in the vca2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. when enabling reduced internal power consumption using the vca20 bit, follow figure 10.13 procedure for enabling reduced internal pow er consumption using vca20 bit . free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 89 of 485 rej09b0244-0300 10.5.2 wait mode since the cpu clock stops in wait mode, the cpu, which operates using the cp u clock, and the watchdog timer, when count source protection mode is disabled, st op. the xin clock, xcin clock, and on-chip oscillator clock do not stop and the peripheral functions using these clocks continue operating. 10.5.2.1 peripheral functi on clock stop function if the cm02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop in wait mode. this reduces power consumption. 10.5.2.2 entering wait mode the mcu enters wait mode when the wait instruction is executed. when the ocd2 bit in the ocd register is set to 1 (on- chip oscillator selected as system clock), set the ocd1 bit in the ocd register to 0 (oscillation stop det ection interrupt disabled) before executing the wait instruction. if the mcu enters wait mode while the ocd1 bit is set to 1 (oscillation stop detection interrupt enabled), current consumption is not reduced because the cpu clock does not stop. 10.5.2.3 pin status in wait mode the i/o port is the status before wait mode was entered is maintained. free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 90 of 485 rej09b0244-0300 10.5.2.4 exiting wait mode the mcu exits wait mode by a reset or a peripheral function interrupt. the peripheral function interrupts are affected by the cm02 bit. when the cm02 bit is set to 0 (peripheral function clock does not stop in wait mode), all periphera l function interrupts can be used to exit wait mode. when the cm02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip oscillator clock can be used to exit wait mode. table 10.3 lists interrupts to exit wait mode and usage conditions. table 10.3 interrupts to exit wait mode and usage conditions interrupt cm02 = 0 cm02 = 1 serial interface interrupt usable when operating with internal or external clock usable when operating with external clock clock synchronous serial i/o with chip select interrupt / i 2 c bus interface interrupt usable in all modes (do not use) key input interrupt usable usable a/d conversion interrupt usable in one-shot mode (do not use) timer ra interrupt usable in all modes can be used if there is no filter in event counter mode. usable by selecting foco or fc32 as count source. timer rb interrupt usable in all modes (do not use) timer rd interrupt usable in all modes usable by selecting foco40m as count source timer re interrupt usable in all modes usable when operating in real time clock mode int interrupt usable usable (int0 to int3 can be used if there is no filter.) voltage monitor 1 interrupt usable usable voltage monitor 2 interrupt usable usable oscillation stop detection interrupt usable (do not use) free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 91 of 485 rej09b0244-0300 figure 10.12 shows the time from wait mode to interrupt routine execution. when using a peripheral function interrupt to exit wait mode, set up the following before executing the wait instruction. (1) set the interrupt priority level in bits ilvl2 to il vl0 in the interrupt control registers of the peripheral function interrupts to be used for exiting wait mode. set bits ilvl2 to ilvl0 of the peripheral function interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled). (2) set the i flag to 1. (3) operate the peripheral function to be used for exiting wait mode. when exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request generation and interrupt routine execution is determined by the settings of the fmstp bit in the fmr0 register and the cm07 bit in the cm0 register, as described in figure 10.12. the cpu clock, when exiting wait mode by a peripheral func tion interrupt, is the same clock as the cpu clock when the wait instru ction is executed. figure 10.12 time from wait mode to interrupt routine execution 0 (system clock) 1 (xcin clock) 0 (system clock) 1 (xcin clock) period of cpu clock 20 cycles same as above same as above same as above following total time is the time from wait mode until an interrupt routine is executed. 0 (flash memory operates) 1 (flash memory stops) wait mode flash memory activation sequence t1 cpu clock restart sequence t2 interrupt sequence t3 interrupt request generated cm07 bit time for interrupt sequence (t3) remarks fmstp bit fmr0 register cm0 register period of system clock 12 cycles + 30 s (max.) period of xcin clock 12 cycles + 30 s (max.) period of system clock 12 cycles period of xcin clock 12 cycles time until flash memory is activated (t1) period of cpu clock 6 cycles same as above same as above same as above time until cpu clock is supplied (t2) free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 92 of 485 rej09b0244-0300 10.5.2.5 reducing intern al power consumption internal power consumption can be reduced by using low-speed clock mode or low-speed on-chip oscillator mode. figure 10.13 shows the procedure for enabling reduced internal power consumption using vca20 bit. when enabling reduced internal power consumption using the vca20 bit, follow figure 10.13 procedure for enabling reduced internal pow er consumption using vca20 bit . figure 10.13 procedure for enabling reduced internal power consumption using vca20 bit notes: 1. execute this routine to handle all interrupts generated in wait mode. however, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the i nterrupt routine. 2. do not set the vca20 bit to 0 with the instruction immediately after setting the vca20 bit to 1. also, do not do the opposit e. 3. when the vca20 bit is set to 1, do not set the cm10 bit to 1 (stop mode). 4. when entering wait mode, follow 10.7.2 wait mode . vca20: bit in vca2 register handling procedure of internal power low consumption enabled by vca20 bit enter low-speed clock mode or low-speed on-chip oscillator mode stop xin clock and high-speed on-chip oscillator clock vca20 1 (internal power low consumption enabled) (2, 3) enter wait mode (4) vca20 0 (internal power low consumption disabled) (2) start xin clock or high-speed on-chip oscillator clock (wait until xin clock oscillation stabilizes) enter high-speed clock mode or high-speed on-chip oscillator mode in interrupt routine vca20 0 (internal power low consumption disabled) (2) start xin clock or high-speed on-chip oscillator clock enter high-speed clock mode or high-speed on-chip oscillator mode enter low-speed clock mode or low-speed on-chip oscillator mode exit wait mode by interrupt stop xin clock and high-speed on-chip oscillator clock vca20 1 (internal power low consumption enabled) (2, 3) interrupt handling completed step (1) step (2) step (3) step (4) step (5) step (6) step (7) step (8) step (5) step (6) step (7) step (8) (wait until xin clock oscillation stabilizes) step (1) step (2) step (3) if it is necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (7) in the interrupt routine. if the high-speed clock or high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine. (note 1) interrupt handling free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 93 of 485 rej09b0244-0300 10.5.3 stop mode since the oscillator circuits stop in stop mode, the cp u clock and peripheral function clock stop and the cpu and peripheral functions that use these clocks stop operat ing. the least power required to operate the mcu is in stop mode. if the voltage applied to the vcc pin is vram or more, the contents of internal ram is maintained. the peripheral functions clocked by external signals continue operating. table 10.4 lists interrupts to exit stop mode and usage conditions. 10.5.3.1 entering stop mode the mcu enters stop mode when the cm10 bit in the cm1 register is set to 1 (all clocks stop). at the same time, the cm06 bit in the cm0 register is set to 1 (d ivide-by-8 mode) and the cm15 bit in the cm1 register is set to 1 (xin clock oscillator circuit drive capacity high). when using stop mode, set bits ocd1 to ocd0 to 00b before entering stop mode. 10.5.3.2 pin status in stop mode the status before wait mode was entered is maintained. however, when the cm13 bit in the cm1 register is set to 1 (xin-xout pins), the xout(p4_7) pin is held ?h?. when the cm13 bit is set to 0 (input ports p4_6 and p4_7), the p4_7(xout pin) is held in input status. table 10.4 interrupts to exit stop mode and usage conditions interrupt usage conditions key input interrupt ? int0 to int3 interrupt can be used if there is no filter timer ra interrupt can be used if there is no filter when external pulse is counted in event counter mode serial interface interrupt when external clock is selected voltage monitor 1 interrupt usable in digital filter disabled mode (vw1c1 bit in vw1c register is set to 1) voltage monitor 2 interrupt usable in digital filter disabled mode (vw2c1 bit in vw2c register is set to 1) free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 94 of 485 rej09b0244-0300 10.5.3.3 exiting stop mode the mcu exits stop mode by a reset or peripheral function interrupt. figure 10.14 shows the time from stop mode to interrupt routine execution. when using a peripheral function interrupt to exit stop mode, set up the following before setting the cm10 bit to 1. (1) set the interrupt priority level in bits ilvl2 to ilvl0 of the peripheral function interrupts to be used for exiting stop mode. set bits ilvl2 to ilvl0 of th e peripheral function interrupts that are not to be used for exiting stop mode to 000b (interrupt disabled). (2) set the i flag to 1. (3) operates the peripheral function to be used for exiting stop mode. when exiting by a peripheral function interrupt, th e interrupt sequence is ex ecuted when an interrupt request is generated and the cpu clock supply is started. if the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral function interrupt, the cpu clock becomes the previous system clock divided by 8. figure 10.14 time from stop mode to interrupt routine execution fmstp bit time until flash memory is activated (t2) t2 0 (flash memory operates) 1 (flash memory stops) period of cpu clock 6 cycles same as above period of cpu clock 20 cycles following total time of t0 to t4 is the time from stop mode until an interrupt handling is executed. cm07 bit period of system clock 12 cycles + 30 s (max.) period of xcin clock 12 cycles + 30 s (max.) period of system clock 12 cycles period of xcin clock 12 cycles same as above same as above same as above same as above same as above time until cpu clock is supplied (t3) time for interrupt sequence (t4) remarks flash memory activation sequence cpu clock restart sequence interrupt sequence oscillation time of cpu clock source used immediately before stop mode stop mode t3 t4 internal power stability time t1 t0 150 s (max.) interrupt request generated 0 (system clock) 1 (xcin clock) 0 (system clock) 1 (xcin clock) fmr0 register cm0 register free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 95 of 485 rej09b0244-0300 figure 10.15 shows the state transitions in power control mode. figure 10.15 state transitions in power control mode cm10 = 1 cpu operation stops stop mode state transitions in power control mode reset wait mode low-speed on-chip oscillator mode cm07 = 0 cm14 = 0 ocd2 = 1 fra01 = 0 high-speed on-chip oscillator mode cm07 = 0 ocd2 = 1 fra00 = 1 fra01 = 1 high-speed clock mode cm05 = 0 cm07 = 0 cm13 = 1 ocd2 = 0 standard operating mode cm14 = 0 ocd2 = 1 fra01 = 0 cm05 = 0 cm13 = 1 ocd2 = 0 cm05 = 0 cm13 = 1 ocd2 = 0 ocd2 = 1 fra00 = 1 fra01 = 1 fra00 = 1 fra01 = 1 cm14 = 0 fra01 = 0 all oscillators stop interrupt wait instruction interrupt cm04, cm05, cm07: bits in cm0 register cm13, cm14: bits in cm1 register ocd2: bit in ocd register fra00, fra01: bits in fra0 register low-speed clock mode cm04 = 1 cm07 = 1 cm07 = 0 cm14 = 0 ocd2 = 1 fra01 = 0 cm04 = 1 cm07 = 1 cm07 = 0 ocd2 = 1 fra00 = 1 fra01 = 1 cm04 = 1 cm07 = 1 cm04 = 1 cm07 = 1 cm05 = 0 cm07 = 0 cm13 = 1 ocd2 = 0 free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 96 of 485 rej09b0244-0300 10.6 oscillation stop detection function the oscillation stop detection function detects the stop of the xin clock oscillating circuit. the oscillation stop detection function can be enabled and disabl ed by the ocd0 bit in the ocd register. table 10.5 lists the specifications of oscillation stop detection function. when the xin clock is the cpu clock sour ce and bits ocd1 to ocd0 are set to 11b, the system is placed in the following state if the xin clock stops. ? ocd2 bit in ocd register = 1 (on-chip oscillator clock selected) ? ocd3 bit in ocd register = 1 (xin clock stops) ? cm14 bit in cm1 register = 0 (low-s peed on-chip oscillator oscillates) ? oscillation stop detection interrupt request is generated. 10.6.1 how to use oscillat ion stop detection function ? the oscillation stop detection inte rrupt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt. wh en using the oscillation stop detection interrupt and watchdog timer interrupt, the interrupt source needs to be determined. table 10.6 lists the determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, and voltage monitor 2 interrupts. figure 10.17 shows an example of determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, or voltage monitor 2 interrupt. ? when the xin clock restarts after os cillation stop, switch the xin clock to the clock source of the cpu clock and peripheral functions by a program. figure 10.16 shows the procedure for switching clock source from low-speed on-chip oscillator to xin clock. ? to enter wait mode while using the oscillation stop detection function, set the cm02 bit to 0 (peripheral function clock does not stop in wait mode). ? since the oscillation stop detection function is a f unction for cases where the xin clock is stopped by an external cause, set bits ocd1 to ocd0 to 00b when the xin clock stops or is started by a program, (stop mode is selected or the cm05 bit is changed). ? this function cannot be used when the xin clock frequency is 2 mhz or below. in this case, set bits ocd1 to ocd0 to 00b. ? to use the low-speed on-chip oscillator clock for th e cpu clock and clock sources of peripheral functions after detecting the oscillation stop, set the fra01 bit in the fra0 register to 0 (low-speed on-chip oscillator selected) and bits ocd1 to ocd0 to 11b. to use the high-speed on-chip oscillator clock for th e cpu clock and clock sources of peripheral functions after detecting the oscillation stop, set the fra00 bit to 1 (high-speed on-chip oscillator on) and the fra01 bit to 1 (high-speed on-chip oscillator selected) and then set bits ocd1 to ocd0 to 11b. table 10.5 specifications of oscillation stop detection function item specification oscillation stop detection clock and frequency bandwidth f(xin) 2 mhz enabled condition for oscillation stop detection function set bits ocd1 to ocd0 to 11b operation at oscillation stop detection osc illation stop detection interrupt is generated free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 97 of 485 rej09b0244-0300 figure 10.16 procedure for switching clock sour ce from low-speed on-chip oscillator to xin clock table 10.6 determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, and voltage monitor 2 interrupts generated inte rrupt source bit showing interrupt cause oscillation stop detection ((a) or (b)) (a) ocd3 bit in ocd register = 1 (b) ocd1 to ocd0 bits in ocd register = 11b and ocd2 bit = 1 watchdog timer vw2c3 bit in vw2c register = 1 voltage monitor 1 vw1c2 bit in vw1c register = 1 voltage monitor 2 vw2c2 bit in vw2c register = 1 ocd3 to ocd0: bits in ocd register switch to xin clock multiple confirmations that ocd3 bit is set to 0 (xin clock oscillates) ? set ocd1 to ocd0 bits to 00b set ocd2 bit to 0 (select xin clock) end yes no free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 98 of 485 rej09b0244-0300 figure 10.17 example of determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, or voltage monitor 2 interrupt interrupt sources judgment ocd3 = 1 ? (xin clock stopped) ocd1 = 1 (oscillation stop detection interrupt enabled) and ocd2 = 1 (on-chip oscillator clock selected as system clock) ? vw2c3 = 1 ? (watchdog timer underflow) vw2c2 = 1 ? (passing vdet2) to oscillation stop detection interrupt routine to voltage monitor 1 interrupt routine to voltage monitor 2 interrupt routine to watchdog timer interrupt routine no yes no yes no yes no yes note: 1. this disables multiple osc illation stop detec tion interrupts. ocd1 to ocd3: bits in ocd register vw2c2, vw2c3: bits in vw2c register set ocd1 bit to 0 (oscillation stop detection interrupt disabled). (1) free datasheet http:///
r8c/24 group, r8c/25 group 10. clock generation circuit rev.3.00 feb 29, 2008 page 99 of 485 rej09b0244-0300 10.7 notes on clock generation circuit 10.7.1 stop mode when entering stop mode, set the fmr01 bit in the fmr0 register to 0 (cpu rewrite mode disabled) and the cm10 bit in the cm1 register to 1 (stop mode). an instruction queue pre-reads 4 bytes from the instruction which sets the cm10 bit to 1 (stop mode) and the program stops. insert at least 4 nop instructions following the jmp.b instruction after the instruction which sets the cm10 bit to 1. ? program example to enter stop mode bclr 1,fmr0 ; cpu rewrite mode disabled bset 0,prcr ; protect disabled fset i ; enable interrupt bset 0,cm1 ; stop mode jmp.b label_001 label_001 : nop nop nop nop 10.7.2 wait mode when entering wait mode, set the fmr01 bit in the fm r0 register to 0 (cpu re write mode disabled) and execute the wait instruction. an instruction queue pre-reads 4 bytes from the wait instruction and the program stops. insert at least 4 nop instructions after the wait instruction. ? program example to execu te the wait instruction bclr 1,fmr0 ; cpu rewrite mode disabled fset i ; enable interrupt wait ; wait mode nop nop nop nop 10.7.3 oscillation stop detection function since the oscillation stop detection function cannot be used if the xin clock frequency is 2 mhz or below, set bits ocd1 to ocd0 to 00b. 10.7.4 oscillation circuit constants ask the manufacturer of the oscillator to specify th e best oscillation circuit constants for your system. to use this mcu with supply voltage below vcc = 2.7 v, it is recommended to set the cm11 bit in the cm1 register to 1 (on-chip feedback resistor disabled), the cm15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally. free datasheet http:///
r8c/24 group, r8c/25 group 11. protection rev.3.00 feb 29, 2008 page 100 of 485 rej09b0244-0300 11. protection the protection function protects important registers from be ing easily overwritten when a program runs out of control. figure 11.1 shows the prcr register. the register s protected by the prcr register are listed below. ? registers protected by prc0 bit: regist ers cm0, cm1, ocd, fra0, fra1, and fra2 ? registers protected by prc1 bit: registers pm0 and pm1 ? registers protected by prc2 bit: pd0 register ? registers protected by prc3 bit: registers vca2, vw0c, vw1c, and vw2c figure 11.1 prcr register protect registe r symbol address after reset prcr 000ah 00h bit symbol bit name function rw note: 1. this bit is set to 0 after w riting 1 to the prc2 bit and executing a w rite to any address. since the other bits are not set to 0, set them to 0 by a program. prc2 protect bit 2 writing to the pd0 register is enabled. 0 : disables w riting 1 : enables w riting (1) rw rw ? (b5-b4) reserved bits set to 0. rw prc0 rw prc1 rw protect bit 0 writing to registers cm0, cm1, ocd, fra0, fra1, and fra2 is enabled. 0 : disables w riting 1 : enables w riting protect bit 1 writing to registers pm0 and pm1 is enabled. 0 : disables w riting 1 : enables w riting 00 b3 b2 b1 b0 b7 b6 b5 b4 ro prc3 protect bit 3 writing to registers vca2, vw0c, vw1c, and vw2c is enabled. 0 : disables w riting 1 : enables w riting ? (b7-b6) reserved bits when read, the content is 0. free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 101 of 485 rej09b0244-0300 12. interrupts 12.1 interrupt overview 12.1.1 types of interrupts figure 12.1 shows the types of interrupts. figure 12.1 types of interrupts ? maskable interrupts: the interrupt enable flag (i flag) enables or disables these interrupts. the interrupt priority order can be changed based on the interrupt priority level. ? non-maskable interrupts: the interr upt enable flag (i flag) does not enable or disabl e these interrupts. the interrupt priority order cannot be changed based on interrupt priority level. interrupts (non-maskable interrupts) hardware software (non-maskable interrupts) (maskable interrupts) special peripheral functions (1) undefined instructi on (und instruction) overflow (into instruction) brk instruction int instruction watchdog timer oscillation stop detection voltage monitor 1 voltage monitor 2 single step (2) address break (2) address match notes: 1. peripheral function interrupts in the mcu are used to generate peripheral interrupts. 2. do not use this interrupt. this is for use with development tools only. free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 102 of 485 rej09b0244-0300 12.1.2 software interrupts a software interrupt is generated when an instruc tion is executed. software interrupts are non-maskable. 12.1.2.1 undefined instruction interrupt the undefined instruction interrupt is generated when the und instruction is executed. 12.1.2.2 overflow interrupt the overflow interrupt is generated when the o flag is set to 1 (arithmetic operation overflow) and the into instruction is executed. inst ructions that set the o flag are: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, and sub. 12.1.2.3 brk interrupt a brk interrupt is generated when the brk instruction is executed. 12.1.2.4 int instruction interrupt an int instruction interrupt is generated when the int instruction is executed. th e int instruction can select software interrupt numbers 0 to 63. so ftware interrupt numbers 3 to 31 are assigned to the peripheral function interrupt. therefore, the mcu executes the same interrupt routine when the int instruction is executed as when a peripheral function interrupt is generated. for so ftware interrupt numbers 0 to 31, the u flag is saved to the stack during instruction execution and the u flag is set to 0 (isp selected) befo re the interrupt sequence is executed. the u flag is restor ed from the stack when retu rning from the interrupt routine. for software interrupt numbers 32 to 63, the u flag does not change state du ring instruction execution, a nd the selected sp is used. free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 103 of 485 rej09b0244-0300 12.1.3 special interrupts special interrupts are non-maskable. 12.1.3.1 watchdog timer interrupt the watchdog timer interrupt is generated by the watchdog timer. for details, refer to 13. watchdog timer . 12.1.3.2 oscillation stop detection interrupt the oscillation stop detection interrupt is generated by th e oscillation stop detection function. for details of the oscillation stop detection function, refer to 10. clock generation circuit . 12.1.3.3 voltage monitor 1 interrupt the voltage monitor 1 interrupt is generated by the voltage detection circuit. for details of the voltage detection circuit, refer to 6. voltage detection circuit . 12.1.3.4 voltage monitor 2 interrupt the voltage monitor 2 interrupt is generated by the voltage detection circuit. for details of the voltage detection circuit, refer to 6. voltage detection circuit . 12.1.3.5 single-step interrupt, and address break interrupt do not use these interrupts. they are for use by development tools only. 12.1.3.6 address match interrupt the address match interrupt is generated immediately be fore executing an instruction that is stored at an address indicated by registers rmad0 to rmad1 when the aier0 or aier1 bit in the aier register is set to 1 (address match interrupt enable). for details of the address match interrupt, refer to 12.4 address match interrupt . 12.1.4 peripheral function interrupt the peripheral function interrupt is generated by the in ternal peripheral function of the mcu and is a maskable interrupt. refer to table 12.2 relocatable vector tables for sources of the peripheral function interrupt. for details of peripheral functions, refer to the de scriptions of individual peripheral functions. free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 104 of 485 rej09b0244-0300 12.1.5 interrupts and interrupt vectors there are 4 bytes in each vector. set the starting addre ss of an interrupt routine in each interrupt vector. when an interrupt request is acknowledged, the cpu branches to the address set in the co rresponding interrupt vector. figure 12.2 shows an interrupt vector. figure 12.2 interrupt vector 12.1.5.1 fixed vector tables the fixed vector tables are allocated addresses 0ffdch to 0ffffh. table 12.1 lists the fixed vector ta bles. the vector addresses (h) of fi xed vectors are used by the id code check function. for details, refer to 19.3 functions to prevent rewriting of flash memory . note: 1. do not use these interrupts. they are for use by development tools only. table 12.1 fixed vector tables interrupt source vector addresses address (l) to (h) remarks reference undefined instruction 0ffdch to 0ffdfh interrupt on und instruction r8c/tiny series software manual overflow 0ffe0h to 0ffe3h interrupt on into instruction brk instruction 0ffe4h to 0ffe7h if the content of address 0ffe7h is ffh, program execution starts from the address shown by the vector in the relocatable vector table. address match 0ffe8h to 0ffebh 12.4 address match interrupt single step (1) 0ffech to 0ffefh watchdog timer, oscillation stop detection, voltage monitor 1, voltage monitor 2 0fff0h to 0fff3h 13. watchdog timer 10. clock generation circuit 6. voltage detection circuit address break (1) 0fff4h to 0fff7h (reserved) 0fff8h to 0fffbh reset 0fffch to 0ffffh 5. resets vector address (l) vector address (h) msb lsb low address mid address high address 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 105 of 485 rej09b0244-0300 12.1.5.2 relocatable vector tables the relocatable vector tables occupy 256 bytes beginning from the starting address set in the intb register. table 12.2 lists the relocatable vector tables. notes: 1. these addresses are relative to those in the intb register. 2. the iicsel bit in the pmr register switches functions. 3. the i flag does not disable these interrupts. table 12.2 relocatable vector tables interrupt source vector addresses (1) address (l) to address (h) software interrupt number interrupt control register reference brk instruction (3) +0 to +3 (0000h to 0003h) 0 ? r8c/tiny series software manual (reserved) 1 to 2 ?? (reserved) 3 to 7 ?? timer rd (channel 0) +32 to +35 (0020h to 0023h) 8 trd0ic 14.3 timer rd timer rd (channel 1) +36 to +39 (0024h to 0027h) 9 trd1ic timer re +40 to +43 (0028h to 002bh) 10 treic 14.4 timer re (reserved) 11 to 12 ?? key input +52 to +55 (0034h to 0037h) 13 kupic 12.3 key input interrupt a/d +56 to +59 (0038h to 003bh) 14 adic 18. a/d converter clock synchronous serial i/o with chip select / i 2 c bus interface (2) +60 to +63 (003ch to 003fh) 15 ssuic/iicic 16.2 clock synchronous serial i/o with chip select (ssu), 16.3 i 2 c bus interface (reserved) 16 ?? uart0 transmit +68 to +71 (0044h to 0047h) 17 s0tic 15. serial interface uart0 receive +72 to +75 (0048h to 004bh) 18 s0ric uart1 transmit +76 to +79 (004ch to 004fh) 19 s1tic uart1 receive +80 to +83 (0050h to 0053h) 20 s1ric int2 +84 to +87 (0054h to 0057h) 21 int2ic 12.2 int interrupt timer ra +88 to +91 (0058h to 005bh) 22 traic 14.1 timer ra (reserved) 23 ?? timer rb +96 to +99 (0060h to 0063h) 24 trbic 14.2 timer rb int1 +100 to +103 (0064h to 0067h) 25 int1ic 12.2 int interrupt int3 +104 to +107 (0068h to 006bh) 26 int3ic (reserved) 27 ?? (reserved) 28 ?? int0 +116 to +119 (0074h to 0077h) 29 int0ic 12.2 int interrupt (reserved) 30 ?? (reserved) 31 ?? software interrupt (3) +128 to +131 (0080h to 0083h) to +252 to +255 (00fch to 00ffh) 32 to 63 ? r8c/tiny series software manual free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 106 of 485 rej09b0244-0300 12.1.6 interrupt control the following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. the explanation does not apply to nonmaskable interrupts. use the i flag in the flg register, ip l, and bits ilvl2 to ilvl0 in each in terrupt control regi ster to enable or disable maskable interrupts. wh ether an interrupt is request ed is indicated by the ir bit in each interrupt control register. figure 12.3 shows the interrupt control register, figur e 12.4 shows registers trd0ic, trd1ic, ssuic, and iicic and figure 12.5 shows the intiic register. figure 12.3 interrupt control register interrupt control register (2) address after reset 004ah xxxxx000b 004dh xxxxx000b 004eh xxxxx000b 0051h xxxxx000b 0052h xxxxx000b 0053h xxxxx000b 0054h xxxxx000b 0056h xxxxx000b 0058h xxxxx000b bit symbol function rw notes: 1. 2. only 0 can be w ritten to the ir bit. do not w rite 1. ir 0 : requests no interrupt 1 : requests interrupt rw (1) ? (b7-b4) ? nothing is assigned. if necessary, set to 0. when read, the content is undefined. rw b2 b1 b0 0 0 0 : level 0 (interrupt disable) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 ilv l1 rw ilv l2 rw rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. ref er to 12.6.5 changing interrupt control register contents . b7 b6 b5 b4 b3 b2 b1 b0 symbol bit name interrupt priority level select bits interrupt request bit ilv l0 trbic s1tic s1ric tra ic treic kupic adic s0tic s0ric free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 107 of 485 rej09b0244-0300 figure 12.4 registers trd0ic, trd1ic, ssuic, and iicic interrupt control register (1) address after reset 0048h xxxxx000b 0049h xxxxx000b 004fh xxxxx000b bit symbol function rw notes: 1. 2. symbol trd1ic trd0ic ssuic/iicic (2) bit name interrupt priority level select bits interrupt request bit nothing is assigned. if necessary, set to 0. when read, the content is undefined. the iicsel bit in the pmr register sw itches functions. rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. ref er to 12.6.5 changing interrupt control register contents . b7 b6 b5 b4 b3 b2 b1 b0 ilv l0 rw b2 b1 b0 0 0 0 : level 0 (interrupt disable) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 ilv l1 rw ilv l2 rw ir 0 : requests no interrupt 1 : requests interrupt ro ? (b7-b4) ? free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 108 of 485 rej09b0244-0300 figure 12.5 intiic register inti interrupt control register (i=0 to 3) (2) symbol address after reset int2ic 0055h xx00x000b int1ic 0059h xx00x000b int3ic 005ah xx00x000b int0ic 005dh xx00x000b bit symbol bit name function rw notes: 1. 2. 3. 4. rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. ref er to 12.6.5 changing interrupt control register contents . if the intipl bit in the inten register is set to 1 (both edges), set the pol bit to 0 (selects fa lling edge). the ir bit may be set to 1 (requests interrupt) w hen the pol bit is rew ritten. refer to 12.6.4 changing interrupt sources. b7 b6 b5 b4 b3 b2 b1 b0 0 ilv l0 rw interrupt priority level select bits b2 b1 b0 0 0 0 : level 0 (interrupt disable) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 ilv l1 rw ilv l2 rw ir interrupt request bit 0 : requests no interrupt 1 : requests interrupt rw (1) pol polarity sw itch bit (4) 0 : selects falling edge 1 : selects rising edge (3) rw ? (b5) reserved bit set to 0. rw ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is undefined. only 0 can be w ritten to the ir bit. (do not w rite 1.) free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 109 of 485 rej09b0244-0300 12.1.6.1 i flag the i flag enables or disables maskab le interrupts. setting the i flag to 1 (enabled) enables maskable interrupts. setting the i flag to 0 (disabled) disables all maskable interrupts. 12.1.6.2 ir bit the ir bit is set to 1 (interrupt requested) when an interrupt request is generated. then, when the interrupt request is acknowledged and th e cpu branches to the corr esponding interrupt vector, the ir bit is set to 0 (= interrupt not requested). the ir bit can be set to 0 by a program. do not write 1 to this bit. however, the ir bit operations of the timer rd interrupt, clock synchronous serial i/o with chip select interrupt and the i 2 c bus interface interrupt are different. refer to 12.5 timer rd interrupt, clock synchronous serial i/o with chip select interrupts, and i 2 c bus interface interrupt (interrupts with multiple interrupt request sources) . 12.1.6.3 bits ilvl2 to ilvl0 and ipl interrupt priority levels can be set using bits ilvl2 to ilvl0. table 12.3 lists the settings of interrupt priority le vels and table 12.4 lists th e interrupt priority levels enabled by ipl. the following are conditions under which an interrupt is acknowledged: ?i flag = 1 ? ir bit = 1 ? interrupt priority level > ipl the i flag, ir bit, bits ilvl2 to il vl0, and ipl are independ ent of each other. they do not affect one another. table 12.3 settings of interrupt priority levels ilvl2 to ilvl0 bits interrupt priority level priority order 000b level 0 (interrupt disabled) ? 001b level 1 low 010b level 2 011b level 3 100b level 4 101b level 5 110b level 6 111b level 7 high table 12.4 interrupt priority levels enabled by ipl ipl enabled interrupt priority levels 000b interrupt level 1 and above 001b interrupt level 2 and above 010b interrupt level 3 and above 011b interrupt level 4 and above 100b interrupt level 5 and above 101b interrupt level 6 and above 110b interrupt level 7 and above 111b all maskable interrupts are disabled free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 110 of 485 rej09b0244-0300 12.1.6.4 interrupt sequence an interrupt sequence is performed between an inte rrupt request acknowledgement and interrupt routine execution. when an interrupt request is generated while an instruct ion is being executed, the cpu determines its interrupt priority level after the instruction is completed. the cpu starts the interrupt sequence from the following cycle. however, for the smovb, smovf, sstr, or rmpa instruct ion if an interrupt request is generated while the instruction is being executed, the mcu suspends the instruction to start the interrupt sequence. the interrupt sequence is performed as indicated below. figure 12.6 shows the time requir ed for executing interrupt sequence. (1) the cpu gets interrupt information (interrupt num ber and interrupt request level) by reading address 00000h. the ir bit for the corresponding interr upt is set to 0 (interrupt not requested). (2) (2) the flg register is saved to a temporary register (1) in the cpu immediately before entering the interrupt sequence. (3) the i, d and u flags in the flg register are set as follows: the i flag is set to 0 (interrupts disabled). the d flag is set to 0 (single-step interrupt disabled). the u flag is set to 0 (isp selected). however, the u flag does not change state if an in t instruction for software interrupt number 32 to 63 is executed. (4) the cpu?s internal temporary register (1) is saved to the stack. (5) the pc is saved to the stack. (6) the interrupt priority level of the acknowledged interrupt is set in the ipl. (7) the starting address of the interrupt routine set in the interrupt vector is stored in the pc. after the interrupt sequence is completed, instructions are executed from the starting address of the interrupt routine. figure 12.6 time required for executing interrupt sequence notes: 1. this register cannot be accessed by the user. 2. refer to 12.5 timer rd interrupt, clock synchronous serial i/o with chip select interrupts, and i 2 c bus interface interrupt (interrupts with multiple interrupt request sources) for the ir bit operations of the timer rd interrupt, clock synchronous serial i/o with chip select interrupt, and the i 2 c bus interface interrupt. 12345678910 11 12 13 14 15 16 17 18 19 20 cpu clock address bus data bus rd wr address 0000h undefined undefined undefined interrupt information sp-2 sp-1 sp-4 sp-3 vec vec+1 vec+2 pc sp-2 contents sp-1 contents sp-4 contents sp-3 contents vec contents vec+1 contents vec+2 contents the indeterminate state depends on the instruction queue buffer. a read cycle occurs when the instruction queue buffer is ready to acknowledge instructions. free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 111 of 485 rej09b0244-0300 12.1.6.5 interrupt response time figure 12.7 shows the interrupt response time. the interr upt response time is the period between an interrupt request generation and the execution of the first instructio n in the interrupt routine. the interrupt response time includes the period between interrup t request generation and the completion of execution of the instruction (refer to (a) in figure 12.7 ) and the period required to perform the in terrupt sequence (20 cycles, refer to (b) in figure 12.7 ). figure 12.7 interrupt response time 12.1.6.6 ipl change when inte rrupt request is acknowledged when an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the ipl. when a software interrupt or special interrupt request is acknowledged, the level listed in table 12.5 is set in the ipl. table 12.5 lists the ipl value when software or special interrupt is acknowledged. table 12.5 ipl value when software or special interrupt is acknowledged interrupt source value set in ipl watchdog timer, oscillation stop detection, voltage monitor 1, voltage monitor 2, address break 7 software, address match, single-step not changed interrupt request is generated. interrupt request is acknowledged. instruction interrupt sequence instruction in interrupt routine time (a) 20 cycles (b) interrupt response time (a) period between interrupt request generation and the completion of execution of an instruction. the length of time varies depending on the instruction being executed. the divx instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 21 cycles for address match and single-step interrupts. free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 112 of 485 rej09b0244-0300 12.1.6.7 saving a register in the interrupt sequence, the flg regi ster and pc are saved to the stack. after an extended 16 bits, 4 high-order bits in the pc and 4 high-order (ipl) and 8 low-order bits in the flg register, are saved to the stack, the 16 low-order bits in the pc are saved. figure 12.8 shows the stack state before and after acknowledgement of interrupt request. the other necessary registers are saved by a program at the beginning of the interrupt routine. the pushm instruction can save several registers in the register bank being currently used (1) with a single instruction. note: 1. selectable from registers r0, r1, r2, r3, a0, a1, sb, and fb. figure 12.8 stack state before and after acknowledgement of interrupt request the register saving operation, which is performed as part of the interrupt se quence, saved in 8 bits at a time in four steps. figure 12.9 shows the register saving operation. figure 12.9 register saving operation stack [sp] sp value before interrupt is generated previous stack contents lsb msb address previous stack contents m ? 4 m ? 3 m ? 2 m ? 1 m m+1 stack state before interrupt request is acknowledged [sp] new sp value previous stack contents lsb msb previous stack contents m m+1 stack state after interrupt request is acknowledged pcl pcm flgl flgh pch m ? 4 m ? 3 m ? 2 m ? 1 stack address pch : 4 high-order bits of pc pcm : 8 middle-order bits of pc pcl : 8 low-order bits of pc flgh : 4 high-order bits of flg flgl : 8 low-order bits of flg note: 1. when executing software number 32 to 63 int instructions, this sp is specified by the u flag. otherwise it is isp. stack completed saving registers in four operations. address [sp] ? 5 [sp] pcl pcm flgl flgh pch (3) (4) (1) (2) saved, 8 bits at a time sequence in which order registers are saved note: 1. [sp] indicates the initial value of the sp when an interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. when executing software number 32 to 63 int instructions, this sp is specified by the u flag. otherwise it is isp. [sp] ? 4 [sp] ? 3 [sp] ? 2 [sp] ? 1 pch : 4 high-order bits of pc pcm : 8 middle-order bits of pc pcl : 8 low-order bits of pc flgh : 4 high-order bits of flg flgl : 8 low-order bits of flg free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 113 of 485 rej09b0244-0300 12.1.6.8 returning from an interrupt routine when the reit instruction is executed at the end of an interrupt rout ine, the flg register and pc, which have been saved to the stack, are automatical ly restored. the program, that was running before the interrupt request was acknowledged, starts running again. restore registers saved by a program in an interrupt routine using the popm instruction or others before executing the reit instruction. 12.1.6.9 interrupt priority if two or more interrupt requests are generated while a single instruction is being executed, the interrupt with the higher priority is acknowledged. set bits ilvl2 to ilvl0 to select the desired priority level for maskable interrupts (peripheral functions). however, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, and the higher priority interrupts acknowledged. the priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set by hardware. figure 12.10 shows the priority levels of hardware interrupts. the interrupt priority does not affect software interrupts. the mcu jumps to the interrupt routine when the instruction is executed. figure 12.10 priority levels of hardware interrupts address break watchdog timer oscillation stop detection voltage monitor 1 voltage monitor 2 peripheral function single step address match high low reset free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 114 of 485 rej09b0244-0300 12.1.6.10 interrupt prio rity judgement circuit the interrupt priority judgement circuit selects the hi ghest priority interrupt, as shown in figure 12.11. figure 12.11 interrupt priority level judgement circuit uart1 receive uart0 receive a/d conversion ssu / i 2 c bus (1) key input ipl lowest highest priority of peripheral function interrupts (if priority levels are same) interrupt request level judgment output signal interrupt request acknowledged i flag address match watchdog timer oscillation stop detection voltage monitor 1 note: 1. the iicsel bit in the pmr register switches functions. uart0 transmit int2 uart1 transmit timer re timer rd0 timer rd1 int0 int1 int3 timer rb timer ra priority level of interrupt level 0 (default value) voltage monitor 2 free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 115 of 485 rej09b0244-0300 12.2 int interrupt 12.2.1 inti interrupt (i = 0 to 3) the inti interrupt is generated by an inti input. when using the inti interrupt, the intien bit in the inten register is set to 1 (enable). the edge polarity is sel ected using the intipl bit in the inten register and the pol bit in the intiic register. inputs can be passed through a digital filter with three different sampling clocks. the int0 pin is shared with the pulse output forced cutoff of timer rd and the external trigger input of timer rb. figure 12.12 shows the inten register. figure 12.13 shows the intf register. figure 12.12 inten register external input enable register symbol address after reset inten 00f9h 00h bit symbol bit name function rw int0 _ ____ input enable bit int0 _ ____ input polarity select bit (1,2) int1 _ ____ input enable bit int1 _ ____ input polarity select bit (1,2) int2 _ ____ input enable bit int2 _ ____ input polarity select bit (1,2) int3 _ ____ input enable bit int3 _ ____ input polarity select bit (1,2) notes: 1. 2. 0 : disable 1 : enable rw int2en 0 : disable 1 : enable rw int2pl 0 : one edge 1 : both edges rw when setting the intipl bit (i = 0 to 3) to 1 (both edges), set the pol bit in the intiic register to 0 (selects fa lling edge). the ir bit in the intiic register may be set to 1 (requests interrupt) w hen the intipl bit is rew ritten. refer to 12.6.4 changing interrupt sources. 0 : disable 1 : enable 0 : one edge 1 : both edges 0 : one edge 1 : both edges rw int0pl rw int1en 0 : disable 1 : enable rw int0en rw int1pl 0 : one edge 1 : both edges rw int3en int3pl b3 b2 b1 b0 b7 b6 b5 b4 free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 116 of 485 rej09b0244-0300 figure 12.13 intf register int0 _ ______ input filter select register symbol address after reset intf 00fah 00h bit symbol bit name function rw int0 _____ input f ilter select bits int1 _____ input f ilter select bits int2 _____ input f ilter select bits int3 _____ input f ilter select bits int0f0 rw int0f1 rw b7 b6 b5 b4 b3 b2 b1 b0 rw b1 b0 0 0 : no filter 0 1 : filter w ith f1 sampling 1 0 : filter w ith f8 sampling 1 1 : filter w ith f32 sampling rw b7 b6 0 0 : no filter 0 1 : filter w ith f1 sampling 1 0 : filter w ith f8 sampling 1 1 : filter w ith f32 sampling int3f1 int3f0 int1f0 b3 b2 0 0 : no filter 0 1 : filter w ith f1 sampling 1 0 : filter w ith f8 sampling 1 1 : filter w ith f32 sampling rw int1f1 rw int2f0 b5 b4 0 0 : no filter 0 1 : filter w ith f1 sampling 1 0 : filter w ith f8 sampling 1 1 : filter w ith f32 sampling rw int2f1 rw free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 117 of 485 rej09b0244-0300 12.2.2 inti input filter (i = 0 to 3) the inti input contains a digital filter. the sampling clock is selected by bits intif1 to intif0 in the intf register. the inti level is sampled every sampling clock cycle and if the sampled input level matches three times, the ir bit in the intiic register is set to 1 (interrupt requested). figure 12.14 shows the configuration of inti input filter. figure 12.15 show s an operating example of inti input filter. figure 12.14 configuration of inti input filter figure 12.15 operating example of inti input filter intif0, intif1: bits in intf register intien, intipl: bits in inten register i = 0 to 3 = 01b inti port direction register (1) sampling clock digital filter (input level matches 3x) inti interrupt = 10b = 11b f32 f8 f1 intif1 to intif0 intien other than intif1 to intif0 = 00b = 00b intipl = 0 intipl = 1 note: 1. int0: port p4_5 direction register int1: port p1_5 direction register when using the p1_5 pin port p1_7 direction register when using the p1_7 pin int2: port p6_6 direction register int3: port p6_7 direction register both edges detection circuit inti input sampling timing ir bit in intiic register set to 0 by a program this is an operation example when bits intif1 to intif0 in the intif register are set to 01b, 10b, or 11b (digital filter enabled). i = 0 to 3 free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 118 of 485 rej09b0244-0300 12.3 key input interrupt a key input interrupt request is generated by one of the input edges of pins k10 to k13 . the key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. the kiien (i = 0 to 3) bit in the kien register can select whether or not the pins are used as kii input. the kiipl bit in the kien register can select the input polarity. when inputting ?l? to the kii pin which sets the kiipl bit to 0 (falling edge), the input of the other pins k10 to k13 is not detected as interrupts. also, when inputting ?h? to the kii pin, which sets the kiipl bit to 1 (rising edge), the input of the other pins k10 to k13 is not detected as interrupts. figure 12.16 shows a block diagram of key input interrupt. figure 12.16 block diagram of key input interrupt ki3 pull-up transistor ki2 pull-up transistor ki3pl = 0 ki3pl = 1 pd1_3 bit ki3en bit pu02 bit in pur0 register pd1_3 bit in pd1 register kupic register interrupt control circuit key input interrupt request ki2pl = 0 ki2pl = 1 pd1_2 bit ki2en bit ki1 pull-up transistor ki1pl = 0 ki1pl = 1 pd1_1 bit ki1en bit ki0 pull-up transistor ki0pl = 0 ki0pl = 1 pd1_0 bit ki0en bit ki0en, ki1en, ki2en, ki3en, ki0pl, ki1pl, ki2pl, ki3pl: bits in kien register pd1_0, pd1_1, pd1_2, pd1_3: bits in pd1 register free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 119 of 485 rej09b0244-0300 figure 12.17 kien register key input enable register (1) symbol address after reset kien 00fbh 00h bit symbol bit name function rw note: 1. ki3 input polarity select bit 0 : falling edge 1 : rising edge ki0en rw ki0pl rw ki0 input enable bit 0 : disable 1 : enable rw 0 : disable 1 : enable the ir bit in the kupic register may be set to 1 (requests interrupt) w hen the kien register is rew ritten. ref er to 12.6.4 changing interrupt sources. ki1en rw ki3en ki3 input enable bit ki3pl rw ki2pl ki2 input polarity select bit 0 : falling edge 1 : rising edge b1 b0 b7 b6 b5 b4 b3 b2 rw ki2en rw ki1pl ki1 input polarity select bit 0 : falling edge 1 : rising edge ki2 input enable bit 0 : disable 1 : enable rw ki0 input polarity select bit 0 : falling edge 1 : rising edge ki1 input enable bit 0 : disable 1 : enable free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 120 of 485 rej09b0244-0300 12.4 address match interrupt an address match interrupt request is generated immediat ely before execution of the instruction at the address indicated by the rmadi register (i = 0 or 1). this inte rrupt is used as a break fu nction by the debugger. when using the on-chip debugger, do not set an address match interrupt (registers of ai er, rmad0, and rmad1 and fixed vector tables) in a user system. set the starting address of any instruction in the rmadi register. bits aier0 and aier 1 in the aier0 register can be used to select enable or disable of the interrupt. the i flag and ipl do not affect the address match interrupt. the value of the pc (refer to 12.1.6.7 saving a register for the value of the pc) which is saved to the stack when an address match interrupt is acknowledged varies depending on the inst ruction at the addre ss indicated by the rmadi register. (the appropriate return address is not saved on the stack.) when returning from the address match interrupt, return by one of the following means: ? change the content of the stack and use the reit instruction. ? use an instruction such as pop to restore the stack as it was before the interrupt request was acknowledged. then use a jump instruction. table 12.6 lists the values of pc saved to stack when address match interrupt is acknowledged. figure 12.18 shows registers aier and rmad0 to rmad1. notes: 1. refer to the 12.1.6.7 saving a register for the pc value saved. 2. operation code: refer to the r8c/tiny series software manual (rej09b0001). chapter 4. instruction code/number of cycles contains diagrams showing operation code below each syntax. operation code is shown in the bold frame in the diagrams. table 12.6 values of pc saved to stack wh en address match interrupt is acknowledged address indicated by rmadi register (i = 0 or 1) pc value saved (1) ? instruction with 2-byte operation code (2) ? instruction with 1-byte operation code (2) add.b:s #imm8,dest sub.b:s #i mm8,dest and.b:s #imm8,dest or.b:s #imm8,dest mov.b: s #imm8,dest stz #imm8,dest stnz #imm8,dest s tzx #imm81,#imm82,dest cmp.b:s #imm8,dest pushm src popm dest jmps #imm8 jsrs #imm8 mov.b:s #imm,dest (however, dest = a0 or a1) address indicated by rmadi register + 2 ? instructions other than th e above address indicated by rmadi register + 1 table 12.7 correspondence between address match interr upt sources and asso ciated registers address match interrupt source address match inte rrupt enable bit address match interrupt register address match interrupt 0 aier0 rmad0 address match interrupt 1 aier1 rmad1 free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 121 of 485 rej09b0244-0300 figure 12.18 registers ai er and rmad0 to rmad1 a ddress match interrupt enable registe r symbol address after reset aier 0013h 00h bit symbol bit name function rw aier1 address match interrupt 1 enable bit aier0 0 : disable 1 : enable rw b2 b1 b0 address match interrupt 0 enable bit ? (b7-b2) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. b7 b6 b5 b4 0 : disable 1 : enable rw b3 address match interrupt register i (i = 0 or 1) b0 symbol address after reset rma d0 0012h-0010h 000000h rma d1 0016h-0014h 000000h setting range rw ( b23) b7 ? ? (b7-b4) nothing is assigned. if necessary, set to 0. when read, the content is 0. address setting register for address match interrupt 00000h to fffffh function rw ( b19) b3 ( b15) b7 ( b8) b0 b7 ( b16) b0 free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 122 of 485 rej09b0244-0300 12.5 timer rd interrupt, clock synchr onous serial i/o with chip select interrupts, and i 2 c bus interface interrupt (interrupts with multiple interrupt request sources) the timer rd (channel 0) interrupt, timer rd (channel 1) interrupt, clock synchronous serial i/o with chip select interrupt, and i 2 c bus interface interrupt each ha ve multiple interrupt request sources. an interrupt request is generated by the logical or of several interrupt request fa ctors and is reflected in the ir bit in the corresponding interrupt control register. therefore, each of these periph eral functions has its own interrupt request source status register (status register) and interrupt request source enable register (enable register) to control the generation of interrupt requests (change the ir bit in the interrupt contro l register). table 12.8 lists the registers associated with timer rd interrupt, clock synchronous serial i/o with chip select interrupt, and i 2 c bus interface interrupt and figure 12.19 shows a block diagram of timer rd interrupt. figure 12.19 block diagram of timer rd interrupt table 12.8 registers associated with timer rd interrupt, clock synchronous serial i/o with chip select interrupt, and i 2 c bus interface interrupt status register of interrupt request source enable register of interrupt request source interrupt control register timer rd channel 0 trdsr0 trdier0 trd0ic channel 1 trdsr1 trdier1 trd1ic clock synchronous serial i/o with chip select sssr sser ssuic i 2 c bus interface icsr icier iicic timer rd (channel i) interrupt request (ir bit in trdiic register) imfa bit imiea bit imfb bit imieb bit imfc bit imiec bit imfd bit imied bit udf bit ovf bit ovie bit i = 0 or 1 imfa, imfb, imfc, imfd, ovf, udf: bits in trdsri register imiea, imieb, imiec, imied, ovie: bits in trdier register channel i free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 123 of 485 rej09b0244-0300 as with other maskable interrupts, the timer rd (cha nnel 0) interrupt, timer rd (channel 1) interrupt, clock synchronous serial i/o with chip select interrupt, and i 2 c bus interface interrupt are controlled by the combination of the i flag, ir bit, bits ilvl0 to ilvl2, and ipl. however, since each interrupt source is generated by a combination of multiple interrupt request sources, the fo llowing differences from other maskable interrupts apply: ? when bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable interrupt), the ir bit in the interrupt control register is set to 1 (interrupt requested). ? when either bits in the status register or bits in the enable register corresponding to bits in the status register, or both, are set to 0, the ir bit is set to 0 (interrupt not requested). basically, even though the interrupt is not acknowledged after the ir bit is set to 1, the interrupt requ est will not be maintained. also, the ir bit is not set to 0 even if 0 is written to the ir bit. ? individual bits in the status register are not automa tically set to 0 even if the interrupt is acknowledged. therefore, the ir bit is also not automatically set to 0 when the interrupt is acknowledged. set each bit in the status register to 0 in the interrupt routine. refer to the status register figure for how to set individual bits in the status register to 0. ? when multiple bits in the enable register are set to 1 and other request sources are generated after the ir bit is set to 1, the ir bit remains 1. ? when multiple bits in the enable register are set to 1, determine by the status register which request source causes an interrupt. refer to chapters of the individual peripheral functions ( 14.3 timer rd , 16.2 clock synchronous serial i/o with chip select (ssu) and 16.3 i 2 c bus interface ) for the status register and enable register. refer to 12.1.6 interrupt control for the interrupt control register. free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 124 of 485 rej09b0244-0300 12.6 notes on interrupts 12.6.1 reading address 00000h do not read address 00000h by a program. when a mask able interrupt request is acknowledged, the cpu reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. at this time, the acknowledged interrupt ir bit is set to 0. if address 00000h is read by a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. this may cause the interrupt to be cancel ed, or an unexpected interrupt to be generated. 12.6.2 sp setting set any value in the sp before an interrupt is acknowledged. the sp is set to 0000h afte r reset. therefore, if an interrupt is acknowledged before setting a value in the sp, the program may run out of control. 12.6.3 external interrupt and key input interrupt either ?l? level or an ?h? le vel of width shown in the el ectrical characteristics is ne cessary for the signal input to pins int0 to int3 and pins ki0 to ki3 , regardless of the cpu clock. for details, refer to table 20.21 (vcc = 5v), table 20.27 (vcc = 3v), table 20.33 (vcc = 2.2v) external interrupt inti (i = 0 to 3) input . free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 125 of 485 rej09b0244-0300 12.6.4 changing interrupt sources the ir bit in the interrupt control register may be se t to 1 (interrupt requested) when the interrupt source changes. when using an interrupt, set the ir bit to 0 (n o interrupt requested) after changing the interrupt source. in addition, changes of interrupt so urces include all factors that change the interr upt sources assigned to individual software interrupt numbers, polarities, and timing. therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and ti ming, set the ir bit to 0 (no interrupt requested) after the change. refer to the individual periph eral function for its related interrupts. figure 12.20 shows an example of pro cedure for changing interrupt sources. figure 12.20 example of procedure for changing interrupt sources notes: 1. execute the above settings individually. do not execute two or more settings at once (by one instruction). 2. to prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. in this case, use the i flag if all maskable interrupts can be disabled. if all maskable interrupts cannot be disabled, use bits ilvl0 to ilvl2 of the interrupt whose source is changed. 3. refer to 12.6.5 changing interrupt control register contents for the instructions to be used and usage notes. interrupt source change disable interrupts (2, 3) set the ir bit to 0 (interrupt not requested) using the mov instruction (3) change interrupt source (including mode of peripheral function) enable interrupts (2, 3) change completed ir bit: the interrupt control register bit of an interrupt whose source is changed. free datasheet http:///
r8c/24 group, r8c/25 group 12. interrupts rev.3.00 feb 29, 2008 page 126 of 485 rej09b0244-0300 12.6.5 changing interrupt c ontrol regist er contents (a) the contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. if in terrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) when changing the contents of an interrupt contro l register after disabling interrupts, be careful to choose appropriate instructions. changing any bit other than ir bit if an interrupt request corresponding to a register is generated while executing the instruction, the ir bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. if this causes a problem, use the following instructions to change the register : and, or, bclr, bset changing ir bit if the ir bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. therefore, use the mov instruct ion to set the ir bit to 0. (c) when disabling interrupts using the i flag, set the i flag as shown in the sample programs below. refer to (b) regarding changing the contents of interrupt control registers by the sample programs. sample programs 1 to 3 are for preventi ng the i flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. example 1: use nop instructions to prevent i flag from being set to 1 before interrupt control register is changed int_switch1: fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h nop ; nop fset i ; enable interrupts example 2: use dummy read to delay fset instruction int_switch2: fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h mov.w mem,r0 ; dummy read fset i ; enable interrupts example 3: use popc instruction to change i flag int_switch3: pushc flg fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h popc flg ; enable interrupts free datasheet http:///
r8c/24 group, r8c/25 group 13. watchdog timer rev.3.00 feb 29, 2008 page 127 of 485 rej09b0244-0300 13. watchdog timer the watchdog timer is a function that detects when a pr ogram is out of control. use of the watchdog timer is recommended to improve the reliability of the system. the watchdog timer contains a 15-bit counter and allows selection of count source protection mode enable or disable. table 13.1 lists information on the count source protection mode. refer to 5.6 watchdog timer reset for details on the watchdog timer. figure 13.1 shows the block diagram of watchdog timer . figure 13.2 shows the registers ofs and wdc, figure 13.3 shows registers wdtr, wdts, and cspr. figure 13.1 block diagram of watchdog timer table 13.1 count source protection mode item count source protection mode disabled count source protection mode enabled count source cpu clock low-speed on-chip oscillator clock count operation decrement count start condition either of the following can be selected ? after reset, count starts automatically ? count starts by writing to wdts register count stop condition stop mode, wait mode none reset condition of watchdog timer ? reset ? write 00h to the wdtr register before writing ffh ? underflow operation at the time of underflow watchdog timer interrupt or watchdog timer reset watchdog timer reset internal reset signal (?l? active) write to wdtr register set to 7fffh (1) pm12 = 1 watchdog timer reset pm12 = 0 watchdog timer interrupt request cspro: bit in cspr register wdc7: bit in wdc register pm12: bit in pm1 register cm07: bit in cm0 register note: 1. when the cspro bit is set to 1 (count source protection mode enabled), 0fffh is set. 1/128 1/2 cm07 = 1 prescaler cspro = 0 foco-s cspro = 1 1/16 cm07 = 0, wdc7 = 0 cm07 = 0, wdc7 = 1 cpu clock watchdog timer free datasheet http:///
r8c/24 group, r8c/25 group 13. watchdog timer rev.3.00 feb 29, 2008 page 128 of 485 rej09b0244-0300 figure 13.2 registers ofs and wdc option function select register (1) symbol address when shipping ofs 0ffffh ffh (3) bit symbol bit name function rw notes: 1. 2. 3. if the block including the ofs register is erased, ffh is set to the ofs register. ? (b6) reserved bit set to 1. rw csproini count source protect mode after reset select bit 0 : count source protect mode enabled after reset 1 : count source protect mode disabled after reset rw to use the pow er-on reset, set the lvd0on bit to 0 (voltage monitor 0 reset enabled after reset). romcp1 rom code protect bit 0 : rom code protect enabled 1 : rom code protect disabled rw romcr rom code protect disabled bit 0 : rom code protect disabled 1 : romcp1 enabled rw ? (b1) rw reserved bit set to 1. wdton rw watchdog timer start select bit 0 : starts w atchdog timer automatically after reset 1 : watchdog timer is inactive after reset 1 11 b7 b6 b5 b4 b3 b2 b1 b0 ? (b4) reserved bit set to 1. rw the ofs register is on the flash memory. write to the ofs register w ith a program. after w riting is completed, do not w rite additions to the ofs register. lvd0on voltage detection 0 circuit start bit (2) 0 : voltage monitor 0 reset enabled after hardw are reset 1 : voltage monitor 0 reset disabled after hardw are reset rw watchdog timer control register symbol address after reset wdc 000fh 00x11111b bit symbol bit name function rw reserved bit set to 0. when read, the content is undefined. ro wdc7 ? (b6) reserved bit set to 0. prescaler select bit 0 : divide-by-16 1 : divide-by-128 b7 b6 b5 b4 00 rw high-order bits of w atchdog timer ? (b4-b0) rw ? (b5) rw b3 b2 b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 13. watchdog timer rev.3.00 feb 29, 2008 page 129 of 485 rej09b0244-0300 figure 13.3 registers wdtr, wdts, and cspr watchdog timer reset register symbol address after reset wdtr 000dh undefined rw notes: 1. 2. when 00h is w ritten before w riting ffh, the w atchdog timer is reset. (1) the default value of the w atchdog timer is 7fffh w hen count source protection mode is disabled and 0fffh w hen count source protection mode is enabled. (2) function do not generate an interrupt betw een w hen 00h and ffh are w ritten. when the cspro bit in the cspr register is set to 1 (count source protection mode enabled), 0fffh is s et in the w atc hdog timer. wo b7 b0 watchdog timer start register symbol address after reset wdts 000eh undefined rw b0 b7 wo function the w atchdog timer starts counting after a w rite instruction to this register. count source protection mode register symbol address after reset (1) cspr 001ch 00h bit symbol bit name function rw notes: 1. 2. 000 b7 b6 b5 b4 b3 b2 b1 b0 write 0 before w riting 1 to set the cspro bit to 1. 0 cannot be set by a program. when 0 is w ritten to the csproini bit in the ofs register, the value after reset is 10000000b. 0 reserved bits set to 0. rw 0 cspro count source protection mode select bit (2) 0 : count source protection mode disabled 1 : count source protection mode enabled ? (b6-b0) rw 0 0 free datasheet http:///
r8c/24 group, r8c/25 group 13. watchdog timer rev.3.00 feb 29, 2008 page 130 of 485 rej09b0244-0300 13.1 count source protect ion mode disabled the count source of the watchdog timer is the cpu cl ock when count source protection mode is disabled. table 13.2 lists the watchdog timer specifications (with count source protection mode disabled). notes: 1. the watchdog timer is reset when 00h is written to the wdtr register before ffh. the prescaler is reset after the mcu is reset. some errors in the period of the watchdog timer may be caused by the prescaler. 2. the wdton bit cannot be changed by a program. to set the wdton bit, write 0 to bit 0 of address 0ffffh with a flash programmer. table 13.2 watchdog timer specifications (with count source protection mode disabled) item specification count source cpu clock count operation decrement period division ratio of prescaler (n) count value of watchdog timer (32768) (1) cpu clock n: 16 or 128 (selected by wdc7 bit in wdc register) example: when the cpu clock frequency is 16 mhz and prescaler divided by 16, the period is approximately 32.8 ms count start condition the wdton bit (2) in the ofs register (0ffffh) selects the operation of the watchdog timer after a reset ? when the wdton bit is set to 1 (watchdog timer is in stop state after reset) the watchdog timer and prescaler stop after a reset and the count starts when the wdts register is written to ? when the wdton bit is set to 0 (w atchdog timer starts automatically after exiting) the watchdog timer and prescaler start counting automatically after a reset reset condition of watchdog timer ? reset ? write 00h to the wdtr register before writing ffh ? underflow count stop condition stop and wait modes (inherit the count from the held value after exiting modes) operation at time of underflow ? when the pm12 bit in the pm1 register is set to 0 watchdog timer interrupt ? when the pm12 bit in the pm1 register is set to 1 watchdog timer reset (refer to 5.6 watchdog timer reset ) free datasheet http:///
r8c/24 group, r8c/25 group 13. watchdog timer rev.3.00 feb 29, 2008 page 131 of 485 rej09b0244-0300 13.2 count source protect ion mode enabled the count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. if the cpu clock stops when a program is out of control, the clock can still be supplied to the watchdog timer. table 13.3 lists the watchdog timer specifications (with count source protection mode enabled). notes: 1. the wdton bit cannot be changed by a program. to set the wdton bit, write 0 to bit 0 of address 0ffffh with a flash programmer. 2. even if 0 is written to the csproini bit in the ofs register, the cspro bit is set to 1. the csproini bit cannot be changed by a program. to set the csproini bit, write 0 to bit 7 of address 0ffffh with a flash programmer. table 13.3 watchdog timer specifications (with count source protection mode enabled) item specification count source low-speed on -chip oscillator clock count operation decrement period count value of watchdog timer (4096) low-speed on-chip oscillator clock example: period is approximately 32.8 ms when the low-speed on- chip oscillator clock frequency is 125 khz count start condition the wdton bit (1) in the ofs register (0ffffh) selects the operation of the watchdog timer after a reset. ? when the wdton bit is set to 1 (watchdog timer is in stop state after reset) the watchdog timer and prescaler stop after a reset and the count starts when the wdts register is written to ? when the wdton bit is set to 0 (watchdog timer starts automatically after reset) the watchdog timer and prescaler start counting automatically after a reset reset condition of watchdog timer ? reset ? write 00h to the wdtr register before writing ffh ? underflow count stop condition none (the count does not stop in wait mode after the count starts. the mcu does not enter stop mode.) operation at time of underflow watchdog timer reset (refer to 5.6 watchdog timer reset. ) registers, bits ? when setting the csppro bi t in the cspr register to 1 (count source protection mode is enabled) (2) , the following are set automatically - set 0fffh to the watchdog timer - set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator on) - set the pm12 bit in the pm1 register to 1 (the watchdog timer is reset when watchdog timer underflows) ? the following conditions apply in count source protection mode - writing to the cm10 bit in the cm1 register is disabled (it remains unchanged even if it is set to 1. the mcu does not enter stop mode.) - writing to the cm14 bit in the cm1 register is disabled (it remains unchanged even if it is set to 1. the low-speed on-chip oscillator does not stop.) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 132 of 485 rej09b0244-0300 14. timers the mcu has two 8-bit timers with 8-bit prescalers, two 16-b it timers, and a timer with a 4-bit counter and an 8-bit counter. the two 8-bit timers with 8-bit prescalers are timer ra and timer rb. thes e timers contain a reload register to store the default value of the counter. the 16-bit timer is timer rd, and has input capture and output compare functions. the 4 and 8-bit counters are timer re, and ha s an output compare function. all the timers operate independently. table 14.1 lists functional comparison of timers. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 133 of 485 rej09b0244-0300 note: 1. the underflow interrupt can be set to channel 1. table 14.1 functional comparison of timers item timer ra timer rb timer rd timer re configuration 8-bit timer with 8- bit prescaler (with reload register) 8-bit timer with 8- bit prescaler (with reload register) 16-bit free-run timer 2 (with input capture and output compare) 4-bit counter 8-bit counter count decrement decrement increment/decrement increment count sources ? f1 ?f2 ?f8 ?foco ?fc32 ?f1 ?f2 ?f8 ?timer ra underflow ?f1 ?f2 ?f4 ?f8 ?f32 ? foco40m ?trdioa0 ?f4 ?f8 ?f32 ?fc4 function timer mode provided provided provided (input capture function, output compare function) not provided pulse output mode provided not pr ovided not provided not provided event counter mode provided not provided not provided not provided pulse width measurement mode provided not provided not provided not provided pulse period measurement mode provided not provided not provided not provided programmable waveform generation mode not provided provided not provided not provided programmable one- shot generation mode not provided provided not provided not provided programmable wait one-shot generation mode not provided provided not provided not provided input capture mode not provided not provided provided not provided output compare mode not provided not provided provided provided pwm mode not provided not provided provided not provided reset synchronized pwm mode not provided not provided provided not provided complementary pwm mode not provided not provided provided not provided pwm3 mode not provided not provided provided not provided real-time clock mode not provided not provided not provided provided input pin traio int0 int0 , trdclk, trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 ? output pin trao traio trbo trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 treo related interrupt timer ra interrupt int1 interrupt timer rb interrupt int0 interrupt compare match/input capture a0 to d0 interrupt compare match/input capture a1 to d1 interrupt overflow interrupt underflow interrupt (1) int0 interrupt timer re interrupt timer stop provided provided provided provided free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 134 of 485 rej09b0244-0300 14.1 timer ra timer ra is an 8-bit timer with an 8-bit prescaler. the prescaler and timer each consist of a reload register and counter. the reload regist er and counter are allocated at the same address, and can be accessed when accessing registers trapre and tra (refer to tables 14.2 to 14.6 the specification s of each mode ). the count source for timer ra is the operating clock that regulates the timing of timer operations such as counting and reloading. figure 14.1 shows a block diagram of timer ra. figures 14.2 and 14.3 show the registers associated with timer ra. timer ra has the following five operating modes: ? timer mode: the timer counts the internal count source. ? pulse output mode: the timer counts the internal count source and outputs pulses of which polarity inverted by underflow of the timer. ? event counter mode: the timer counts external pulses. ? pulse width measurement mode: the timer meas ures the pulse width of an external pulse. ? pulse period measurement mode: the timer meas ures the pulse period of an external pulse. figure 14.1 block diagram of timer ra = 000b = 001b = 011b f2 f8 f1 = 010b foco tck2 to tck0 bit tmod2 to tmod0 = other than 010b counter reload register trapre register (prescaler) data bus timer ra interrupt write to tramr register write 1 to tstop bit tcstf, tstop: bits in tracr register tedgsel, topcr, toena, tiosel, tipf1, tipf0: bits in traioc register tmod2 to tmod0, tck2 to tck0, tckcut: bits in tramr register toggle flip-flop q q clr ck toena bit trao pin int1/traio (p1_5) pin tcstf bit tckcut bit tmod2 to tmod0 = 011b or 100b tmod2 to tmod0 = 010b polarity switching digital filter counter reload register tra register (timer) tipf1 to tipf0 bits = 01b = 10b f8 f1 = 11b f32 tiosel = 0 tiosel = 1 count control circle tmod2 to tmod0 = 001b topcr bit underflow signal measurement completion signal tipf1 to tipf0 bits = other than 000b = 00b int1/traio (p1_7) pin tedgsel = 1 tedgsel = 0 = 100b fc32 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 135 of 485 rej09b0244-0300 figure 14.2 registers tracr and traioc timer ra control register (4) symbol address after reset tra cr 0100h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. rw tcstf rw rw ro tsta rt 0 : count stops 1 : during count 0 : count stops 1 : count starts timer ra count status flag (1) tstop ? ? rw tedgf 0 : active edge not received 1 : active edge received (end of measurement period) active edge judgment flag (3, 5) timer ra underflow flag (3, 5) 0 : no underflow 1 : underflow nothing is assigned. if necessary, set to 0. when read, the content is 0. b3 b2 when this bit is set to 1, the count is forcibly stopped. when read, its content is 0. ? (b3) b1 b0 b7 b6 b5 b4 timer ra count start bit (1) timer ra count forcible stop bit (2) in pulse w idth measurement mode and pulse period measurement mode, use the mov instruction to set the tracr register. if it is necessary to avoid changing the values of bits tedgf and tundf, w rite 1 to them. set to 0 in timer mode, pulse output mode, and event counter mode. bits tedgf and tundf can be set to 0 by w riting 0 to these bits by a program. how ever, their value remains unchanged w hen 1 is w ritten. tundf when the tstop bit is set to 1, bits tstart and tcstf and registers tprapre and tra are set to the values after a reset. nothing is assigned. if necessary, set to 0. when read, the content is 0. ref er to 14.1.6 notes on tim er ra . ? (b7-b6) timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit rw tipf0 rw toena rw traio input filter select bits tipf1 function varies depending on operating mode. traio output control bit trao output enable bit ? tedgsel rw topcr rw traio polarity sw itch bit nothing is assigned. if necessary, set to 0. when read, the content is 0. ? (b7-b6) b7 b6 b5 b4 b3 b2 tiosel b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 136 of 485 rej09b0244-0300 figure 14.3 registers tramr, trapre, and tra timer ra mode register (1) symbol address after reset tra mr 0102h 00h bit symbol bit name function rw note: 1. tck0 b3 b2 ? (b3) b1 b0 nothing is assigned. if necessary, set to 0. when read, the content is 0. rw ? rw b7 b6 b5 b4 rw tmod1 rw tmod0 timer ra operating mode select bits b2 b1 b0 0 0 0 : timer mode 0 0 1 : pulse output mode 0 1 0 : event counter mode 0 1 1 : pulse w idth measurement mode 1 0 0 : pulse period measurement mode 1 0 1 : 1 1 0 : do not set. 1 1 1 : tmod2 rw when both the tstart and tcstf bits in the tracr register are set to 0 (count stops), rew rite this register. rw timer ra count source cutoff bit 0 : provides count source 1 : cuts off count source tck2 rw timer ra count source select bits b6 b5 b4 0 0 0 : f1 0 0 1 : f8 0 1 0 : foco 0 1 1 : f2 1 0 0 : fc32 1 0 1 : 1 1 0 : do not set. 1 1 1 : tckcut tck1 timer ra prescaler registe r symbol address after reset tra pre 0103h ffh (1) mode function setting range rw note: 1. rw pulse w idth measurement mode b0 timer mode rw b7 counts an internal count source 00h to ffh pulse output mode rw counts an internal count source 00h to ffh counts internal count source when the tstop bit in the tracr register is set to 1, the trapre register is set to ffh. event counter mode counts an external count source 00h to ffh rw 00h to ffh rw pulse period measurement mode 00h to ffh timer ra register symbol address after reset tra 0104h ffh (1) mode function setting range rw note: 1. 00h to ffh b7 when the tstop bit in the tracr register is set to 1, the tra register is set to ffh. b0 all modes counts on underflow of timer ra prescaler register rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 137 of 485 rej09b0244-0300 14.1.1 timer mode in this mode, the timer counts an internally generated count source (refer to table 14.2 timer mode specifications ). figure 14.4 shows the traioc register in timer mode. figure 14.4 traioc register in timer mode table 14.2 timer m ode specifications item specification count sources f1, f2, f8, foco, fc32 count operations ? decrement ? when the timer underflows, the contents of the reload register are reloaded and the count is continued. divide ratio 1/(n+1)(m+1) n: value set in trapre register, m: value set in tra register count start condition 1 (count starts) is writte n to the tstart bit in the tracr register. count stop conditions ? 0 (count stops) is wri tten to the tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing when timer ra underflows [timer ra interrupt]. int1 /traio pin function programmable i/o port, or int1 interrupt input trao pin function programmable i/o port read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tra are written while the count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). timer ra i/o control register symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit traio input filter select bits set to 0 in timer mode. rw traio polarity sw itch bit 0 set to 0 in timer mode. traio output control bit ? (b7-b6) ? topcr rw toena rw rw tipf0 rw tipf1 00 b7 b6 b5 b4 b3 b2 tiosel b1 b0 0 0 tedgsel free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 138 of 485 rej09b0244-0300 14.1.1.1 timer write control during count operation timer ra has a prescaler and a time r (which counts the prescaler unde rflows). the prescaler and timer each consist of a reload register and a coun ter. when writing to the pr escaler or timer, values are written to both the reload register and counter. however, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. in addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. therefore, if the prescaler or timer is written to when count operation is in progress, the counter value is not updated immediately after the write instruction is executed. figure 14.5 shows an operating example of timer ra when counter value is rewritten during count operation. figure 14.5 operating example of timer ra when counter value is rewritten during count operation count source reloads register of timer ra prescaler ir bit in traic register 0 counter of timer ra prescaler reloads register of timer ra counter of timer ra set 01h to the trapre register and 25h to the tra register by a program. after writing, the reload register is written to at the first count source. reload at second count source reload at underflow after writing, the reload register is written to at the first underflow. reload at the second underflow the ir bit remains unchanged until underflow is generated by a new value. 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h 06h new value (01h) previous value new value (25h) previous value 03h 24h 02h 25h the above applies under the following conditions. both bits tstart and tcstf in the tra cr register are set to 1 (during count). free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 139 of 485 rej09b0244-0300 14.1.2 pulse output mode in pulse output mode, the internally generated count sour ce is counted, and a pulse with inverted polarity is output from the traio pin each time the timer underflows (refer to table 14.3 pulse output mode specifications ). figure 14.6 shows the traioc register in pulse output mode. note: 1. the level of the output pulse becomes the level when the pulse output starts when the tramr register is written to. table 14.3 pulse output mode specifications item specification count sources f1, f2, f8, foco, fc32 count operations ? decrement ? when the timer underflows, the contents in the reload register is reloaded and the count is continued. divide ratio 1/(n+1)(m+1) n: value set in trapre register , m: value set in tra register count start condition 1 (count starts) is writte n to the tstart bit in the tracr register. count stop conditions ? 0 (count stops) is writ ten to the tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing when timer ra underflows [timer ra interrupt]. int1 /traio pin function pulse output, programmable output port, or int1 interrupt (1) trao pin function programmable i/o port or inverted output of traio (1) read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tra are written while the count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). select functions ? traio output polarity switch function the tedgsel bit in the traioc register selects the level at the start of pulse output. (1) ? trao output function pulses inverted from the traio output polarity can be output from the trao pin (selectable by the toena bit in the traioc register). ? pulse output stop function output from the traio pin is stopped by the topcr bit in the traioc register. ?int1 /traio pin select function p1_7 or p1_5 is selected by the tiosel bit in the traioc register. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 140 of 485 rej09b0244-0300 figure 14.6 traioc register in pulse output mode timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) b3 b2 0 : po r t p3 _ 0 1 : trao output (inverted traio output from p3_0) tiosel b1 b0 0 : traio output starts at ?h? 1 : traio output starts at ?l? b7 b6 b5 b4 00 tipf1 ? (b7-b6) ? topcr rw toena rw rw tipf0 traio output control bit tedgsel rw traio polarity sw itch bit rw rw 0 : traio output 1 : port p1_7 or p1_5 nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit traio input filter select bits set to 0 in pulse output mode. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 141 of 485 rej09b0244-0300 14.1.3 event counter mode in event counter mode, external signal inputs to the int1 /traio pin are counted (refer to table 14.4 event counter mode specifications ). figure 14.7 shows the traioc register in event counter mode. note: 1. the level of the output pulse becomes the level when the pulse output starts when the tramr register is written to. table 14.4 event counter mode specifications item specification count source external signal which is input to traio pin (active edge selectable by a program) count operations ? decrement ? when the timer underflows, the contents of the reload register are reloaded and the count is continued. divide ratio 1/(n+1)(m+1) n: setting value of trapre register , m: setting value of tra register count start condition 1 (count starts) is written to the tstart bit in the tracr register. count stop conditions ? 0 (count stops) is writ ten to the tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing ? when timer ra underflows [timer ra interrupt]. int1 /traio pin function count source input (int1 interrupt input) trao pin function programmable i/o port or pulse output (1) read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tra ar e written while the count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). select functions ?nt1 input polarity switch function the tedgsel bit in the traioc register selects the active edge of the count source. ? count source input pin select function p1_7 or p1_5 is selected by the tiosel bit in the traioc register. ? pulse output function pulses of inverted polarity can be output from the trao pin each time the timer underflows (selectable by the toena bit in the traioc register). (1) ? digital filter function bits tipf0 and tipf1 in the traioc regist er enable or disable the digital filter and select the sampling frequency. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 142 of 485 rej09b0244-0300 figure 14.7 traioc register in event counter mode timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) note: 1. ? when the same value from the traio pin is sampled three times continuously, the input is determined. traio output control bit set to 0 in event counter mode. nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit traio input filter select bits (1) b5 b4 0 0 : no filter 0 1 : filter w ith f1 sampling 1 0 : filter w ith f8 sampling 1 1 : filter w ith f32 sampling tipf1 ? (b7-b6) rw tedgsel rw traio polarity sw itch bit rw tipf0 rw topcr rw b3 b2 b7 b6 b5 b4 0 : po r t p3 _ 0 1 : trao output tiosel b1 b0 0 : starts counting at rising edge of the traio input or traio starts output at ?l? 1 : starts counting at fa lling edge of the traio input or traio starts output at ?h? 0 toena free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 143 of 485 rej09b0244-0300 14.1.4 pulse width measurement mode in pulse width measurement mode, the pulse width of an external signal input to the int1 /traio pin is measured (refer to table 14.5 pulse width meas urement mode specifications ). figure 14.8 shows the traioc register in pulse width measurement mode and figure 14.9 shows an operating example of puls e width measurement mode. table 14.5 pulse width measurement mode specifications item specification count sources f1, f2, f8, foco, fc32 count operations ? decrement ? continuously counts the selected signal only when measurement pulse is ?h? level, or conversely only ?l? level. ? when the timer underflows, the contents of the reload register are reloaded and the count is continued. count start condition 1 (count starts) is written to the tstart bit in the tracr register. count stop conditions ? 0 (count stops) is writ ten to the tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing ? when timer ra underflows [timer ra interrupt]. ? rising or falling of the traio input (end of measurement period) [timer ra interrupt] int1 /traio pin function measured pulse input (int1 interrupt input) trao pin function programmable i/o port read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tr a are written while th e count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). select functions ? measurement level select the tedgsel bit in the traioc register selects the ?h? or ?l? level period. ? measured pulse input pin select function p1_7 or p1_5 is selected by the tiosel bit in the traioc register. ? digital filter function bits tipf0 and tipf1 in the traioc re gister enable or disable the digital filter and select the sampling frequency. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 144 of 485 rej09b0244-0300 figure 14.8 traioc register in pulse width measurement mode timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) note: 1. when the same value from the traio pin is sampled three times continuously, the input is determined. b3 b2 tiosel b1 b0 0 : traio input starts at ?l? 1 : traio input starts at ?h? 0 0 b7 b6 b5 b4 ? topcr rw toena rw rw tipf0 rw traio output control bit tipf1 tedgsel rw traio polarity sw itch bit ? (b7-b6) nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit traio input filter select bits (1) b5 b4 0 0 : no filter 0 1 : filter w ith f1 sampling 1 0 : filter w ith f8 sampling 1 1 : filter w ith f32 sampling set to 0 in pulse w idth measurement mode. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 145 of 485 rej09b0244-0300 figure 14.9 operating example of pulse width measurement mode ffffh n 0000h content of counter (hex) n = high level: the contents of tra register, low level: the contents of trapre register count start count stop underflow period tstart bit in tracr register 1 0 measured pulse (traio pin input) 1 0 tedgf bit in tracr register 1 0 tundf bit in tracr register 1 0 ? ?h? level width of measured pulse is measured. (tedgsel = 1) ? trapre = ffh set to 1 by program ir bit in traic register 1 0 set to 0 by program count stop count start set to 0 when interrupt request is acknowledged, or set by program count start set to 0 by program the above applies under the following conditions. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 146 of 485 rej09b0244-0300 14.1.5 pulse period measurement mode in pulse period measurement mode, the pulse period of an external signal input to the int1 /traio pin is measured (refer to table 14.6 pulse period measu rement mode specifications ). figure 14.10 shows the traioc register in pulse period measurement mode and figure 14.11 shows an operating example of puls e period measurement mode. note: 1. input a pulse with a period longer than twice th e timer ra prescaler period. input a pulse with a longer ?h? and ?l? width than the timer ra prescaler period. if a pulse with a shorter period is input to the traio pin, the input may be ignored. table 14.6 pulse period measurement mode specifications item specification count sources f1, f2, f8, foco, fc32 count operations ? decrement ? after the active edge of the measured pulse is input, the contents of the read- out buffer are retained at the first underflow of timer ra prescaler. then timer ra reloads the contents in the reload register at the second underflow of timer ra prescaler and continues counting. count start condition 1 (count starts) is writte n to the tstart bit in the tracr register. count stop conditions ? 0 (count stops) is wri tten to tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing ? when timer ra underflows or reloads [timer ra interrupt]. ? rising or falling of the traio input (end of meas urement period) [timer ra interrupt] int1 /traio pin function measured pulse input (1) (int1 interrupt input) trao pin function programmable i/o port read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tr a are written while th e count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). select functions ? measurement period select the tedgsel bit in the traioc regist er selects the measurement period of the input pulse. ? measured pulse input pin select function p1_7 or p1_5 is selected by the ti osel bit in the traioc register. ? digital filter function bits tipf0 and tipf1 in the traioc r egister enable or disable the digital filter and select the sampling frequency. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 147 of 485 rej09b0244-0300 figure 14.10 traioc register in pulse period measurement mode timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) note: 1. when the same value from the traio pin is sampled three times continuously, the input is determined. b3 b2 tiosel b1 b0 0 : measures measurement pulse from one rising edge to next rising edge 1 : measures measurement pulse from one f alling edge to next f alling edge 0 0 b7 b6 b5 b4 ? topcr rw toena rw rw tipf0 rw traio output control bit tipf1 tedgsel rw tra io polarity sw itch bit ? (b7-b6) nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit traio input filter select bits (1) b5 b4 0 0 : no filter 0 1 : filter w ith f 1 sampling 1 0 : filter w ith f 8 sampling 1 1 : filter w ith f32 sampling set to 0 in pulse period measurement mode. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 148 of 485 rej09b0244-0300 figure 14.11 operating example of pulse period measurement mode underflow signal of timer ra prescaler notes: 1. the contents of the read-out buffer can be read by r eading the tra register in pulse period measurement mode. 2. after an active edge of the measured pulse is input, the tedgf bit in the tracr register is set to 1 (active edge found) whe n the timer ra prescaler underflows for the second time. 3. the tra register should be read before the next active edge is input after the tedgf bit is set to 1 (active edge found). the contents in the read-out buffer are retained until the tra register is read. if the tra register is not read before the nex t active edge is input, the measured result of the previous period is retained. 4. to set to 0 by a program, use a mov instruction to write 0 to the tedgf bit in the tracr register. at the same time, write 1 to the tundf bit in the tracr register. 5. to set to 0 by a program, use a mov instruction to write 0 to the tundf bit. at the same time, write 1 to the tedgf bit. 6. bits tundf and tedgf are both set to 1 if timer ra underflows and reloads on an active edge simultaneously. 0eh 0dh 0fh 0eh 0dh 0ch 0bh 0ah 09h 0fh 0eh 0dh 01h 00h 0fh 0eh 0fh 0dh 0fh 0bh 0ah 0dh 01h 00h 0fh 0eh 09h tstart bit in tracr register 1 0 1 0 1 0 tedgf bit in tracr register 1 0 measurement pulse (traio pin input) contents of tra 1 0 contents of read-out buffer (1) ir bit in traic register tundf bit in tracr register set to 1 by program starts counting tra reloads tra read (3) retained (note 2) set to 0 by program conditions: the period from one rising edge to the next rising edge of the measured pulse is measured (tedgsel = 0) with the default value of the tra register as 0fh. 0eh tra reloads retained set to 0 when interrupt request is acknowledged, or set by program set to 0 by program underflow (note 2) (note 4) (note 6) (note 5) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 149 of 485 rej09b0244-0300 14.1.6 notes on timer ra ? timer ra stops counting after a rese t. set the values in the timer ra and timer ra prescalers before the count starts. ? even if the prescaler and timer ra are read out in 16- bit units, these registers are read 1 byte at a time by the mcu. consequently, the timer va lue may be updated during the period when these two registers are being read. ? in pulse period measurement mode, bits tedgf and tundf in the tracr register can be set to 0 by writing 0 to these bits by a program. however, these b its remain unchanged if 1 is written. when using the read-modify-write instruction for the tracr regi ster, the tedgf or tundf bit may be set to 0 although these bits are set to 1 while the instruction is being executed. in this case, write 1 to the tedgf or tundf bit which is not supposed to be set to 0 with the mov instruction. ? when changing to pulse period m easurement mode from another mode, the contents of bits tedgf and tundf are undefined. write 0 to bits tedgf and tundf before the count starts. ? the tedgf bit may be set to 1 by the first timer ra prescaler underflow generate d after the count starts. ? when using the pulse period measur ement mode, leave two or more periods of the timer ra prescaler immediately after the count starts, then set the tedgf bit to 0. ? the tcstf bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the tstart bit to 1 (count starts) while the count is stopped. during this time, do not access registers associated with timer ra (1) other than the tcstf bit. timer ra starts counting at the first valid edge of the count source after the tcstf bit is set to 1 (during count). the tcstf bit remains 1 for 0 to 1 cycle of the count source after setting the tstart bit to 0 (count stops) while the count is in progress. timer ra c ounting is stopped when the tcstf bit is set to 0. during this time, do not access re gisters associated with timer ra (1) other than the tcstf bit. note: 1. registers associated with timer ra: tracr, traioc, tramr, trapre, and tra. ? when the trapre register is continuously written during count operation (tcstf bit is set to 1), allow three or more cycles of the count source clock for each write interval. ? when the tra register is continuously written during count operation (tcstf bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 150 of 485 rej09b0244-0300 14.2 timer rb timer rb is an 8-bit timer with an 8-bit prescaler. the prescaler and timer each consist of a reload regist er and counter (refer to tables 14.7 to 14.10 the specifications of each mode ). timer rb has timer rb primary and time r rb secondary as reload registers. the count source for timer rb is the opera ting clock that regulates the timing of timer operations such as counting and reloading. figure 14.12 shows a block diagram of timer rb. figures 14.13 to 14.15 show the registers associated with timer rb. timer rb has four operation modes listed as follows: ? timer mode: the timer counts an internal count source (peripheral function clock or timer ra underflows). ? programmable waveform generation mode: the timer outputs pulses of a given width successively. ? programmable one-shot generation mode: the timer outputs a one-shot pulse. ? programmable wait one-shot generation mode: the timer outputs a delayed one-shot pulse. figure 14.12 block diagram of timer rb int0pl bit = 00b = 01b = 11b f8 f1 = 10b timer ra underflow tck1 to tck0 bits tstart bit trbpre register (prescaler) timer rb interrupt int0 interrupt tcstf bit toggle flip-flop q q clr ck topl = 1 topl = 0 trbo pin tocnt = 0 tocnt = 1 p3_1 bit in p3 register f2 tmod1 to tmod0 bits = 10b or 11b tosstf bit polarity select inoseg bit input polarity selected to be one edge or both edges digital filter int0 pin int0en bit tmod1 to tmod0 bits = 01b , 10b, 11b tmod1 to tmod0 bits = 01b , 10b, 11b counter reload register counter (timer rb) reload register trbpr register data bus trbsc register reload register tckcut bit inostg bit tstart, tcstf: bit in trbcr register tosstf: bit in trbocr register topl, tocnt, inostg, inoseg: bits in trbioc register tmod1 to tmod0, tck1 to tck0, tckcut: bits in trbmr register (timer) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 151 of 485 rej09b0244-0300 figure 14.13 registers trbcr and trbocr timer rb control registe r symbol address after reset trbcr 0108h 00h bit symbol bit name function rw notes: 1. 2. 3. indicates that count operation is in progress in timer mode or programmable w aveform mode. in programmable one- shot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has been acknow ledged. timer rb count start bit (1) timer rb count forcible stop bit (1, 2) ref er to 14.2.5 notes on tim er rb . tsta rt rw b7 b6 b5 b4 b3 b2 when this bit is set to 1, the count is forcibly stopped. when read, its content is 0. b1 b0 0 : count stops 1 : count starts when the tstop bit is set to 1, registers trbpre, trbsc, trbpr, and bits tstart and tcstf, and the tosstf bit in the trbocr register are set to values after a reset. 0 : count stops 1 : during count (3) nothing is assigned. if necessary, set to 0. when read, the content is 0. ro ? (b7-b3) ? tcstf timer rb count status flag (1) tstop rw timer rb one-shot control register (2) symbol address after reset trbocr 0109h 00h bit symbol bit name function rw notes: 1. 2. nothing is assigned. if necessary, set to 0. when read, the content is 0. timer rb one-shot status flag (1) when 1 is set to the tstop bit in the trbcr register, the tosstf bit is set to 0. this register is enabled w hen bits tmod1 to tmod0 in the trbmr register is set to 10b (programmable one-shot generation mode) or 11b (programmable w ait one-shot generation mode). ro ? (b7-b3) ? rw rw timer rb one-shot start bit when this bit is set to 1, one-shot trigger generated. when read, its content is 0. timer rb one-shot stop bit when this bit is set to 1, counting of one-shot pulses (including programmable w ait one-shot pulses) stops. when read, its content is 0. b7 b6 b5 b4 b3 b2 0 : one-shot stopped 1 : one-shot operating (including w ait period) b1 b0 tossp tosstf tosst free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 152 of 485 rej09b0244-0300 figure 14.14 registers trbioc and trbmr timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw nothing is assigned. if necessary, set to 0. when read, the content is 0. one-shot trigger polarity select bit ? (b7-b4) ? function varies depending on operating mode. rw rw rw rw one-shot trigger control bit b3 b2 inoseg b1 b0 inostg tocnt b7 b6 b5 b4 topl timer rb output level select bit timer rb output sw itch bit timer rb mode registe r symbol address after reset trbmr 010bh 00h bit symbol bit name function rw notes: 1. 2. ? timer rb count source select bits (1) b5 b4 0 0 : f1 0 1 : f8 1 0 : timer ra underflow 1 1 : f2 tck1 nothing is assigned. if necessary, set to 0. when read, the content is 0. the twrc bit can be set to either 0 or 1 in timer mode. in programmable w aveform generation mode, programmable one-shot generation mode, or programmable w ait one-shot generation mode, the twrc bit must be set to 1 (w rite to reload register only). tck0 rw change bits tmod1 and tmod0; tck1 and tck0; and tckcut w hen both the tstart and tcstf bits in the trbcr register set to 0 (count stops). rw timer rb count source cutoff bit (1) 0 : provides count source 1 : cuts off count source rw tckcut ? (b6) rw nothing is assigned. if necessary, set to 0. when read, the content is 0. timer rb w rite control bit (2) 0 : write to reload register and counter 1 : write to reload register only ? b7 b6 b5 b4 rw tmod1 rw timer rb operating mode select bits (1) b1 b0 0 0 : timer mode 0 1 : programmable w aveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable w ait one-shot generation mode b3 b2 twrc b1 b0 ? (b2) tmod0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 153 of 485 rej09b0244-0300 figure 14.15 registers t rbpre, trbsc, and trbpr timer rb secondary register (3, 4) symbol address after reset trbsc 010dh ffh mode function setting range rw notes: 1. 2. 3. 4. to w rite to the trbsc register, perform the follow ing steps. (1) write the value to the trbsc register. (2) write the value to the trbpr register. (if the value does not change, w rite the same value second time.) the count value can be read out by reading the trbpr register even w hen the secondary period is being counted. programmable w ait one-shot generation mode counts timer rb prescaler underflow s (one-shot w idth is counted) 00h to ffh wo (2) the values of registers trbpr and trbsc are reloaded to the counter alternately and counted. when the tstop bit in the trbcr register is set to 1, the trbsc register is set to ffh. wo (2) counts timer rb prescaler underflow s (1) 00h to ffh programmable one-shot generation mode disabled 00h to ffh ? programmable w aveform generation mode b7 b0 timer mode ? disabled 00h to ffh timer rb prescaler register (1) symbol address after reset trbpre 010ch ffh mode function setting range rw note: 1. when the tstop bit in the trbcr register is set to 1, the trbpre register is set to ffh. programmable w aveform generation mode rw counts an internal count source or timer ra underflow s 00h to ffh programmable one-shot generation mode counts an internal count source or timer ra underflow s 00h to ffh rw programmable w ait one-shot generation mode rw counts an internal count source or timer ra underflow s 00h to ffh b7 counts an internal count source or timer ra underflow s 00h to ffh rw b0 timer mode timer rb primary register (2) symbol address after reset trbpr 010eh ffh mode function setting range rw notes: 1. 2. when the tstop bit in the trbcr register is set to 1, the trbpr register is set to ffh. programmable w aveform generation mode rw counts timer rb prescaler underflow s (1) 00h to ffh programmable one-shot generation mode counts timer rb prescaler underflow s (one-shot w idth is counted) 00h to ffh rw the values of registers trbpr and trbsc are reloaded to the counter alternately and counted. timer mode rw counts timer rb prescaler underflow s 00h to ffh b7 b0 programmable w ait one-shot generation mode counts timer rb prescaler underflow s (w ait period w idth is counted) 00h to ffh rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 154 of 485 rej09b0244-0300 14.2.1 timer mode in timer mode, a count source which is internally gene rated or timer ra underflo ws are counted (refer to table 14.7 timer mode specifications ). registers trbocr and trbsc are not used in timer mode. figure 14.16 shows the trbioc register in timer mode. figure 14.16 trbioc register in timer mode table 14.7 timer m ode specifications item specification count sources f1, f2, f8, timer ra underflow count operations ? decrement ? when the timer underflows, it reloads th e reload register contents before the count continues (when timer rb underflows, the contents of timer rb primary reload register is reloaded). divide ratio 1/(n+1)(m+1) n: setting value in trbpre register, m: setting value in trbpr register count start condition 1 (count starts) is writte n to the tstart bit in the trbcr register. count stop conditions ? 0 (count stops) is writt en to the tstart bit in the trbcr register. ? 1 (count forcibly stops) is written to the tstop bit in the trbcr register. interrupt request generation timing when timer rb underflows [timer rb interrupt]. trbo pin function programmable i/o port int0 pin function programmable i/o port or int0 interrupt input read from timer the count value can be read out by reading registers trbpr and trbpre. write to timer ? when registers trbpre and trbp r are written while th e count is stopped, values are written to both the reload register and counter. ? when registers trbpre and trbpr are writ ten to while count operation is in progress: if the twrc bit in the trbmr register is se t to 0, the value is written to both the reload register and the counter. if the twrc bit is set to 1, the value is written to the reload register only. (refer to 14.2.1.1 timer write control during count operation .) timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw rw rw one-shot trigger control bit set to 0 in timer mode. rw rw 00 topl timer rb output level select bit timer rb output sw itch bit b7 b6 b5 b4 b3 b2 inoseg b1 b0 00 inostg tocnt nothing is assigned. if necessary, set to 0. when read, the content is 0. one-shot trigger polarity select bit ? (b7-b4) ? free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 155 of 485 rej09b0244-0300 14.2.1.1 timer write control during count operation timer rb has a prescaler and a timer (which counts the prescaler underflows). the prescaler and timer each consist of a reload register and a co unter. in timer mode, the twrc bit in the trbmr register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register. however, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. in addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflow s. therefore, even if the twrc bit is set for writing to both the reload register and counter, the counter va lue is not updated immediately after the write instruction is executed. in addition, if the twrc bit is set for writing to the reload register only, the synchronization of the writing will be shifted if the prescaler value changes. figure 14.17 shows an operating example of timer rb when counter value is rewritten during count operation. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 156 of 485 rej09b0244-0300 figure 14.17 operating example of timer rb when counter value is rewritten during count operation count source reloads register of timer rb prescaler ir bit in trbic register 0 counter of timer rb prescaler reloads register of timer rb counter of timer rb set 01h to the trbpre register and 25h to the trbpr register by a program. after writing, the reload register is written with the first count source. reload with the second count source reload on underflow after writing, the reload register is written on the first underflow. reload on the second underflow the ir bit remains unchanged until underflow is generated by a new value. when the twrc bit is set to 0 (write to reload register and counter) count source reloads register of timer rb prescaler ir bit in trbic register counter of timer rb prescaler reloads register of timer rb counter of timer rb set 01h to the trbpre register and 25h to the trbpr register by a program. after writing, the reload register is written with the first count source. reload on underflow after writing, the reload register is written on the first underflow. reload on underflow only the prescaler values are updated, extending the duration until timer rb underflow. when the twrc bit is set to 1 (write to reload register only) 05h 04h 03h 02h 01h 00h 01h 00h 01h 00h 06h 01h 00h 01h 03h 00h 02h 01h 25h new value (25h) previous value new value (01h) previous value new value (01h) previous value 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h 06h new value (25h) previous value 03h 24h 02h 25h the above applies under the following conditions. both bits tstart and tcstf in the trb cr register are set to 1 (during count). 0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 157 of 485 rej09b0244-0300 14.2.2 programmable waveform generation mode in programmable waveform generation mode, the signal output from the trbo pin is inverted each time the counter underflows, while the valu es in registers trbpr and trbsc are counted alternately (refer to table 14.8 programmable waveform generation mode specifications ). counting starts by counting the setting value in the trbpr register. the trbocr register is unused in this mode. figure 14.18 shows the trbioc register in programma ble waveform generation mode. figure 14.19 shows an operating example of timer rb in programmable waveform generation mode. notes: 1. even when counting the secondary period, the trbpr register may be read. 2. the set values are reflected in the waveform output beginning with the following primary period after writing to the trbpr register. 3. the value written to the tocnt bit is enabled by the following. ? when count starts. ? when a timer rb interrup t request is generated. the contents after the tocnt bit is changed are reflected from the output of the following primary period. table 14.8 programmable waveform generation mode specifications item specification count sources f1, f2, f8, timer ra underflow count operations ? decrement ? when the timer underflows, it reloads the contents of the primary reload and secondary reload registers alternately before the count continues. width and period of output waveform primary period: (n+1)(m+1)/fi secondary period: (n+1)(p+1)/fi period: (n+1){(m+1)+(p+1)}/fi fi: count source frequency n: value set in trbpre register m: value set in trbpr register p: value set in trbsc register count start condition 1 (count starts) is writte n to the tstart bit in the trbcr register. count stop conditions ? 0 (count stops) is writt en to the tstart bit in the trbcr register. ? 1 (count forcibly stops) is written to the tstop bit in the trbcr register. interrupt request generation timing in half a cycle of the count source, after timer rb underflows during the secondary period (at the same time as the trbo output change) [timer rb interrupt] trbo pin function programmable output port or pulse output int0 pin function programmable i/o port or int0 interrupt input read from timer the count value can be read out by reading registers trbpr and trbpre (1) . write to timer ? when registers trbpre, trbsc, and trbpr are written while the count is stopped, values are written to both the reload register and counter. ? when registers trbpre, trbsc, and trbpr are written to during count operation, values are written to the reload registers only. (2) select functions ? output level select function the topl bit in the trbioc register selects the output level during primary and secondary periods. ? trbo pin output switch function timer rb pulse output or p3_1 latch output is selected by the tocnt bit in the trbioc register. (3) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 158 of 485 rej09b0244-0300 figure 14.18 trbioc register in programmable waveform generation mode figure 14.19 operating example of timer rb in programmable waveform generation mode timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw ? (b7-b4) ? rw rw one-shot trigger control bit nothing is assigned. if necessary, set to 0. when read, the content is 0. one-shot trigger polarity select bit set to 0 in programmable w aveform generation mode. rw tocnt rw 00 topl timer rb output level select bit 0 : outputs ?h? for primary period outputs ?l? for secondary period outputs ?l? w hen the timer is stopped 1 : outputs ?l? for primary period outputs ?h? for secondary period outputs ?h? w hen the timer is stopped timer rb output sw itch bit 0 : outputs timer rb w aveform 1 : outputs value in p3_1 port latch b7 b6 b5 b4 b3 b2 inoseg b1 b0 inostg 1 0 1 0 ir bit in trbic register 1 0 count source timer rb prescaler underflow signal counter of timer rb trbo pin output topl bit in trbio register set to 1 by program set to 0 when interrupt request is acknowledged, or set by program. the above applies under the following conditions. tstart bit in trbcr register 1 0 01h 00h 02h timer rb secondary reloads timer rb primary reloads set to 0 by program trbpre = 01h, trbpr = 01h, trbsc = 02h trbioc register tocnt = 0 (timer rb waveform is output from the trbo pin) 02h 01h 00h 01h 00h primary period primary period secondary period waveform output starts waveform output inverted waveform output starts initial output is the same level as during secondary period. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 159 of 485 rej09b0244-0300 14.2.3 programmable one-shot generation mode in programmable one-shot generation mode, a one-shot pulse is output from the trbo pin by a program or an external trigger input (input to the int0 pin) (refer to table 14.9 programmable on e-shot generation mode specifications ). when a trigger is generated, the timer starts operating from the point only once for a given period equal to the set value in the trbpr register . the trbsc register is not used in this mode. figure 14.20 shows the trbioc register in program mable one-shot generation mode. figure 14.21 shows an operating example of program mable one-shot generation mode. notes: 1. the set value is reflected at the following one- shot pulse after writing to the trbpr register. 2. do not set both the trbpre and trbpr registers to 00h. table 14.9 programmable one-shot generation mode specifications item specification count sources f1, f2, f8, timer ra underflow count operations ? decrement the setting value in the trbpr register ? when the timer underflows, it reloads the contents of the reload register before the count completes and the tosstf bit is set to 0 (one-shot stops). ? when the count stops, the timer reloads the contents of the reload register before it stops. one-shot pulse output time (n+1)(m+1)/fi fi: count source frequency, n: setting value in trbpre register , m: setting value in trbpr register (2) count start conditions ? the tstart bit in the trbcr re gister is set to 1 (count starts) and the next trigger is generated. ? set the tosst bit in the trbocr register to 1 (one-shot starts) ? input trigger to the int0 pin count stop conditions ? when reloading completes af ter timer rb underflows during primary period. ? when the tossp bit in the trbocr regi ster is set to 1 (one-shot stops). ? when the tstart bit in the trbcr re gister is set to 0 (count stops). ? when the tstop bit in the trbcr register is set to 1 (count forcibly stops). interrupt request generation timing in half a cycle of the count source, after the timer underflows (at the same time as the trbo output ends) [timer rb interrupt] trbo pin function pulse output int0 pin functions ? when the inostg bit in the trbioc register is set to 0 (int0 one-shot trigger disabled): programmable i/o port or int0 interrupt input ? when the inostg bit in the trbioc register is set to 1 (int0 one-shot trigger enabled): external trigger (int0 interrupt input) read from timer the count value can be re ad out by reading registers trbpr and trbpre. write to timer ? when registers trbpre and tr bpr are written while the count is stopped, values are written to both the reload register and counter. ? when registers trbpre and trbpr are written during the count, values are written to the reload register only (the da ta is transferred to the counter at the following reload). (1) select functions ? output level select function the topl bit in the trbioc register se lects the output level of the one-shot pulse waveform. ? one-shot trigger select function refer to 14.2.3.1 one-shot trigger selection . free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 160 of 485 rej09b0244-0300 figure 14.20 trbioc register in programmable one-shot generation mode timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw 0 : int0 _ ____ pin one-shot trigger disabled 1 : int0 _ ____ pin one-shot trigger enabled note: 1. rw rw one-shot trigger control bit (1) 0 : falling edge trigger 1 : rising edge trigger rw tocnt rw topl timer rb output level select bit 0 : outputs one-shot pulse ?h? outputs ?l? w hen the timer is stopped 1 : outputs one-shot pulse ?l? outputs ?h? w hen the timer is stopped timer rb output sw itch bit set to 0 in programmable one-shot generation mode. b7 b6 b5 b4 b3 b2 inoseg b1 b0 0 inostg ref er to 14.2.3.1 one-shot trigger selection . nothing is assigned. if necessary, set to 0. when read, its content is 0. one-shot trigger polarity select bit (1) ? (b7-b4) ? free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 161 of 485 rej09b0244-0300 figure 14.21 operating example of programmable one-shot generation mode tosstf bit in trbocr register int0 pin input 1 0 1 0 ir bit in trbic register 1 0 count source timer rb prescaler underflow signal counter of timer rb trbio pin output topl bit in trbioc register set to 1 by program set to 1 by setting 1 to tosst bit in trbocr register set to 0 when interrupt request is acknowledged, or set by program. the above applies under the following conditions. tstart bit in trbcr register 1 0 1 0 01h 00h 01h 00h 01h count starts timer rb primary reloads count starts timer rb primary reloads set to 0 by program waveform output starts waveform output ends waveform output starts waveform output ends set to 0 when counting ends set to 1 by int0 pin input trigger trbpre = 01h, trbpr = 01h trbioc register topl = 0, tocnt = 0 inostg = 1 (int0 one-shot trigger enabled) inoseg = 1 (edge trigger at rising edge) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 162 of 485 rej09b0244-0300 14.2.3.1 one-shot trigger selection in programmable one-shot generation mode and programm able wait one-shot generation mode, operation starts when a one-shot trigger is generated while the tcstf b it in the trbcr register is set to 1 (count starts). a one-shot trigger can be generated by either of the following causes: ? 1 is written to the tosst bit in the trbocr register by a program. ? trigger input from the int0 pin. when a one-shot trigger occurs, the tosstf bit in the trbocr register is set to 1 (one-shot operation in progress) after one or two cycles of the count source have elapsed. then, in programmable one-shot generation mode, count operation begins and one-shot waveform ou tput starts. (in programmable wait one-shot generation mode, count operation starts for the wait period.) if a one- shot trigger occurs while the tosstf bit is set to 1, no retriggering occurs. to use trigger input from the int0 pin, input the trigger after making the following settings: ? set the pd4_5 bit in the pd4 register to 0 (input port). ? select the int0 digital filter with bits int0f1 and int0f0 in the intf register. ? select both edges or one edge with th e int0pl bit in inten register. if one edge is selected, further select falling or rising edge with the inoseg bit in trbioc register. ? set the int0en bit in the in ten register to 0 (enabled). ? after completing the above, set the inostg bit in the trbioc register to 1 (int pin one-shot trigger enabled). note the following points with regard to generatin g interrupt requests by trigger input from the int0 pin. ? processing to handle the interrupts is required. refer to 12. interrupts , for details. ? if one edge is selected, use the pol bit in the int0 ic register to select falling or rising edge. (the inoseg bit in the trbioc register does not affect int0 interrupts). ? if a one-shot trigger occurs while the tosstf bit is set to 1, timer rb operation is not affected, but the value of the ir bit in th e int0ic register changes. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 163 of 485 rej09b0244-0300 14.2.4 programmable wait one-shot generation mode in programmable wait one-shot generation mode, a one-shot pulse is output from the trbo pin by a program or an external trigger input (input to the int0 pin) (refer to table 14.10 programmable wait one-shot generation mode specifications ). when a trigger is generated from that point, the timer outputs a pulse only once for a given length of time equal to the setting va lue in the trbsc register after waiting for a given length of time equal to the setting value in the trbpr register. figure 14.22 shows the trbioc register in programm able wait one-shot generation mode. figure 14.23 shows an operating example of programmable wait one-shot generation mode. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 164 of 485 rej09b0244-0300 notes: 1. the set value is reflected at the following one-shot pulse after writing to registers trbsc and trbpr. 2. do not set both the trbpre and trbpr registers to 00h. table 14.10 programmable wait one-shot generation mode specifications item specification count sources f1, f2, f8, timer ra underflow count operations ? decrement the timer rb primary setting value. ? when a count of the timer rb primar y underflows, the timer reloads the contents of timer rb secondar y before the count continues. ? when a count of the timer rb second ary underflows, the timer reloads the contents of timer rb primary before the count completes and the tosstf bit is set to 0 (one-shot stops). ? when the count stops, the timer reload s the contents of the reload register before it stops. wait time (n+1)(m+1)/fi fi: count source frequency n: value set in the trbpre register , m value set in the trbpr register (2) one-shot pulse output time (n+1)(p+1)/fi fi: count source frequency n: value set in the trbpre register, p: value set in the trbsc register count start conditions ? the tstart bit in the trbcr register is set to 1 (count starts) and the next trigger is generated. ? set the tosst bit in the trbocr register to 1 (one-shot starts). ? input trigger to the int0 pin count stop conditions ? when reloading completes after timer rb underflows during secondary period. ? when the tossp bit in the trbocr regi ster is set to 1 (one-shot stops). ? when the tstart bit in the trbcr register is set to 0 (count starts). ? when the tstop bit in the trbcr regi ster is set to 1 (count forcibly stops). interrupt request generation timing in half a cycle of the count source after timer rb underflows during secondary period (complete at the same time as waveform output from the trbo pin) [timer rb interrupt]. trbo pin function pulse output int0 pin functions ? when the inostg bit in the trbioc register is set to 0 (int0 one-shot trigger disabled): programmable i/o port or int0 interrupt input ? when the inostg bit in the trbioc register is set to 1 (int0 one-shot trigger enabled): external trigger (int0 interrupt input) read from timer the count value can be read out by reading registers trbpr and trbpre. write to timer ? when registers trbpre, tr bsc, and trbpr are written while the count stops, values are written to both the reload register and counter. ? when registers trbpre, trbsc, and trbpr are written to during count operation, values are written to the reload registers only. (1) select functions ? output level select function the topl bit in the trbioc register selects the output level of the one- shot pulse waveform. ? one-shot trigger select function refer to 14.2.3.1 one-shot trigger selection . free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 165 of 485 rej09b0244-0300 figure 14.22 trbioc register in progra mmable wait one-shot generation mode timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw 0 : int0 _ ____ pin one-shot trigger disabled 1 : int0 _ ____ pin one-shot trigger enabled note: 1. rw rw one-shot trigger control bit (1) 0 : falling edge trigger 1 : rising edge trigger tocnt rw topl timer rb output level select bit 0 : outputs one-shot pulse ?h?. outputs ?l? w hen the timer stops or during w ait. 1 : outputs one-shot pulse ?l?. outputs ?h? w hen the timer stops or during w ait. timer rb output sw itch bit set to 0 in programmable w ait one-shot generation mode. b7 b6 b5 b4 ref er to 14.2.3.1 one-shot trigger selection . b3 b2 inoseg b1 b0 0 inostg rw nothing is assigned. if necessary, set to 0. when read, the content is 0. one-shot trigger polarity select bit (1) ? (b7-b4) ? free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 166 of 485 rej09b0244-0300 figure 14.23 operating example of programmable wait one-shot generation mode tosstf bit in trbocr register int0 pin input 1 0 1 0 ir bit in trbic register 1 0 count source timer rb prescaler underflow signal counter of timer rb trbio pin output topl bit in trbioc register set to 1 by program set to 1 by setting 1 to tosst bit in trbocr register, or int0 pin input trigger. set to 0 when interrupt request is acknowledged, or set by program. the above applies under the following conditions. tstart bit in trbcr register 1 0 1 0 01h 00h 00h 01h count starts timer rb secondary reloads timer rb primary reloads set to 0 by program wait starts waveform output starts waveform output ends set to 0 when counting ends trbpre = 01h, trbpr = 01h, trbsc = 04h inostg = 1 (int0 one-shot trigger enabled) inoseg = 1 (edge trigger at rising edge) 04h 03h 02h 01h wait (primary period) one-shot pulse (secondary period) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 167 of 485 rej09b0244-0300 14.2.5 notes on timer rb ? timer rb stops counting after a reset. set the values in the timer rb and timer rb prescalers before the count starts. ? even if the prescaler and timer rb is read out in 16-bit units, these registers are read 1 byte at a time by the mcu. consequently, the timer value may be updated during the period when these two registers are being read. ? in programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the tstart bit in the trbcr register to 0 (c ount stops) or setting th e tossp bit in the trbocr register to 1 (one-shot stops), the timer reloads the value of reload register and stops. therefore, in programmable one-shot generation mode and programmab le wait one-shot generation mode, read the timer count value before the timer stops. ? the tcstf bit remains 0 (count stops) for 1 to 2 cycl es of the count source after setting the tstart bit to 1 (count starts) while the count is stopped. during this time, do not access re gisters associated with timer rb (1) other than the tcstf bit. the tcstf bit remains 1 for 1 to 2 cycles of the count source after setting the tstart bit to 0 (count stops) while the count is in progress. timer rb count ing is stopped when the tcstf bit is set to 0. during this time, do not access re gisters associated with timer rb (1) other than the tcstf bit. note: 1. registers associated with timer rb: trbcr , trbocr, trbioc, trbmr, trbpre, trbsc, and trbpr. ? if the tstop bit in the trbcr register is set to 1 during timer operation, timer rb stops immediately. ? if 1 is written to the tosst or tossp bit in the t rbocr register, the value of the tosstf bit changes after one or two cycles of the count source have elapsed. if the tossp bit is written to 1 during the period between when the tosst bit is written to 1 and when the tosstf bit is set to 1, the tosstf bit may be set to either 0 or 1 depending on the content state. likewise, if the tosst bit is written to 1 during the period between when the tossp bit is written to 1 and when th e tosstf bit is set to 0, the tosstf bit may be set to either 0 or 1. 14.2.5.1 timer mode the following workaround should be performed in timer mode. to write to registers trbpre and trbpr during count operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 168 of 485 rej09b0244-0300 14.2.5.2 programmable waveform generation mode the following three workarounds should be performe d in programmable waveform generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) to change registers trbpre and trbpr during coun t operation (tcstf bit is set to 1), synchronize the trbo output cycle using a timer rb interrupt, etc. this operation should be preformed only once in the same output cycle. also, make sure that writi ng to the trbpr register does not occur during period a shown in figures 14.24 and 14.25. the following shows the detailed workaround examples. ? workaround example (a): as shown in figure 14.24, write to registers trbsc and trbpr in the timer rb interrupt routine. these write operations must be completed by the beginning of period a. figure 14.24 workaround example (a) when timer rb interrupt is used trbo pin output count source/ prescaler underflow signal primary period period a ir bit in trbic register secondary period (b) interrupt sequence instruction in interrupt routine interrupt request is acknowledged (a) interrupt request is generated ensure sufficient time set the secondary and then the primary register immediately (a) period between interrupt request generation and the completion of execution of an instruction. the length of time varies depending on the instruction being executed. the divx instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 169 of 485 rej09b0244-0300 ? workaround example (b): as shown in figure 14.25 detect the start of the primary period by the trbo pin output level and write to registers trbsc and trbpr. these write operations must be completed by the beginning of period a. if the port register?s bit value is read after the port direction register?s bit corresponding to the trbo pin is set to 0 (input mode), the read value indicates the trbo pin output value. figure 14.25 workaround example (b) when trbo pin output value is read (3) to stop the timer counting in the primary period, use the tstop bit in the trbcr register. in this case, registers trbpre and trbpr are initialized and th eir values are set to the values after reset. 14.2.5.3 programmable one-shot generation mode the following two workarounds should be performe d in programmable one-shot generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously du ring count operation (tcstf bit is set to 1), allow three or more cycles of the co unt source for each write interval. ? when the trbpr register is written continuously du ring count operation (tcstf bit is set to 1), allow three or more cycles of the prescal er underflow for each write interval. (2) do not set both the trbpre and trbpr registers to 00h. trbo pin output count source/ prescaler underflow signal primary period period a read value of the port register?s bit corresponding to the trbo pin (when the bit in the port direction register is set to 0) secondary period (i) the trbo output inversion is detected at the end of the secondary period. ensure sufficient time upon detecting (i), set the secondary and then the primary register immediately. (ii) (iii) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 170 of 485 rej09b0244-0300 14.2.5.4 programmable wait one-shot generation mode the following three workarounds should be performe d in programmable wait one-shot generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) do not set both the trbpre and trbpr registers to 00h. (3) set registers trbsc and trbp r using the following procedure. (a) to use ?int0 pin one-shot trigger enabled? as the count start condition set the trbsc register an d then the trbpr register. at this time, after writing to the trbpr register, allow an interval of 0.5 or more cycles of the count source before trigger input from the int0 pin. (b) to use ?writing 1 to tosst bit? as the start condition set the trbsc register, the trbpr register, and then tosst bit. at this time, after writing to the trbpr register, allow an interval of 0.5 or more cycles of the count source before writing to the tosst bit. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 171 of 485 rej09b0244-0300 14.3 timer rd timer rd has 2 16-bit timers (channels 0 and 1). each channel has 4 i/o pins. the operation clock of timer rd is f1 or foco40m. table 14.11 lists the timer rd operation clocks. figure 14.26 shows a block diagram of timer rd. timer rd has 5 modes: ? timer mode - input capture function transfer the counter value to a register with an external signal as the trigger - output compare function detect regi ster value matches with a counter (pin output can be changed at detection) the following 4 modes use th e output comp are function. ? pwm mode output pulse of any width continuously ? reset synchronous pwm mode output three-phase waveforms (6) without sawtooth wave modulation and dead time ? complementary pwm mode output three-phase waveforms (6) with triangular wave modulation and dead time ? pwm3 mode output pwm waveforms (2) with a fixed period in the input capture function, output compare function , and pwm mode, channels 0 and 1 have the equivalent functions, and functions or modes can be selected individually for each pin. also, a combina tion of these functions and modes can be used in 1 channel. in reset synchronous pwm mode, complementary pwm mo de, and pwm3 mode, a waveform is output with a combination of count ers and registers in channels 0 and 1. tables 14.12 to 14.20 list the pin functions of timer rd. table 14.11 timer rd operation clocks condition operation clock of timer rd the count source is f1, f2, f4, f8, f32, or trdclk input (bits tck2 to tck0 in registers trdcr0 and trdcr1 are set to a value from 000b to 101b). f1 the count source is foco40m (bits tck2 to tck0 in registers trdcr0 and trdcr1 are set to 110b). foco40m free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 172 of 485 rej09b0244-0300 x: can be 0 or 1, no change in outcome note: 1. set the pd2_0 bit in the pd2 register to 0 (input mode) at time r mode trigger input (input capt ure function) and external clo ck input (trdclk). x: can be 0 or 1, no change in outcome note: 1. set the pd2_1 bit in the pd2 register to 0 (input mode) at timer mode trigger input (input capture function). x: can be 0 or 1, no change in outcome note: 1. set the pd2_2 bit in the pd2 register to 0 (input mode) at timer mode trigger input (input capture function). table 14.12 pin functions trdioa0/trdclk(p2_0) register trdoer1 trdfcr trdiora0 function bit ea0 pwm3 stclk cmd1, cmd0 ioa3 ioa2_ioa0 setting value 0 0 0 00b x xxxb pwm3 mode waveform output 0 1 0 00b 1 001b, 01xb timer mode waveform output (output compare function) x 1 0 00b x 1xxb timer mode trigger input (input capture function) (1) 1 1 xxb x 000b external clock input (trdclk) (1) other than above i/o port table 14.13 pin functions trdiob0(p2_1) register trdoer1 trdfcr trdpmr trdiora0 function bit eb0 pwm3 cmd1, cmd0 pwmb0 iob2_iob0 setting value 0x 1 x b x xxxb complementary pwm mode waveform output 0 x 01b x xxxb reset synchronous pwm mode waveform output 0 0 00b x xxxb pwm3 mode waveform output 0 1 00b 1 xxxb pwm mode waveform output 0 1 00b 0 001b, 01 x b timer mode waveform output (output compare function) x 1 00b 0 1xxb timer mode trigger input (input capture function) (1) other than above i/o port table 14.14 pin functions trdioc0(p2_2) register trdoer1 trdfcr trdpmr trdiorc0 function bit ec0 pwm3 cmd1, cmd0 pwmc0 ioc2_ioc0 setting value 0x 1 x b x xxxb complementary pwm mode waveform output 0 x 01b x xxxb reset synchronous pwm mode waveform output 0 1 00b 1 xxxb pwm mode waveform output 0 1 00b 0 001b, 01 x b timer mode waveform output (output compare function) x 1 00b 0 1xxb timer mode trigger input (input capture function) (1) other than above i/o port free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 173 of 485 rej09b0244-0300 x: can be 0 or 1, no change in outcome note: 1. set the pd2_3 bit in the pd2 register to 0 (input mode) at timer mode trigger input (input capture function). x: can be 0 or 1, no change in outcome note: 1. set the pd2_4 bit in the pd2 register to 0 (input mode) at timer mode trigger input (input capture function). x: can be 0 or 1, no change in outcome note: 1. set the pd2_5 bit in the pd2 register to 0 (input mode) at timer mode trigger input (input capture function). table 14.15 pin functions trdiod0(p2_3) register trdoer1 trdfcr trdpmr trdiorc0 function bit ed0 pwm3 cmd1, cmd0 pwmd0 iod2_iod0 setting value 0x 1 x b x xxxb complementary pwm mode waveform output 0 x 01b x xxxb reset synchronous pwm mode waveform output 0 1 00b 1 xxxb pwm mode waveform output 0 1 00b 0 001b, 01 x b timer mode waveform output (output compare function) x 1 00b 0 1xxb timer mode trigger input (input capture function) (1) other than above i/o port table 14.16 pin functions trdioa1(p2_4) register trdoer1 trdfcr trdiora1 function bit ea1 pwm3 cmd1, cmd0 ioa2_ioa0 setting value 0x 1 x b xxxb complementary pwm mode waveform output 0 x 01b xxxb reset synchronous pwm mode waveform output 0 1 00b 001b, 01 x b timer mode waveform output (output compare function) x 1 00b 1xxb timer mode trigger input (input capture function) (1) other than above i/o port table 14.17 pin functions trdiob1(p2_5) register trdoer1 trdfcr trdpmr trdiora1 function bit eb1 pwm3 cmd1, cmd0 pwmb1 iob2_iob0 setting value 0x 1 x b x xxxb complementary pwm mode waveform output 0 x 01b x xxxb reset synchronous pwm mode waveform output 0 1 00b 1 xxxb pwm mode waveform output 0 1 00b 0 001b, 01 x b timer mode waveform output (output compare function) x 1 00b 0 1xxb timer mode trigger input (input capture function) (1) other than above i/o port free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 174 of 485 rej09b0244-0300 x: can be 0 or 1, no change in outcome note: 1. set the pd2_6 bit in the pd2 register to 0 (input mode) at timer mode trigger input (input capture function). x: can be 0 or 1, no change in outcome note: 1. set the pd2_7 bit in the pd2 register to 0 (input mode) at timer mode trigger input (input capture function). table 14.18 pin functions trdioc1(p2_6) register trdoer1 trdfcr trdpmr trdiorc1 function bit ec1 pwm3 cmd1, cmd0 pwmc1 ioc2_ioc0 setting value 0x 1 x b x xxxb complementary pwm mode waveform output 0 x 01b x xxxb reset synchronous pwm mode waveform output 0 1 00b 1 xxxb pwm mode waveform output 0 1 00b 0 001b, 01 x b timer mode waveform output (output compare function) x 1 00b 0 1xxb timer mode trigger input (input capture function) (1) other than above i/o port table 14.19 pin functions trdiod1(p2_7) register trdoer1 trdfcr trdpmr trdiorc1 function bit ed1 pwm3 cmd1, cmd0 pwmd1 iod2_iod0 setting value 0x 1 x b x xxxb complementary pwm mode waveform output 0 x 01b x xxxb reset synchronous pwm mode waveform output 0 1 00b 1 xxxb pwm mode waveform output 0 1 00b 0 001b, 01 x b timer mode waveform output (output compare function) x 1 00b 0 1xxb timer mode trigger input (input capture function) (1) other than above i/o port table 14.20 pin functions int0 (p4_5) register trdoer2 inten pd4 function bit pto int0pl int0en pd4_5 setting value 10 1 0 pulse output forced cutoff signal input other than above i/o port or int0 interrupt input free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 175 of 485 rej09b0244-0300 figure 14.26 block diagram of timer rd trdi register data bus trdgrai register trdgrbi register trdgrci register trdgrdi register trdcri register trdiorai register trdiorci register trdsri register trdieri register trdpocri register trdstr register trdmr register trdpmr register trdfcr register trdoer1 register trdoer2 register trdocr register timer rd control circuit int0 trdioa0/trdclk trdiob0 trdioc0 trdiod0 trdiob1 trdioc1 trdiod1 trdioa1 count source select circuit f1, f2, f4, f8, f32, foco40m channel 0 interrupt request channel 1 interrupt request a/d trigger channel i i = 0 or 1 trddfi register free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 176 of 485 rej09b0244-0300 14.3.1 count sources the count source selection method is the same in all modes. however, in pwm3 mode, the external clock cannot be selected. i = 0 or 1 note: 1. the count source foco40m can be used with vcc = 3.0 to 5.5 v. figure 14.27 block diagram of count source set the pulse width of the external clock which inputs to the trdclk pin to 3 cycles or above of the operation clock of timer rd (refer to table 14.11 timer rd operation clocks ). when selecting foco40m for the count source, set the fra00 bit in th e fra0 register to 1 (high-speed on- chip oscillator on) before setting bits tck2 to tck0 in the trdcri register (i = 0 or 1) to 110b (foco40m). table 14.21 count source selection count source selection f1, f2, f4, f8, f32 the coun t source is selected by bits tck2 to tck0 in the trdcri register. foco40m (1) the fra00 bit in the fra0 register is set to 1 (high-speed on-chip oscillator frequency). bits tck2 to tck0 in the trdcri register is set to 110b (foco40m). external signal input to trdclk pin the stclk bit in the trdfcr register is set to 1 (external clock input enabled). bits tck2 to tck0 in the tr dcri register are set to 101b (count source: external clock). the valid edge is selected by bits ckeg1 to ckeg0 in the trdcri register. the pd2_0 bit in the pd2 register is set to 0 (input mode). trdclk/ trdioa0 tck2 to tck0 trdi register tck2 to tck0, ckeg1 to ckeg0: bits in trdcri register stclk: bit in trdfcr register f1 f2 f4 f8 f32 = 001b = 010b = 011b = 000b = 101b = 100b valid edge selected ckeg1 to ckeg0 trdioa0 i/o or programmable i/o port count source stclk = 1 stclk = 0 foco40m = 110b free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 177 of 485 rej09b0244-0300 14.3.2 buffer operation the trdgrci (i = 0 or 1) register can be used as the buffer register of the trdgrai register, and the trdgrdi register can be used as the buffer register of the trdgrbi register by means of bits bfci and bfdi in the trdmr register. ? trdgrai buffer register: trdgrci register ? trdgrbi buffer register: trdgrdi register buffer operation depends on the mode. table 14.22 lists the buffer operation in each mode. figure 14.28 shows the buffer operation in input capture function, and figure 14.29 shows the buffer operation in output compare function. i = 0 or 1 figure 14.28 buffer operation in input capture function table 14.22 buffer operation in each mode function and mode transfer timing transfer register input capture function input capture sign al input transfer content in trdgrai (trdgrbi) register to buffer register output compare function compare match with trdi register and trdgrai (trdgrbi) register transfer content in buffer register to trdgrai (trdgrbi) register pwm mode reset synchronous pwm mode compare match withtrd0 register and trdgra0 register transfer content in buffer register to trdgrai (trdgrbi) register complementary pwm mode ? compare match with trd0 register and trdgra0 register ? trd1 register underflow transfer content in buffer register to registers trdgrb0, trdgra1, and trdgrb1 pwm3 mode compare match with trd0 register and trdgra0 register transfer content in buffer register to registers trdgra0, trdgrb0, trdgra1, and trdgrb1 m transfer n trdgrai register n-1 n+1 trdioai input trdi register i = 0 or 1 the above applies under the following conditions: ? the bfci bit in the trdmr register is set to 1 (the trdgrci register is used as the buffer register of the trdgrai register). ? bits ioa2 to ioa0 in the trdiorai register are set to 100b (input capture at the falling edge). m transfer trdgrci register (buffer) n trdgrci register (buffer) trdgrai register trdi trdioai input (input capture signal) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 178 of 485 rej09b0244-0300 figure 14.29 buffer operation in output compare function perform the following for the timer mode (i nput capture and output compare functions). when using the trdgrci (i = 0 or 1) register as the buffer register of the trdgrai register ? set the ioc3 bit in the trdi orci register to 1 (general register or buffer register). ? set the ioc2 bit in the trdiorci register to the same value as the ioa2 bit in the trdiorai register. when using the trdgrdi register as the buffer register of the trdgrbi register ? set the iod3 bit in the trdi ordi register to 1 (general register or buffer register). ? set the iod2 bit in the trdiorci register to the same value as the iob2 bit in the trdiorai register. bits imfc and imfd in the trdsri register are set to 1 at the input edge of the trdioci pin when also using registers trdgrci and trdgrdi as the buffer register in the input capture function. when also using registers trdgrci an d trdgrdi as buffer registers for the output compare function, reset synchronous pwm mode, complementary pwm mode, and pwm3 mode, bits imfc and imfd in the trdsri register are set to 1 by a compar e match with the trdi register. mn trdgrai register m-1 m+1 trdi register i = 0 or 1 the above applies under the following conditions: ? bfci bit in the trdmr register is set to 1 (the trdgrci register is used as the buffer register of the trdgrai register). ? bits ioa2 to ioa0 in the trdiorai register are set to 001b (?l? output by the compare match). n transfer trdgrci register (buffer) m trdioai output trdgrci register (buffer) trdgrai register comparator trdi compare match signal free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 179 of 485 rej09b0244-0300 14.3.3 synchronous operation the trd1 register is synchron ized with the trd0 register. ? synchronous preset when the sync bit in the trdmr regi ster is set to 1 (synchronous operation), the data is written to both the trd0 and trd1 registers afte r writing to the trdi register. ? synchronous clear when the sync bit in the trdmr register is set to 1 and bits cclr2 to cclr0 in the trdcri register are set to 011b (synchronous clear), the trd0 register is set to 0000h at the same time as the trd1 register is set to 0000h. also, when the sync bit in the trdmr register is set to 1 and bits cclr2 to cclr0 in the trdcri register are set to 011b (synchronous clear), the trd1 re gister is set to 0000h at the same time as the trd0 register is set to 0000h. figure 14.30 synchronous operation value in trd0 register trdioa0 input n n is set n writing value in trd1 register n set to 0000h with trd0 register set to 0000h by input capture the above applies under the following conditions: ? the sync bit in the trdmr register is set to 1 (synchronous operation). ? bits cclr2 to cclr0 in the trdcr0 register are set to 001b (set the trd0 register to 0000h in input capture). bits cclr2 to cclr0 in the trdcr1 register are set to 011b (set the trd1 register to 0000h synchronizing with the trd0 register). ? bits ioa2 to ioa0 in the trdiora0 register are set to 100b. ? bits cmd1 to cmd0 in the trdfcr register are set to 00b. (input capture at the rising edge of the trdioa0 input) the pwm 3 bit in the trdfcr register is set to 1. n is set free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 180 of 485 rej09b0244-0300 14.3.4 pulse output forced cutoff in the output compare function, pwm mode, reset synchronous pwm mode, complementary pwm mode, and pwm3 mode, the trdioji (i = 0 or 1, j = either a, b, c, or d) output pin can be forcibly set to a programmable i/o port by the int0 pin input, and pulse output can be cut off. the pins used for output in these functions or modes can function as the output pin of timer rd when the applicable bit in the trdoer1 register is set to 0 (enable timer rd output). when the pto bit in the trdoer2 register to 1 (int0 of pulse output forced cutoff signal input enabled), all bits in the trdoer1 register are set to 1 (disable timer rd output, the trdioji output pin is used as the programmable i/o port) after ?l? is applied to the int0 pin. the trdioji output pin is set to the programmable i/o port after ?l? is applied to the int0 pin and waiting for 1 to 2 cycles of the timer rd operatio n clock (refer to table 14.11 timer rd operation clocks ). set as below when using this function: ? set the pin status (high impedance, ?l? or ?h? output) to pulse output forced cutoff by registers p2 and pd2. ? set the int0en bit in the in ten register to 1 (enable int0 input) and the int0pl bit to 0 (one edge). ? set the pd4_5 bit in the pd4 register to 0 (input mode). ? set the int0 digital filter by bits int0f1 to int0f0 in the intf register. ? set the pto bit in the trdoer2 register to 1 (enable pulse output forced cutoff signal input int0 ). according to the selection of the pol bit in the int0ic register an d change of the int0 pin input, the ir bit in the int0ic register is set to 1 (interrupt request). refer to 12. interrupts for details of interrupts. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 181 of 485 rej09b0244-0300 figure 14.31 pulse output forced cutoff int0 input trdioa0 pto bit d s q ea0 bit trdiob0 d s q eb0 bit trdioc0 d s q ec0 bit trdiod0 d s q ed0 bit trdioa1 d s q ea1 bit trdiob1 d s q eb1 bit trdioc1 d s q ec1 bit trdiod1 d s q ed1 bit port p2_0 output data port p2_0 input data port p2_1 output data port p2_1 input data port p2_2 output data port p2_2 input data port p2_3 output data port p2_3 input data port p2_4 output data port p2_4 input data port p2_5 output data port p2_5 input data port p2_6 output data port p2_6 input data port p2_7 output data port p2_7 input data pto: bit in trdoer2 register ea0, eb0, ec0, ed0, ea1, eb1, ec1, ed1: bits in trdoer1 register ea0 bit writing value eb0 bit writing value ec0 bit writing value ed0 bit writing value ea1 bit writing value eb1 bit writing value ec1 bit writing value ed1 bit writing value timer rd output data timer rd output data timer rd output data timer rd output data timer rd output data timer rd output data timer rd output data timer rd output data free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 182 of 485 rej09b0244-0300 14.3.5 input capture function the input capture function measures the external signal width and period . the content of the trdi register (counter) is transferred to the trdgrji re gister as a trigger of the trdioji (i = 0 or 1, j = either a, b, c, or d) pin external signal (input cap ture). since this function is enabled with a combination of the trdioji pin and trdgrji register, the input cap ture function, or any other mode or func tion, can be selected for each individual pin. the trdgra0 register can also select foco 128 signal as input-capture trigger input. figure 14.32 shows a block diag ram of input capture function, table 14.23 lists the input capture function specifications. figures 14.33 to 14.43 show the register s associated with input capture function, and figure 14.44 shows an operating example of input capture function. figure 14.32 block diagram of input capture function i = 0 or 1 note 1: when the bfci bit in the trdmr register is set to 1 (the trdgrci register is used as the buffer register of the trdgrai register). note 2: when the bfdi bit in the trdmr register is set to 1 (the trdgrdi register is used as the buffer register of the trdgrbi register). trdgrai register trdi register input capture signal trdioai (3) trdgrci register trdgrbi register input capture signal trdgrdi register trdiobi (note 1) (note 2) trdioci trdiodi note 3: the trigger input of the trdgra0 register can select the trdioa0 pin input or foco128 signal. trdioa0 divided by 128 ioa3 = 0 ioa3 = 1 foco foco128 input capture signal input capture signal input capture signal free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 183 of 485 rej09b0244-0300 i = 0 or 1, j = either a, b, c, or d table 14.23 input capture function specifications item specification count sources f1, f2, f4, f8, f32, foco40m external signal input to the trdclk pin (valid edge selected by a program) count operations increment count period when bits cclr2 to cclr0 in the trdcri register are set to 000b (free-running operation). 1/fk 65536 fk: freq uency of count source count start condition 1 (count starts) is writte n to the tstarti bit in the trdstr register. count stop condition 0 (count stops) is writte n to the tstarti bit in the trdstr register when the cseli bit in the trdstr register is set to 1. interrupt request generation timing ? input capture (valid edge of trdioji input or foco128 signal edge) ? trdi register overflows trdioa0 pin function programmable i/o port, inpu t-capture input, or trdclk (external clock) input trdiob0, trdioc0, trdiod0, trdioa1 to trdiod1 pin functions programmable i/o port, or input-c apture input (selectable by pin) int0 pin function programmable i/o port or int0 interrupt input read from timer the count value can be read by reading the trdi register. write to timer ? when the sync bit in the trdmr register is set to 0 (channels 0 and 1 operate independently). data can be written to the trdi register. ? when the sync bit in the trdmr register is set to 1 (channels 0 and 1 operate synchronously). data can be written to both the trd0 and trd1 registers by writing to the trdi register. select functions ? input-capture input pin selected either 1 pin or multiple pins amon g trdioai, trdiobi, trdioci, or trdiodi. ? input-capture input valid edge selected the rising edge, falling edge, or both the ri sing and falling edges ? the timing when the trdi register is set to 0000h at overflow or input capture ? buffer operation (refer to 14.3.2 buffer operation. ) ? synchronous operation (refer to 14.3.3 synchronous operation. ) ? digital filter the trdioji input is sampled, an d when the sampled input level match as 3 times, the level is determined. ? input-capture trigger selected foco128 can be selected for input-capture trigger input of the trdgra0 register. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 184 of 485 rej09b0244-0300 figure 14.33 registers trdstr and trdmr in input capture function timer rd start register (1) symbol address after reset trdstr 0137h 11111100b bit symbol bit name function rw note: 1. b3 b2 csel1 b1 b0 set to 1 in the input capture function. trd1 count operation select bit set to 1 in the input capture function. set the trdstr register using the mov instruction (do not use the bit handling instruction). refer to 14.3.12.1 t rdst r re g is t e r of notes on timer rd. rw rw nothing is assigned. if necessary, set to 0. when read, the content is 1. ? trd0 count operation select bit b7 b6 b5 b4 ? (b7-b4) csel0 11 tsta rt0 rw tsta rt1 rw trd1 count start flag 0 : count stops 1 : count starts trd0 count start flag 0 : count stops 1 : count starts timer rd mode register symbol address after reset trdmr 0138h 00001110b bit symbol bit name function rw b3 b2 bfd0 b1 b0 sync b7 b6 b5 b4 rw ? (b3-b1) ? timer rd synchronous bit 0 : registers trd0 and trd1 operate independently 1 : registers trd0 and trd1 operate synchronously nothing is assigned. if necessary, set to 0. when read, the content is 1. rw trdgrd0 register function select bit 0 : general register 1 : buffer register of trdgrb0 register trdgrc1 register function select bit 0 : general register 1 : buffer register of trdgra1 register rw trdgrc0 register function select bit 0 : general register 1 : buffer register of trdgra0 register bfc0 rw rw bfc1 bfd1 trdgrd1 register function select bit 0 : general register 1 : buffer register of trdgrb1 register free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 185 of 485 rej09b0244-0300 figure 14.34 trdpmr register in input capture function timer rd pwm mode register symbol address after reset trdpmr 0139h 10001000b bit symbol bit name function rw ? (b7) ? pwmb1 pwmc1 rw nothing is assigned. if necessary, set to 0. when read, the content is 1. pwm mode of trdioc1 select bit set to 0 (timer mode) in the input capture function. pwmd1 pwm mode of trdiod1 select bit ? pwm mode of trdiob1 select bit set to 0 (timer mode) in the input capture function. rw rw nothing is assigned. if necessary, set to 0. when read, the content is 1. set to 0 (timer mode) in the input capture function. pwm mode of trdiod0 select bit set to 0 (timer mode) in the input capture function. pwmd0 rw rw pwmc0 rw pwm mode of trdiob0 select bit set to 0 (timer mode) in the input capture function. pwm mode of trdioc0 select bit set to 0 (timer mode) in the input capture function. 000 b7 b6 b5 b4 b3 b2 ? (b3) b1 b0 00 0 pwmb0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 186 of 485 rej09b0244-0300 figure 14.35 trdfcr register in input capture function timer rd function control register symbol address after reset trdfcr 013ah 10000000b bit symbol bit name function rw notes: 1. 2. when bits cmd1 to cmd0 are set to 00b (timer mode, pwm mode, or pwm3 mode), the setting of the pwm3 bit is enabled. b3 b2 ols1 b1 b0 00 1 b7 b6 b5 b4 rw cmd1 rw combination mode select bits (1) set to 00b (timer mode, pwm mode, or pwm3 mode) in the input capture function. cmd0 normal-phase output level select bit (in reset synchronous pwm mode or complementary pwm mode) this bit is disabled in the input capture function. set bits cmd1 to cmd0 w hen both the tstart0 and tstart1 bits are set to 0 (count stops). ols0 rw rw counter-phase output level select bit (in reset synchronous pwm mode or complementary pwm mode) this bit is disabled in the input capture function. a/d trigger enable bit (in complementary pwm mode) this bit is disabled in the input capture function. rw pwm3 rw adtrg adeg a/d trigger edge select bit (in complementary pwm mode) this bit is disabled in the input capture function. rw pwm3 mode select bit (2) set this bit to 1 (other than pwm3 mode) in the input capture function. stclk external clock input select bit 0 : external clock input disabled 1 : external clock input enabled rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 187 of 485 rej09b0244-0300 figure 14.36 registers trddf0 to trddf1 in input capture function timer rd digital filter function select register i (i = 0 or 1) symbol address after reset trddf0 trddf1 013eh 013fh 00h 00h bit symbol bit name function rw b3 b2 dfd b1 b0 dfc b7 b6 b5 b4 rw dfb rw dfa trdioa pin digital filter function select bit 0 : function is not used 1 : function is used trdiob pin digital filter function select bit 0 : function is not used 1 : function is used rw rw trdiod pin digital filter function select bit 0 : function is not used 1 : function is used trdioc pin digital filter function select bit 0 : function is not used 1 : function is used nothing is assigned. if necessary, set to 0. when read, the content is 0. clock select bits for digital filter function dfck1 rw b7 b6 0 0 : f32 0 1 : f8 1 0 : f1 1 1 : count source (clock selected by bits tck2 to tck0 in the trdcri register) ? (b5-b4) dfck0 rw ? free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 188 of 485 rej09b0244-0300 figure 14.37 registers trdcr0 to trdc r1 in input capture function timer rd control register i (i = 0 or 1) symbol address after reset trdcr0 trdcr1 0140h 0150h 00h 00h bit symbol bit name function rw notes: 1. 2. 3. rw tck1 rw tck0 rw rw rw cclr2 cclr1 rw count source select bits b2 b1 b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : trdclk input (1) 1 1 0 : foco40m 1 1 1 : do not set. external clock edge select bits (2) b4 b3 0 0 : count at the rising edge 0 1 : count at the fa lling edge 1 0 : count at both edges 1 1 : do not set. b7 b6 b5 b4 b3 b2 ckeg0 b1 b0 tck2 this setting is enabled w hen the sync bit in the trdmr register is set to 1 (registers trd0 and trd1 operate synchronously). bits ckeg1 to ckeg0 are enabled w hen bits tck2 to tck0 are set to 101b (trdclk input) and the stclk bit in the trdfcr register is set to 1 (external clock input enabled). rw ckeg1 cclr0 rw b7 b6 b5 0 0 0 : disable clear (free-running operation) 0 0 1 : clear by input capture in the trdgrai register 0 1 0 : clear by input capture in the trdgrbi register 0 1 1 : synchronous clear (clear simultaneously w ith other channel counter) (3) 1 0 0 : do not set. 1 0 1 : clear by input capture in the trdgrci register 1 1 0 : clear by input capture in the trdgrdi register 1 1 1 : do not set. trdi counter clear select bits this setting is enabled w hen the stclk bit in the trdfcr register is set to 1 (external clock input enabled). free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 189 of 485 rej09b0244-0300 figure 14.38 registers trdiora0 to trdiora1 in input capture function timer rd i/o control register ai (i = 0 or 1) symbol address after reset trdiora 0 trdiora 1 0141h 0151h 10001000b 10001000b bit symbol bit name function rw notes: 1. 2. 3. 4. the ioa3 bit is enabled in the trdiora0 register only. set to the ioa3 bit in trdiora1 to 1. the ioa3 bit is enabled w hen the ioa2 bit is set to 1 (input capture function). trdgra mode select bit (1) set to 1 (input capture) in the input capture function. rw input capture input sw itch bit (3, 4) 0 : foco128 signal 1 : trdioa0 pin input rw to select 1 (the trdgrci register is used as a buffer register of the trdgrai register) for this bit by the bfci bit in the trdmr register, set the ioc2 bit in the trdiorci register to the same value as the ioa2 bit in the trdiorai register. trdgrb mode select bit (2) rw rw ioa 1 ioa 0 trdgra control bits b1 b0 0 0 : input capture to the trdgrai register at the rising edge 0 1 : input capture to the trdgrai register at the falling edge 1 0 : input capture to the trdgrai register at both edges 1 1 : do not set. b7 b6 b5 b4 1 ioa 2 1 iob0 iob1 rw b3 b2 ioa 3 b1 b0 to select 1 (the trdgrdi register is used as a buffer register of the trdgrbi register) for this bit by the bfdi bit in the trdmr register, set the iod2 bit in the trdiorci register to the same value as the iob2 bit in the trdiorai register. set to 1 (input capture) in the input capture function. rw ? (b7) iob2 rw trdgrb c ontrol bits b5 b4 0 0 : input capture to the trdgrbi register at the rising edge 0 1 : input capture to the trdgrbi register at the falling edge 1 0 : input capture to the trdgrbi register at both edges 1 1 : do not set. nothing is assigned. if necessary, set to 0. when read, the content is 1. ? free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 190 of 485 rej09b0244-0300 figure 14.39 registers trdiorc0 to trdiorc1 in input capture function timer rd i/o control register ci (i = 0 or 1) symbol address after reset trdiorc0 trdiorc1 0142h 0152h 10001000b 10001000b bit symbol bit name function rw notes: 1. 2. to select 1 (the trdgrci register is used as a buffer register of the trdgrai register) for this bit by the bfci bit in the trdmr register, set the ioc2 bit in the trdiorci register to the same value as the ioa2 bit in the trdiorai register. rw iod0 iod1 rw set to 1 (general register or buffer register) in the input capture function. to select 1 (the trdgrdi register is used as a buffer register of the trdgrbi register) for this bit by the bfdi bit in the trdmr register, set the iod2 bit in the trdiorci register to the same value as the iob2 bit in the trdiorai register. trdgrd mode select bit (2) set to 1 (input capture) in the input capture function. rw iod3 iod2 rw trdgrd c ontr ol bits b5 b4 0 0 : input capture to the trdgrdi register at the rising edge 0 1 : input capture to the trdgrdi register at the falling edge 1 0 : input capture to the trdgrdi register at both edges 1 1 : do not set. trdgrd register function select bit b3 b2 ioc3 b1 b0 11 ioc2 11 b7 b6 b5 b4 rw rw ioc1 ioc0 trdgrc c ontr ol bits b1 b0 0 0 : input capture to the trdgrci register at the rising edge 0 1 : input capture to the trdgrci register at the falling edge 1 0 : input capture to the trdgrci register at both edges 1 1 : do not set. trdgrc mode select bit (1) set to 1 (input capture) in the input capture function. rw trdgrc register function select bit set to 1 (general register or buffer register) in the input capture function. rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 191 of 485 rej09b0244-0300 figure 14.40 registers trdsr0 to trdsr1 in input capture function timer rd status register i (i = 0 or 1) symbol address after reset trdsr0 trdsr1 0143h 0153h 11100000b 11000000b bit symbol bit name function rw notes: 1. 2. 3. 4. edge selected by bits iok1 to iok0 (k = c or d) in the trdiorci register including w hen the bfki bit in the trdmr register is set to 1 (trdgrki is used as the buffer register). edge selected by bits ioj1 to ioj0 (j = a or b) in the trdiorai register. the w riting results are as follow s: ? this bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. ? this bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) ? this bit remains unchanged if 1 is w ritten to it. b3 b2 imfd b1 b0 b7 b6 b5 b4 rw imfb rw input capture/compare match flag a [source for setting this bit to 0] write 0 after read (2) [source for setting this bit to 1] trdsr0 r egis ter : foco128 signal edge w hen the ioa3 bit in the trdiora0 register is set to 0 (foco128 signal) trdioa0 pin input edge w hen the ioa3 bit in the trdiora0 register is set to 1 (trdioa0 input) (3) trdsr1 r egis ter : input edge of trdioa1 pin (3) input capture/compare match flag b [source for setting this bit to 0] write 0 after read (2) [source for setting this bit to 1] input edge of trdiobi pin (3) imfa input capture/compare match flag c [source for setting this bit to 0] write 0 after read (2) [source for setting this bit to 1] input edge of trdioci pin (4) nothing is assigned to b5 in the trdsr0 register. when w riting to b5, w rite 0. when reading, the content is 1. imfc rw rw input capture/compare match flag d [source for setting this bit to 0] write 0 after read (2) [source for setting this bit to 1] input edge of trdiodi pin (4) overflow flag [source for setting this bit to 0] write 0 after read (2) [source for setting this bit to 1] when the trdi register overflow s ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. rw ov f udf underflow flag (1) this bit is disabled in the input capture function. rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 192 of 485 rej09b0244-0300 figure 14.41 registers trdier0 to trdier1 in input capture function figure 14.42 registers trd0 to trd1 in input capture function timer rd interrupt enable register i (i = 0 or 1) symbol address after reset trdier0 trdier1 0144h 0154h 11100000b 11100000b bit symbol bit name function rw b3 b2 imied b1 b0 b7 b6 b5 b4 rw imieb rw input capture/compare match interrupt enable bit a 0 : disable interrupt (imia) by the imfa bit 1 : enable interrupt (imia) by the imfa bit input capture/compare match interrupt enable bit b 0 : disable interrupt (imib) by the imfb bit 1 : enable interrupt (imib) by the imfb bit imiea rw input capture/compare match interrupt enable bit d 0 : disable interrupt (imid) by the imfd bit 1 : enable interrupt (imid) by the imfd bit overflow /underflow interrupt enable bit 0 : disable interrupt (ovi) by the ovf bit 1 : enable interrupt (ovi) by the ovf bit rw input capture/compare match interrupt enable bit c 0 : disable interrupt (imic) by the imfc bit 1 : enable interrupt (imic) by the imfc bit imiec rw ov ie ? (b7-b5) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. timer rd counter i (i = 0 or 1) (1) symbol address after reset trd0 trd1 0147h-0146h 0157h-0156h 0000h 0000h setting range rw note: 1. function count the count source. count operation is incremented. when an overflow occurs, the ovf bit in the trdsri register is set to 1. 0000h to ffffh rw access the trdi register in 16-bit units. do not access it in 8-bit units. b0 b7 ( b8) b0 ( b15) b7 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 193 of 485 rej09b0244-0300 figure 14.43 registers trdgrai, trdgrbi, trdgrci, and trdgrdi in input capture function the following registers are disabled in the inpu t capture function: trdo er1, trdoer2, trdocr, trdpocr0, and trdpocr1. i = 0 or 1, j = either a, b, c, or d bfci, bfdi: bits in trdmr register set the pulse width of the input capture signal applied to the trdioji pin to 3 cycles or more of the timer rd operation clock (refer to table 14.11 timer rd operation clocks ) for no digital filter (the dfj bit in the trddfi register set to 0). table 14.24 trdgrji register functions in input capture function register setting register function input-capture input pin trdgrai ? general register the value in the trdi regist er can be read at input capture. trdioai trdgrbi trdiobi trdgrci bfci = 0 general register the value in the trdi regist er can be read at input capture. trdioci trdgrdi bfdi = 0 trdiodi trdgrci bfci = 1 buffer register the value in the trdi regist er can be read at input capture. (refer to 14.3.2 buffer operation .) trdioai trdgrdi bfdi = 1 trdiobi timer rd general registers ai, bi, ci, and di (i = 0 or 1) (1) symbol address after reset trdgra 0 trdgrb0 trdgrc0 trdgrd0 trdgra 1 trdgrb1 trdgrc1 trdgrd1 0149h-0148h 014bh-014ah 014dh-014ch 014fh-014eh 0159h-0158h 015bh-015ah 015dh-015ch 015fh-015eh ffffh ffffh ffffh ffffh ffffh ffffh ffffh ffffh rw note: 1. rw function ref er to table 14.24 trdgrji register functions in input capture function . access registers trdgrai to trdgrdi in 16-bit units. do not access them in 8-bit units. b0 b7 ( b8) b0 ( b15) b7 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 194 of 485 rej09b0244-0300 figure 14.44 operating example of input capture function set to 0 by a program transfer i = 0 or 1 the above applies under the following conditions: bits cclr2 to cclr0 in the trdcri register are set to 001b. (the trdi register set to 0000h by trdgrai register input capture). bits tck2 to tck0 in the trdcri register are set to 101b (trdclk input for the count source). bits ckeg1 to ckeg0 in the trdcri register are set to 01b (count at the falling edge for the count source). bits ioa2 to ioa0 in the trdiorai register are set to 101b (input capture at the falling edge of the trdioai input). the bfci bit in the trdmr register is set to 1 (the trdgrci regi ster is used as the buffer register of the trdgrai register). count value in trdi register ffffh 0009h 0006h tstarti bit in trdstr register 65536 trdgrai register 0000h 1 0 trdioai input trdgrci register imfa bit in trdsri register ovf bit in trdsri register 0009h 0006h 0006h 1 0 1 0 trdclk input count source transfer free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 195 of 485 rej09b0244-0300 14.3.5.1 digital filter the trdioji input is sampled, and when the sampled input level matches 3 times, its level is determined. select the digital filter function and sampling clock by the trddfi register. figure 14.45 block diagram of digital filter clock period selected by bits tck2 to tck0 or bits dfck1 to dfck0 sampling clock trdioji input signal input signal through digital filtering transmission cannot be performed without 3-time match because the input signal is assumed to be noise. signal transmission delayed up to 5-sampling clock recognition of the signal change with 3-time match i = 0 or 1, j = either a, b, c, or d tck0 to tck2: bits in trdcri register dfck0 to dfck1 and dfj: bits in trddf register ioa0 to ioa2 and iob0 to iob2: bits in trdiorai register ioc0 to ioc3 and iod0 to iod3: bits in trdiorci register c dq latch c dq latch c dq latch match detection circuit edge detection circuit dfj sampling clock ioa2 to ioa0 iob2 to iob0 ioc3 to ioc0 iod3 to iod0 dfck1 to dfck0 trdioji input signal f32 f8 f1 c dq latch c dq latch timer rd operation clock f1, foco40m) count source = 101b = 100b = 011b = 110b = 010b = 001b foco40m f4 f2 f8 f32 trdclk f1 = 000b = 00b = 01b = 10b = 11b tck2 to tck0 1 0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 196 of 485 rej09b0244-0300 14.3.6 output compare function this function detects matches (compare match) between the content of the tr dgrji (j = either a, b, c, or d) register and the content of the trdi (i = 0 or 1) regi ster. when the content matches, a user-set level is output from the trdioji pin. since this function is enabled with a combination of the trdioji pin and trdgrji register, the output compare function, or any other mode or function, can be selected for each individual pin. figure 14.46 shows a block diagram of output compare function, table 14.25 lists the output compare function specifications. figures 14.47 to 14.58 list the registers associated with output compare function, and figure 14.59 shows an operating example of output compare function. figure 14.46 block diagram of output compare function trdioa0 output control comparator trdgra0 trd0 trdioc0 output control comparator trdgrc0 compare match signal trdiob0 output control comparator trdgrb0 trdiod0 output control comparator trdgrd0 channel 0 trdioa1 output control comparator trdgra1 trd1 trdioc1 output control comparator trdgrc1 trdiob1 output control comparator trdgrb1 trdiod1 output control comparator trdgrd1 channel 1 compare match signal compare match signal compare match signal compare match signal compare match signal compare match signal compare match signal ioc3 = 0 in trdiorc0 register ioc3 = 1 iod3 = 0 in trdiord0 register iod3 = 1 ioc3 = 0 in trdiorc1 register ioc3 = 1 iod3 = 0 in trdiord1 register iod3 = 1 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 197 of 485 rej09b0244-0300 i = 0 or 1, j = either a, b, c, or d table 14.25 output compare function specifications item specification count sources f1, f2, f4, f8, f32, foco40m external signal input to the trdclk pin (valid edge selected by a program) count operations increment count period ? when bits cclr2 to cclr0 in the trdcri register are set to 000b (free- running operation) 1/fk 65536 fk: frequency of count source ? bits cclr1 to cclr0 in the trdcri register are set to 01b or 10b (set the trdi register to 0000h at the compar e match in the trdgrji register). frequency of count source x (n+1) n: setting value in the trdgrji register waveform output timing compare match count start condition 1 (count starts) is writt en to the tstarti bit in the trdstr register. count stop conditions ? 0 (count stops) is written to the tstarti bit in the trdstr register when the cseli bit in the trdstr register is set to 1. the output compare output pin holds output level before the count stops. ? when the cseli bit in the trdstr register is set to 0, the count stops at the compare match in the trdgrai register. the output compare output pin holds le vel after output change by the compare match. interrupt request generation timing ? compare match (content of the trdi re gister matches content of the trdgrji register.) ? trdi register overflows trdioa0 pin function programmable i/ o port, output-compare output, or trdclk (external clock) input trdiob0, trdioc0, trdiod0, trdioa1 to trdiod1 pin functions programmable i/o port or output-compare output (selectable by pin) int0 pin function programmable i/o port, pulse output forced cutoff signal input, or int0 interrupt input read from timer the count value can be read by reading the trdi register. write to timer ? when the sync bit in the trdmr register is set to 0 (channels 0 and 1 operate independently). data can be written to the trdi register. ? when the sync bit in the trdmr register is set to 1 (channels 0 and 1 operate synchronously). data can be written to both the trd0 and trd1 registers by writing to the trdi register. select functions ? output-com pare output pin selected either 1 pin or multiple pins among t rdioai, trdiobi, t rdioci, or trdiodi. ? output level at the compare match selected ?l? output, ?h? output, or output level inversed ? initial output level selected set the level at period from the count start to the compare match. ? timing to set the trdi register to 0000h overflow or compare match in the trdgrai register ? buffer operation (refer to 14.3.2 buffer operation. ) ? synchronous operation (refer to 14.3.3 synchronous operation. ) ? output pin in register s trdgrci and trdgrdi changed the trdgrci register can be used as ou tput control of t he trdioai pin and the trdgrdi register can be used as output control of the trdiobi pin. ? pulse output forced cutoff signal input (refer to 14.3.4 pulse output forced cutoff. ) ? timer rd can be used as the internal timer without output. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 198 of 485 rej09b0244-0300 figure 14.47 registers trdstr and trdmr in output compare function timer rd mode register symbol address after reset trdmr 0138h 00001110b bit symbol bit name function rw note: 1. b3 b2 bfd0 b1 b0 sync b7 b6 b5 b4 rw ? (b3-b1) ? timer rd synchronous bit 0 : registers trd0 and trd1 operate independently 1 : registers trd0 and trd1 operate synchronously nothing is assigned. if necessary, set to 0. when read, the content is 1. rw trdgrd0 register function select bit (1) 0 : general register 1 : buffer register of trdgrb0 register trdgrc1 register function select bit (1) 0 : general register 1 : buffer register of trdgra1 register trdgrc0 register function select bit (1) 0 : general register 1 : buffer register of trdgra0 register bfc0 rw when selecting 0 (change the trdgrji register output pin) by the ioj3 (j = c or d) bit in the trdiorci (i = 0 or 1) register, set the bfji bit in the trdmr register to 0. rw bfc1 bfd1 trdgrd1 register function select bit (1) 0 : general register 1 : buffer register of trdgrb1 register rw timer rd start register (1) symbol address after reset trdstr 0137h 11111100b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. set the trdstr register using the mov instruction (do not use the bit handling instruction). refer to 14.3.12.1 t rdst r re g is t e r of notes on timer rd . trd0 count operation select bit 0 : count stops at the compare match w ith the trdgra0 register 1 : count continues at the compare match w ith the trdgra0 register csel0 rw rw trd1 count operation select bit 0 : count stops at the compare match w ith the trdgra1 register 1 : count continues at the compare match w ith the trdgra1 register ? ? (b7-b4) rw tsta rt1 rw trd1 count start flag (5) 0 : count stops (3) 1 : count starts trd0 count start flag (4) 0 : count stops (2) 1 : count starts nothing is assigned. if necessary, set to 0. when read, the content is 1. b7 b6 b5 b4 b3 b2 csel1 b1 b0 tsta rt0 when the csel0 bit is set to 1, w rite 0 to the tstart0 bit. when the csel1 bit is set to 1, w rite 0 to the tstart1 bit. when the csel0 bit is set to 0 and the compare match signal (trdioa0) is generated, this bit is set to 0 (count stops). when the csel1 bit is set to 0 and the compare match signal (trdioa1) is generated, this bit is set to 0 (count stops). free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 199 of 485 rej09b0244-0300 figure 14.48 trdpmr register in output compare function timer rd pwm mode register symbol address after reset trdpmr 0139h 10001000b bit symbol bit name function rw b3 b2 ? (b3) b1 b0 00 0 pwmb0 b7 b6 b5 b4 000 rw pwmc0 rw pwm mode of trdiob0 select bit set to 0 (timer mode) in the output compare function. pwm mode of trdioc0 select bit set to 0 (timer mode) in the output compare function. ? pwm mode of trdiob1 select bit set to 0 (timer mode) in the output compare function. rw rw nothing is assigned. if necessary, set to 0. when read, the content is 1. set to 0 (timer mode) in the output compare function. pwm mode of trdiod0 select bit set to 0 (timer mode) in the output compare function. pwmd0 rw ? (b7) ? pwmb1 pwmc1 rw nothing is assigned. if necessary, set to 0. when read, the content is 1. pwm mode of trdioc1 select bit set to 0 (timer mode) in the output compare function. pwmd1 pwm mode of trdiod1 select bit free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 200 of 485 rej09b0244-0300 figure 14.49 trdfcr register in output compare function timer rd function control register symbol address after reset trdfcr 013ah 10000000b bit symbol bit name function rw notes: 1. 2. stclk external clock input select bit 0 : external clock input disabled 1 : external clock input enabled rw rw pwm3 rw adtrg adeg a/d trigger edge select bit (in complementary pwm mode) this bit is disabled in the output compare function. rw pwm3 mode s elec t bit (2) set this bit to 1 (other than pwm3 mode) in the output compare function. normal-phase output level select bit (in reset synchronous pwm mode or c omplement ar y pwm mode) this bit is disabled in the output compare function. set bits cmd1 to cmd0 w hen both the tstart0 and tstart1 bits are set to 0 (count stops). ols0 rw rw counter-phase output level select bit (in reset synchronous pwm mode or c omplement ar y pwm mode) this bit is disabled in the output compare function. a/d trigger enable bit (in complementary pwm mode) this bit is disabled in the output compare function. rw cmd1 rw combination mode select bits (1) set to 00b (timer mode, pwm mode, or pwm3 mode) in the output compare function. cmd0 b7 b6 b5 b4 1 when bits cmd1 to cmd0 are set to 00b (timer mode, pwm mode, or pwm3 mode), the setting of the pwm3 bit is enabled. b3 b2 ols1 b1 b0 00 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 201 of 485 rej09b0244-0300 figure 14.50 registers trdoer1 to trdoer2 in output compare function timer rd output master enable register 1 symbol address after reset trdoer1 013bh ffh bit symbol bit name function rw ed1 rw ea 1 eb1 rw trdiod1 output disable bit 0 : enable output 1 : disable output (the trdiod1 pin is used as a programmable i/o port.) trdiob1 output disable bit 0 : enable output 1 : disable output (the trdiob1 pin is used as a programmable i/o port.) ec1 rw trdioa1 output disable bit 0 : enable output 1 : disable output (the trdioa1 pin is used as a programmable i/o port.) rw rw trdiod0 output disable bit 0 : enable output 1 : disable output (the trdiod0 pin is used as a programmable i/o port.) trdioc1 output disable bit 0 : enable output 1 : disable output (the trdioc1 pin is used as a programmable i/o port.) trdioc0 output disable bit 0 : enable output 1 : disable output (the trdioc0 pin is used as a programmable i/o port.) ec0 rw rw eb0 rw trdioa0 output disable bit 0 : enable output 1 : disable output (the trdioa0 pin is used as a programmable i/o port.) trdiob0 output disable bit 0 : enable output 1 : disable output (the trdiob0 pin is used as a programmable i/o port.) 1 b7 b6 b5 b4 b3 b2 ed0 b1 b0 1 ea 0 timer rd output master enable register 2 symbol address after reset trdoer2 013ch 01111111b bit symbol bit name function rw int0 _ ____ of pulse output forced 0 : pulse output forced cutoff input disabled cutoff signal input enabled 1 : pulse output forced cutoff input enabled bit (1) (all bits in the trdoer1 register are set to 1 (disable output) w hen ?l? is applied to the int0 _ ____ pin.) note: 1. ref er to 14.3.4 pulse output forced cutoff. b3 b2 b1 b0 ? b7 b6 b5 b4 ? (b6-b0) nothing is assigned. if necessary, set to 0. when read, the content is 1. rw pto free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 202 of 485 rej09b0244-0300 figure 14.51 trdocr register in output compare function timer rd output control register (1, 2) symbol address after reset trdocr 013dh 00h bit symbol bit name function rw notes: 1. 2. b3 b2 tod0 b1 b0 toa 0 b7 b6 b5 b4 001 rw tob0 rw trdioa0 output level select bit 0 : initial output ?l? 1 : initial output ?h? trdiob0 output level select bit 0 : initial output ?l? 1 : initial output ?h? write to the trdocr register w hen both the tstart0 and tstart1 bits in the trdstr register are set to 0 (count stopped). toc0 rw rw trdioa1 initial output level select bit rw rw trdiod0 initial output level select bit tod1 rw if the pin function is set for w aveform output (refer to tables 14.12 to 14.19 ), the initial output level is output w hen the trdocr r egis ter is s et. toa 1 tob1 rw trdiod1 initial output level select bit 0 : ?l? 1 : ?h? trdiob1 initial output level select bit toc1 trdioc1 initial output level select bit trdioc0 initial output level select bit free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 203 of 485 rej09b0244-0300 figure 14.52 registers t rdcr0 to trdcr1 in output compare function timer rd control register i (i = 0 or 1) symbol address after reset trdcr0 trdcr1 0140h 0150h 00h 00h bit symbol bit name function rw notes: 1. 2. 3. this setting is enabled w hen the sync bit in the trdmr register is set to 1 (trd0 and trd1 operate synchronously). bits ckeg1 to ckeg0 are enabled w hen bits tck2 to tck0 are set to 101b (trdclk input) and the stclk bit in the trdfcr register is set to 1 (external clock input enabled). rw ckeg1 cclr0 rw b7 b6 b5 0 0 0 : disable clear (free-running operation) 0 0 1 : clear by compare match w ith the trdgrai register 0 1 0 : clear by compare match w ith the trdgrbi register 0 1 1 : synchronous clear (clear simultaneously w ith other channel counter) (3) 1 0 0 : do not set. 1 0 1 : clear by compare match w ith the trdgrci register 1 1 0 : clear by compare match w ith the trdgrdi register 1 1 1 : do not set. trdi counter clear select bits this setting is enabled w hen the stclk bit in the trdfcr register is set to 1 (external clock input enabled). b3 b2 ckeg0 b1 b0 tck2 b7 b6 b5 b4 rw rw rw cclr2 cclr1 rw count source select bits b2 b1 b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : trdclk input (1) 1 1 0 : foco40m 1 1 1 : do not set. external clock edge select bits (2) b4 b3 0 0 : count at the rising edge 0 1 : count at the falling edge 1 0 : count at both edges 1 1 : do not set. rw tck1 rw tck0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 204 of 485 rej09b0244-0300 figure 14.53 registers trdiora0 to trdiora1 in output compare function timer rd i/o control register ai (i = 0 or 1) symbol address after reset trdiora 0 trdiora 1 0141h 0151h 10001000b 10001000b bit symbol bit name function rw notes: 1. 2. to select 1 (the trdgrdi register is used as a buffer register of the trdgrbi register) for this bit by the bfdi bit in the trdmr register, set the iod2 bit in the trdiorci register to the same value as the iob2 bit in the trdiorai register. ? iob0 iob1 rw to select 1 (the trdgrci register is used as a buffer register of the trdgrai register) for this bit by the bfci bit in the trdmr register, set the ioc2 bit in the trdiorci register to the same value as the ioa2 bit in the trdiorai register. trdgrb mode select bit (2) set to 0 (output compare) in the output compare function. rw b3 b2 ioa 3 b1 b0 10 ioa 2 0 b7 b6 b5 b4 ? (b7) iob2 rw trdgrb c ontrol bits b5 b4 0 0 : disable pin output by the compare match (trdiobi pin functions as programmable i/o port) 0 1 : ?l? output at compare match w ith the trdgrbi register 1 0 : ?h? output at compare match w ith the trdgrbi 1 1 : toggle output by compare match w ith the trdgrbi register nothing is assigned. if necessary, set to 0. when read, the content is 1. rw rw ioa 1 ioa 0 trdgra control bits b1 b0 0 0 : disable pin output by the compare match (trdioai pin functions as programmable i/o port) 0 1 : ?l? output at compare match w ith the trdgrai register 1 0 : ?h? output at compare match w ith the trdgrai register 1 1 : toggle output by compare match w ith the trdgrai register trdgra mode select bit (1) set to 0 (output compare) in the output compare function. rw input capture input sw itch bit set to 1. rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 205 of 485 rej09b0244-0300 figure 14.54 registers trdiorc0 to trdiorc1 in output compare function timer rd i/o control register ci (i = 0 or 1) symbol address after reset trdiorc0 trdiorc1 0142h 0152h 10001000b 10001000b bit symbol bit name function rw notes: 1. 2. ioc2 to select 1 (the trdgrci register is used as a buffer register of the trdgrai register) for this bit by the bfci bit in the trdmr register, set the ioc2 bit in the trdiorci register to the same value as the ioa2 bit in the trdiorai register. trdgrd mode select bit (2) set to 0 (output compare) in the output compare function. iod3 iod2 rw trdgrd register function select bit 0 : trdiob output register (refer to 14.3.6.1 changing output pins in registers trdgrci (i = 0 or 1) and trdgrdi. ) 1 : general register or buffer register rw b3 b2 ioc3 b1 b0 0 rw trdgrd c ontr ol bits b5 b4 0 0 : disable pin output by compare match 0 1 : ?l? output at compare match w ith the trdgrdi register 1 0 : ?h? output at compare match w ith the trdgrdi register 1 1 : toggle output by compare match w ith the trdgrdi register b7 b6 b5 b4 0 rw rw ioc1 ioc0 trdgrc c ontr ol bits b1 b0 0 0 : disable pin output by compare match 0 1 : ?l? output at compare match w ith the trdgrci register 1 0 : ?h? output at compare match w ith the trdgrci register 1 1 : toggle output by compare match w ith the trdgrci register to select 1 (the trdgrdi register is used as a buffer register of the trdgrbi register) for this bit by the bfdi bit in the trdmr register, set the iod2 bit in the trdiorci register to the same value as the iob2 bit in the trdiorai register. trdgrc mode select bit (1) set to 0 (output compare) in the output compare function. rw trdgrc register function select bit 0 : trdioa output register (refer to 14.3.6.1 changing output pins in registers trdgrci (i = 0 or 1) and trdgrdi. ) 1 : general register or buffer register rw iod0 iod1 rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 206 of 485 rej09b0244-0300 figure 14.55 registers trdsr0 to trdsr1 in output compare function timer rd status register i (i=0 or 1) symbol address after reset trdsr0 trdsr1 0143h 0153h 11100000b 11000000b bit symbol bit name function rw notes: 1. 2. 3. ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. rw ov f udf underflow flag (1) this bit is disabled in the output compare function. rw input capture/compare match flag c [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrci register (3) . nothing is assigned to b5 in the trdsr0 register. when w riting to b5, w rite 0. when reading, the content is 1. imfc rw rw input capture/compare match flag d [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrdi register (3) . overflow flag [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the trdi register overflow s. rw imfb rw input capture/compare match flag a [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrai register. input capture/compare match flag b [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrbi register. imfa b7 b6 b5 b4 including w hen the bfji bit in the trdmr register is set to 1 (trdgrji is used as the buffer register). the w riting results are as follow s: ? this bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. ? this bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) ? this bit remains unchanged if 1 is w ritten to it. b3 b2 imfd b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 207 of 485 rej09b0244-0300 figure 14.56 registers trdier0 to trdier1 in output compare function figure 14.57 registers trd0 to trd1 in output compare function timer rd interrupt enable register i (i = 0 or 1) symbol address after reset trdier0 trdier1 0144h 0154h 11100000b 11100000b bit symbol bit name function rw b3 b2 imied b1 b0 b7 b6 b5 b4 rw imieb rw input capture/compare match interrupt enable bit a 0 : disable interrupt (imia) by the imfa bit 1 : enable interrupt (imia) by the imfa bit input capture/compare match interrupt enable bit b 0 : disable interrupt (imib) by the imfb bit 1 : enable interrupt (imib) by the imfb bit imiea rw input capture/compare match interrupt enable bit d 0 : disable interrupt (imid) by the imfd bit 1 : enable interrupt (imid) by the imfd bit overflow /underflow interrupt enable bit 0 : disable interrupt (ovi) by the ovf bit 1 : enable interrupt (ovi) by the ovf bit rw input capture/compare match interrupt enable bit c 0 : disable interrupt (imic) by the imfc bit 1 : enable interrupt (imic) by the imfc bit imiec rw ov ie ? (b7-b5) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. timer rd counter i (i = 0 or 1) (1) symbol address after reset trd0 trd1 0147h-0146h 0157h-0156h 0000h 0000h setting range rw note: 1. function count a count source. count operation is incremented. when an overflow occurs, the ovf bit in the trdsri register is set to 1. 0000h to ffffh rw access the trdi register in 16-bit units. do not access it in 8-bit units. b0 b7 ( b8) b0 ( b15) b7 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 208 of 485 rej09b0244-0300 figure 14.58 registers trdgrai, trdgrbi, trdg rci, and trdgrdi in output compare function the following registers are disabled in the output compare function: trddf0, trddf1, trdpocr0, and trdpocr1. i = 0 or 1, j = either a, b, c, or d bfji: bit in trdmr register io j3: bit in trdiorci register table 14.26 trdgrji register function in output compare function register setting register function output-compare output pin bfji ioj3 trdgrai ?? general register. write the compare value. trdioai trdgrbi trdiobi trdgrci 0 1 general register. write the compare value. trdioci trdgrdi trdiodi trdgrci 1 1 buffer register. write the next compare value. (refer to 14.3.2 buffer operation .) trdioai trdgrdi trdiobi trdgrci 0 0 trdioai output control. (refer to 14.3.6.1 changing output pins in registers trdgrci (i = 0 or 1) and trdgrdi .) trdioai trdgrdi trdiobi timer rd general register ai, bi, ci and di (i = 0 or 1) (1) symbol address after reset trdgra 0 trdgrb0 trdgrc0 trdgrd0 trdgra 1 trdgrb1 trdgrc1 trdgrd1 0149h-0148h 014bh-014ah 014dh-014ch 014fh-014eh 0159h-0158h 015bh-015ah 015dh-015ch 015fh-015eh ffffh ffffh ffffh ffffh ffffh ffffh ffffh ffffh rw note: 1. ( b8) b0 ( b15) b7 b0 b7 rw function ref er to table 14.26 trdgrji register function in output compare function . access registers trdgrai to trdgrdi in 16-bit units. do not access them in 8-bit units. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 209 of 485 rej09b0244-0300 figure 14.59 operating example of output compare function m n p value in trdi register m+1 m+1 tstarti bit in trdstr register 1 0 trdioai output imfa bit in trdsri register 1 0 n+1 trdiobi output imfb bit in trdsri register 1 0 trdioci output imfc bit in trdsri register 1 0 initial output ?h? ?l? output by compare match set to 0 by a program count source i = 0 or 1 m: value set in trdgrai register n: value set in trdgrbi register p: value set in trdgrci register the above applies under the following conditions: the cseli bit in the trdstr register is set to 1 (the trdi register is not stopped by compare match). bits bfci and bfdi in the trdmr register are set to 0 (registers trdgrci and trdgrdi are not used as buffer registers). bits eai, ebi, and eci in the trdoer1 register are set to 0 (enable the trdioai, trdiobi and trdioci pin outputs). bits cclr2 to cclr0 in the trdcri register ar e set to 001b (set the trdi register to 000h by compare match in the trdgrai regis ter). the iod3 bit in the trdiorci register is set to 1 (t rdgrdi register does not control trdiobi pin output). m n p m+1 m+1 n+1 p+1 count stops count restarts output level held output level held output level held set to 0 by a program set to 0 by a program ?h? output by compare match output inverted by compare match initial output ?l? initial output ?l? bits toai and tobi in the trdocr register is set to 0 (initial output ?l? to compare match), the toci bit is set to 1 (initial output ?h? to compare match). bits ioa2 to ioa0 in the trdiorai register are set to 011b (trdioai output inverted at trdgrai register compare match). bits iob2 to iob0 in the trdiorai register are set to 010b (trdiobi ?h? output at trdgrbi register compare match). bits ioc3 to ioc0 in the trdiorci register are set to 10 01b (trdioci ?l? output at trdgrci register compare match). free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 210 of 485 rej09b0244-0300 14.3.6.1 changing output pi ns in registers trdgrci (i = 0 or 1) and trdgrdi the trdgrci register can be used fo r output control of the trdioai pin, and the trdgrdi register can be used for output control of the tr diobi pin. therefore, each pin outpu t can be controlled as follows: ? trdioai output is controlled by the values in registers trdgrai and trdgrci. ? trdiobi output is controlled by the values in registers trdgrbi and trdgrdi. change output pins in registers trdgrci and trdgrdi as follows: ? select 0 (change trdgrji register output pin) by the ioj3 (j = c or d) bit in the trdiorci register. ? set the bfji bit in the trdmr re gister to 0 (general register). ? set different values in registers trdgrci and tr dgrai. also, set different values in registers trdgrdi and trdgrbi. figure 14.61 shows an operating example when trdgrci register is used for output control of trdioai pin and trdgrdi register is used for output control of trdiobi pin. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 211 of 485 rej09b0244-0300 figure 14.60 changing output pins in registers trdgrci and trdgrdi trdioa0 output control comparator trdgra0 trd0 trdioc0 output control comparator trdgrc0 compare match signal trdiob0 output control comparator trdgrb0 trdiod0 output control comparator trdgrd0 channel 0 trdioa1 output control comparator trdgra1 trd1 trdioc1 output control comparator trdgrc1 trdiob1 output control comparator trdgrb1 trdiod1 output control comparator trdgrd1 channel 1 compare match signal compare match signal compare match signal compare match signal compare match signal compare match signal compare match signal ioc3 = 0 in trdiorc0 register ioc3 = 1 iod3 = 0 in trdiord0 register iod3 = 1 ioc3 = 0 in trdiorc1 register ioc3 = 1 iod3 = 0 in trdiord1 register iod3 = 1 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 212 of 485 rej09b0244-0300 figure 14.61 operating example when trdgrci register is used for output control of trdioai pin and trdgrdi register is used for output control of trdiobi pin set to 0 by a program set to 0 by a program value in trdi register count source trdioai output ffffh trdiobi output m: value set in trdgrai register n: value set in trdgrci register p: value set in trdgrbi register q: value set in trdgrdi register the above applies under the following conditions: the cseli bit in the trdstr register is set to 1 (the trdi register is not stopped by compare match). bits bfci and bfdi in the trdmr register are set to 0 (registers trdgrci and trdgrdi are not used as buffer register). bits eai and ebi in the trdoer1 register are set to 0 (enable trdioai and trdiobi pin outputs). bits cclr2 to cclr0 in the trdcri register are set to 001b (set the trdi register to 0000h by compare match in the trdgrai regi ster). bits toai and tobi in the trdocr register are set to 0 (initial output ?l? to compare match). bits ioa2 to ioa0 in the trdiorai register are set to 011b (trdioai output inverted at trdgrai register compare match). bits iob2 to iob0 in the trdiorai register are set to 011b (trdiobi output inverted at trdgrbi register compare match). bits ioc3 to ioc0 in the trdiorci register are set to 0011b (trdioai output inverted at trdgrci register compare match). bits iod3 to iod0 in the trdiorci register are set to 0011b (trdiobi output inverted at trdgrdi register compare match). i = 0 or 1 m n p m+1 n+1 q 0000h m-n p+1 p-q q+1 imfa bit in trdsri register 1 0 imfc bit in trdsri register 1 0 set to 0 by a program output inverted by compare match initial output ?l? imfb bit in trdsri register 1 0 imfd bit in trdsri register 1 0 initial output ?l? set to 0 by a program output inverted by compare match free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 213 of 485 rej09b0244-0300 14.3.7 pwm mode in pwm mode, a pwm waveform is output. up to 3 pwm waveforms with the same period can be output by 1 channel. also, up to 6 pwm waveforms with the same period can be output by synchronizing channels 0 and 1. since this mode functions by a combination of the trdioji (i = 0 or 1, j = b, c, or d) pin and trdgrji register, the pwm mode, or any other mode or function, can be selected for each indi vidual pin. (however, since the trdgrai register is used when using any pin for pwm mode, the trdgrai register cannot be used for other modes.) figure 14.62 shows a block diagram of pwm mode, and table 14.27 lists the pwm mode specifications. figures 14.63 to 14.72 show the registers associated with pwm mode, and figures 14.73 and 14.74 show operating examples of pwm mode. figure 14.62 block diagram of pwm mode trdiobi output control trdgrai trdi compare match signal trdgrbi trdioci trdgrci trdgrdi trdiodi (note 1) (note 2) i = 0 or 1 notes: 1. when the bfci bit in the trdmr register is set to 1 (the trdgrci register is used as the buffer register of the trdgrai register). 2. when the bfdi bit in the trdmr register is set to 1 (the trdgrdi register is used as the buffer register of the trdgrbi register). compare match signal compare match signal compare match signal comparator comparator comparator comparator free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 214 of 485 rej09b0244-0300 i = 0 or 1 j = either b, c, or d h = either a, b, c, or d table 14.27 pwm mode specifications item specification count sources f1, f2, f4, f8, f32, foco40m external signal input to the trdclk pin (valid edge selected by a program) count operations increment pwm waveform pwm period: 1/fk x (m+1) active level width : 1/fk x (m-n) inactive level width: 1/fk x (n+1) fk: frequency of count source m: value set in the trdgrai register n: value set in t he trdgrji register count start condition 1 (count starts) is writte n to the tstarti bit in the trdstr register. count stop conditions ? 0 (count stops) is writte n to the tstarti bit in the trdstr register when the cseli bit in the trdstr register is set to 1. the pwm output pin holds output level before the count stops. ? when the cseli bit in the trdstr register is set to 0, the count stops at the compare match in the trdgrai register. the pwm output pin holds level after output change by compare match. interrupt request generation timing ? compare match (the content of the trdi register matches content of the trdgrhi register.) ? trdi register overflows trdioa0 pin function programmable i/o port or trdclk (external clock) input trdioa1 pin function programmable i/o port trdiob0, trdioc0, trdiod0, trdiob1, trdioc1, trdiod1 pin functions programmable i/o port or pulse output (selectable by pin) int0 pin function programmable i/o port, pulse outp ut forced cutoff signal input, or int0 interrupt input read from timer the count value can be read by reading the trdi register. write to timer the value can be written to the trdi register. select functions ? 1 to 3 pwm output pins selected per 1 channel either 1 pin or multiple pins of the trdiobi, trdioci or trdiodi pin. ? the active level selected by pin. ? initial output level selected by pin. ? synchronous operation (refer to 14.3.3 synchronous operation .) ? buffer operation (refer to 14.3.2 buffer operation .) ? pulse output forced cutoff signal input (refer to 14.3.4 pulse output forced cutoff .) m+1 n+1 m-n (when ?l? is selected as the active level) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 215 of 485 rej09b0244-0300 figure 14.63 registers trdstr and trdmr in pwm mode timer rd mode register symbol address after reset trdmr 0138h 00001110b bit symbol bit name function rw b3 b2 bfd0 b1 b0 sync b7 b6 b5 b4 rw ? (b3-b1) ? timer rd synchronous bit 0 : registers trd0 and trd1 operate independently 1 : registers trd0 and trd1 operate synchronously nothing is assigned. if necessary, set to 0. when read, the content is 1. trdgrc0 register function select bit 0 : general register 1 : buffer register of trdgra0 register bfc0 rw rw trdgrd0 register function select bit 0 : general register 1 : buffer register of trdgrb0 register trdgrc1 register function select bit 0 : general register 1 : buffer register of trdgra1 register rw rw bfc1 bfd1 trdgrd1 register function select bit 0 : general register 1 : buffer register of trdgrb1 register timer rd start register (1) symbol address after reset trdstr 0137h 11111100b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. set the trdstr register using the mov instruction (do not use the bit handling instruction). refer to 14.3.12.1 t rdst r re g is t e r of no t e s o n t im e r rd . trd0 count operation select bit 0 : count stops at compare match w ith the trdgra0 register 1 : count continues at compare match w ith the trdgra0 register csel0 rw rw trd1 count operation select bit 0 : count stops at compare match w ith the trdgra1 register 1 : count continues at compare match w ith the trdgra1 register ? ? (b7-b4) rw tsta rt1 rw trd1 count start flag (5) 0 : count stops (3) 1 : count starts trd0 count start flag (4) 0 : count stops (2) 1 : count starts nothing is assigned. if necessary, set to 0. when read, the content is 1. b7 b6 b5 b4 b3 b2 csel1 b1 b0 tsta rt0 when the csel0 bit is set to 1, w rite 0 to the tstart0 bit. when the csel1 bit is set to 1, w rite 0 to the tstart1 bit. when the csel0 bit is set to 0 and the compare match signal (trdioa0) is generated, this bit is set to 0 (count stops). when the csel1 bit is set to 0 and the compare match signal (trdioa1) is generated, this bit is set to 0 (count stops). free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 216 of 485 rej09b0244-0300 figure 14.64 trdpmr register in pwm mode timer rd pwm mode register symbol address after reset trdpmr 0139h 10001000b bit symbol bit name function rw b3 b2 ? (b3) b1 b0 pwmb0 b7 b6 b5 b4 rw pwmc0 rw pwm mode of trdiob0 select bit 0 : timer mode 1 : pwm mode pwm mode of trdioc0 select bit 0 : timer mode 1 : pwm mode pwm mode of trdiod0 select bit 0 : timer mode 1 : pwm mode pwmd0 rw ? pwm mode of trdiob1 select bit 0 : timer mode 1 : pwm mode rw rw nothing is assigned. if necessary, set to 0. when read, the content is 1. 0 : timer mode 1 : pwm mode ? (b7) ? pwmb1 pwmc1 rw nothing is assigned. if necessary, set to 0. when read, the content is 1. pwm mode of trdioc1 select bit 0 : timer mode 1 : pwm mode pwmd1 pwm mode of trdiod1 select bit free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 217 of 485 rej09b0244-0300 figure 14.65 trdfcr register in pwm mode timer rd function control register symbol address after reset trdfcr 013ah 10000000b bit symbol bit name function rw notes: 1. 2. when bits cmd1 to cmd0 are set to 00b (timer mode, pwm mode, or pwm3 mode), the setting of the pwm3 bit is enabled. stclk external clock input select bit 0 : external clock input disabled 1 : external clock input enabled rw rw pwm3 rw adtrg adeg a/d trigger edge select bit (in complementary pwm mode) this bit is disabled in pwm mode. rw pwm3 mode select bit (2) set this bit to 1 (other than pwm3 mode) in pwm mode. normal-phase output level select bit (in reset synchronous pwm mode or c omplement ar y pwm mode) this bit is disabled in pwm mode. set bits cmd1 to cmd0 w hen both the tstart0 and tstart1 bits are set to 0 (count stops). ols0 rw rw counter-phase output level select bit (in reset synchronous pwm mode or c omplement ar y pwm mode) this bit is disabled in pwm mode. a/d trigger enable bit (in complementary pwm mode) this bit is disabled in pwm mode. rw cmd1 rw combination mode select bits (1) set to 00b (timer mode, pwm mode, or pwm3 mode) in pwm mode. cmd0 b7 b6 b5 b4 1 b3 b2 ols1 b1 b0 00 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 218 of 485 rej09b0244-0300 figure 14.66 registers trdoer1 to trdoer2 in pwm mode timer rd output master enable register 1 symbol address after reset trdoer1 013bh ffh bit symbol bit name function rw ed1 rw ea 1 eb1 rw trdiod1 output disable bit 0 : enable output 1 : disable output (the trdiod1 pin is used as a programmable i/o port.) trdiob1 output disable bit 0 : enable output 1 : disable output (the trdiob1 pin is used as a programmable i/o port.) ec1 rw trdioa1 output disable bit 0 : enable output 1 : disable output (the trdioa1 pin is used as a programmable i/o port.) rw rw trdiod0 output disable bit 0 : enable output 1 : disable output (the trdiod0 pin is used as a programmable i/o port.) trdioc1 output disable bit 0 : enable output 1 : disable output (the trdioc1 pin is used as a programmable i/o port.) trdioc0 output disable bit 0 : enable output 1 : disable output (the trdioc0 pin is used as a programmable i/o port.) ec0 rw rw eb0 rw trdioa0 output disable bit 0 : enable output 1 : disable output (the trdioa0 pin is used as a programmable i/o port.) trdiob0 output disable bit 0 : enable output 1 : disable output (the trdiob0 pin is used as a programmable i/o port.) 1 b7 b6 b5 b4 b3 b2 ed0 b1 b0 1 ea 0 timer rd output master enable register 2 symbol address after reset trdoer2 013ch 01111111b bit symbol bit name function rw int0 _ ____ of pulse output forced 0 : pulse output forced cutoff input disabled 1 : pulse output forced cutoff input enabled (all bits in the trdoer1 register are set to 1 (disable output) w hen ?l? is applied to the int0 _ ____ pin.) note: 1. ref er to 14.3.4 pulse output forced cutoff. b3 b2 b1 b0 ? b7 b6 b5 b4 ? (b6-b0) nothing is assigned. if necessary, set to 0. when read, the content is 1. rw pto cutoff signal input enabled bit (1) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 219 of 485 rej09b0244-0300 figure 14.67 registers trdocr and trdcr0 to trdcr1 in pwm mode timer rd output control register (1) symbol address after reset trdocr 013dh 00h bit symbol bit name function rw notes: 1. 2. if the pin function is set for w aveform output (refer to tables 14.13 to 14.15 and tables 14.17 to 14.19 ), the initial output level is output w hen the trdocr register is set. b3 b2 tod0 b1 b0 0 toa 0 b7 b6 b5 b4 0 trdiod0 initial output level select bit (2) tod1 rw rw tob0 rw trdioa0 output level select bit set this bit to 0 (enable output) in pwm mo d e . trdiob0 output level select bit (2) trdioc0 initial output level select bit (2) 0 : initial output is inactive level 1 : initial output is active level set this bit to 0 (enable output) in pwm mo d e . write to the trdocr register w hen both the tstart0 and tstart1 bits in the trdstr register are set to 0 (count stops). toc0 rw rw trdioa 1 initial output level select bit rw rw 0 : inactive level 1 : active level toa 1 tob1 rw trdiod1 initial output level select bit (2) trdiob1 initial output level select bit (2) toc1 trdioc1 initial output level select bit (2) timer rd control register i (i = 0 or 1) symbol address after reset trdcr0 trdcr1 0140h 0150h 00h 00h bit symbol bit name function rw notes: 1. 2. bits ckeg1 to ckeg0 are enabled w hen bits tck2 to tck0 are set to 101b (trdclk input) and the stclk bit in the trdfcr register is set to 1 (external clock input enabled). rw ckeg1 cclr0 rw set to 001b (the trdi register cleared at compare match w ith trdgrai register) in pwm mo d e . trdi counter clear select bits this setting is enabled w hen the stclk bit in the trdfcr register is set to 1 (external clock input enabled). b3 b2 ckeg0 b1 b0 tck2 001 b7 b6 b5 b4 rw rw rw cclr2 cclr1 rw count source select bits b2 b1 b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : trdclk input (1) 1 1 0 : foco40m 1 1 1 : do not set. external clock edge select bits (2) b4 b3 0 0 : count at the rising edge 0 1 : count at the f alling edge 1 0 : count at both edges 1 1 : do not set. rw tck1 rw tck0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 220 of 485 rej09b0244-0300 figure 14.68 registers trdsr0 to trdsr1 in pwm mode timer rd status register i (i=0 or 1) symbol address after reset trdsr0 trdsr1 0143h 0153h 11100000b 11000000b bit symbol bit name function rw notes: 1. 2. 3. ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. rw ov f udf underflow flag (1) this bit is disabled in pwm mode. rw input capture/compare match flag c [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrci register (3) . nothing is assigned to b5 in the trdsr0 register. when w riting to b5, w rite 0. when reading, the content is 1. imfc rw rw input capture/compare match flag d [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrdi register (3) . overflow flag [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the trdi register overflow s. rw imfb rw input capture/compare match flag a [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrai register. input capture/compare match flag b [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrbi register. imfa b7 b6 b5 b4 including w hen the bfji bit in the trdmr register is set to 1 (trdgrji is used as the buffer register). the w riting results are as follow s: ? this bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. ? this bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) ? this bit remains unchanged if 1 is w ritten. b3 b2 imfd b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 221 of 485 rej09b0244-0300 figure 14.69 registers trdier0 to trdier1 in pwm mode timer rd interrupt enable register i (i = 0 or 1) symbol address after reset trdier0 trdier1 0144h 0154h 11100000b 11100000b bit symbol bit name function rw ov ie ? (b7-b5) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. rw input capture/compare match interrupt enable bit d 0 : disable interrupt (imid) by the imfd bit 1 : enable interrupt (imid) by the imfd bit overflow /underflow interrupt enable bit 0 : disable interrupt (ovi) by the ovf bit 1 : enable interrupt (ovi) by the ovf bit rw input capture/compare match interrupt enable bit c 0 : disable interrupt (imic) by the imfc bit 1 : enable interrupt (imic) by the imfc bit imiec rw rw imieb rw input capture/compare match interrupt enable bit a 0 : disable interrupt (imia) by the imfa bit 1 : enable interrupt (imia) by the imfa bit input capture/compare match interrupt enable bit b 0 : disable interrupt (imib) by the imfb bit 1 : enable interrupt (imib) by the imfb bit imiea b7 b6 b5 b4 b3 b2 imied b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 222 of 485 rej09b0244-0300 figure 14.70 registers trdpocr0 to trdpocr1 in pwm mode figure 14.71 registers trd0 to trd1 in pwm mode timer rd pwm mode output level control register i (i = 0 or 1) symbol address after reset trdpocr0 trdpocr1 0145h 0155h 11111000b 11111000b bit symbol bit name function rw ? nothing is assigned. if necessary, set to 0. when read, the content is 1. pwm mode output level control bit d 0 : ?l? active trdiodi output level is selected 1 : ?h? active trdiodi output level is selected rw rw pol c rw pwm mode output level control bit b 0 : ?l? active trdiobi output level is selected 1 : ?h? active trdiobi output level is selected pwm mode output level control bit c 0 : ?l? active trdioci output level is selected 1 : ?h? active trdioci output level is selected pol b b7 b6 b5 b4 b3 b2 ? (b7-b3) b1 b0 pol d timer rd counter i (i = 0 or 1) (1) symbol address after reset trd0 trd1 0147h-0146h 0157h-0156h 0000h 0000h setting range rw note: 1. ( b8) b0 ( b15) b7 access the trdi register in 16-bit units. do not access it in 8-bit units. b0 b7 function count a count source. count operation is incremented. when an overflow occurs, the ovf bit in the trdsri register is set to 1. 0000h to ffffh rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 223 of 485 rej09b0244-0300 figure 14.72 registers t rdgrai, trdgrbi, tr dgrci, and trdgrdi in pwm mode the following registers are disabled in the pwm mode: trddf0, trddf1, trdiora0, trdiorc0, trdiora1, and trdiorc1. i = 0 or 1 bfci, bfdi: bits in trdmr register table 14.28 trdgrji register functions in pwm mode register setting register function pwm output pin trdgrai ? general register. set the pwm period ? trdgrbi ? general register. set the changin g point of pwm output trdiobi trdgrci bfci = 0 general register. set th e changing point of pwm output trdioci trdgrdi bfdi = 0 trdiodi trdgrci bfci = 1 buffer register. set the next pwm period. (refer to 14.3.2 buffer operation .) ? trdgrdi bfdi = 1 buffer register. set the changing point of the next pwm output. (refer to 14.3.2 buffer operation .) trdiobi timer rd general registers ai, bi, ci, and di (i = 0 or 1) (1) symbol address after reset trdgra 0 trdgrb0 trdgrc0 trdgrd0 trdgra 1 trdgrb1 trdgrc1 trdgrd1 0149h-0148h 014bh-014ah 014dh-014ch 014fh-014eh 0159h-0158h 015bh-015ah 015dh-015ch 015fh-015eh ffffh ffffh ffffh ffffh ffffh ffffh ffffh ffffh rw note: 1. ( b8) b0 ( b15) b7 b0 b7 rw function ref er to table 14.28 trdgrji register functions in pwm mode. access registers trdgrai to trdgrdi in 16-bit units. do not access them in 8-bit units. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 224 of 485 rej09b0244-0300 figure 14.73 operating example of pwm mode m n p value in trdi register count source m+1 n+1 trdioci output q m-n p+1 m-p m-q q+1 trdiodi output m: value set in trdgrai register n: value set in trdgrbi register p: value set in trdgrci register q: value set in trdgrdi register inactive level ?l? active level ?h? inactive level ?h? active level ?l? initial output ?h? to compare match initial output ?l? to compare match set to 0 by a program set to 0 by a program set to 0 by a program trdiobi output imfa bit in trdsri register 1 0 imfb bit in trdsri register 1 0 imfc bit in trdsri register 1 0 imfd bit in trdsri register 1 0 i = 0 or 1 set to 0 by a program the above applies under the following conditions: bits bfci and bfdi in the trdmr register are set to 0 (registers trdgrci and trdgrdi are not used as buffer registers). bits ebi, eci and edi in the trdoer1 register are set to 0 (enable trdiobi, trdioci and trdiodi pin outputs). bits tobi and toci in the trdocr register are set to 0 (i nactive level), the todi bit is set to 1 (active level). the polb bit in the trdpocri register is set to 1 (active level ?h?), bits polc and pold are set to 0 (active level ?l?). initial output ?l? to compare match free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 225 of 485 rej09b0244-0300 figure 14.74 operating example of pwm mode (duty 0%, duty 100%) m p q value in trdi register n m: value set in trdgrai register set to 0 by a program rewrite by a program 0000h q duty 0% trdgrbi register imfa bit in trdsri register 1 0 imfb bit in trdsri register 1 0 tstarti bit in trdstr register trdiobi output p (p>m) n since no compare match in the trdgrbi register is generated, ?l? is not applied to the trdiobi output 1 0 m p value in trdi register n 0000h trdgrbi register imfa bit in trdsri register 1 0 imfb bit in trdsri register 1 0 tstarti bit in trdstr register trdiobi output p n 1 0 ?l? is applied to trdiobi output at compare match with the trdgrbi register with no change. m i = 0 or 1 the above applies under the following conditions: the ebi bit in the trdoer1 register is set to 0 (enable trdiobi output). the polb bit in the trdpocri register is set to 0 (active level ?l?). rewrite by a program set to 0 by a program set to 0 by a program when compare matches with registers trdgrai and trdgrbi are generated simultaneously, the compare match with the trdgrbi register has priority. ?l? is applied to the trdiobi output without any change. duty 100% set to 0 by a program free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 226 of 485 rej09b0244-0300 14.3.8 reset synchronous pwm mode in this mode, 3 normal-phases and 3 counter-phases of the pwm waveform are output with the same period (three-phase, sawtooth wave modulation, and no dead time). figure 14.75 shows a block diagram of reset sync hronous pwm mode, and table 14.29 lists the reset synchronous pwm mode specifications. figures 14.76 to 14.83 show the register s associated with reset synchronous pwm mode and figure 14.84 shows an op erating example of reset synchronous pwm mode. refer to figure 14.74 operating example of pwm mode (duty 0%, duty 100%) for an operating example of pwm mode with duty 0% and duty 100%. figure 14.75 block diagram of reset synchronous pwm mode period trdioc0 trdiob0 trdiod0 trdioa1 trdioc1 trdiob1 trdiod1 pwm1 pwm2 pwm3 waveform control trdgrb0 register trdgra1 register trdgrb1 register normal-phase counter-phase trdgra0 register trdgrd0 register trdgrc1 register trdgrd1 register trdgrc0 register buffer (1) normal-phase counter-phase normal-phase counter-phase note: 1. when bits bfc0, bfd0, bfc1, and bfd1 in the trdmr register are set to 1 (buffer register). free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 227 of 485 rej09b0244-0300 j = either a, b, c, or d table 14.29 reset synchronous pwm mode specifications item specification count sources f1, f2, f4, f8, f32, foco40m external signal input to the trdclk pin (valid edge selected by a program) count operations the trd0 register is incremented (the trd1 register is not used). pwm waveform pwm period : 1/fk (m+1) active level width of normal-phase : 1/fk (m-n) active level width of coun ter-phase: 1/fk (n+1) fk: frequency of count source m: value set in the trdgra0 register n: value set in the trdgrb0 register (pwm1 output), value set in the trdgra1 register (pwm2 output), value set in the trdgrb1 register (pwm3 output) count start condition 1 (count starts) is writt en to the tstart0 bit in the trdstr register. count stop conditions ? 0 (count stops) is writt en to the tstart0 bit in the trdstr register when the csel0 bit in the trdstr register is set to 1. the pwm output pin holds output level before the count stops ? when the csel0 bit in the trdstr register is set to 0, the count stops at the compare match in the trdgra0 register. the pwm output pin holds level af ter output change at compare match. interrupt request generation timing ? compare match (the content of th e trd0 register matches content of registers trdgrj0, t rdgra1, and trdgrb1). ? the trd0 register overflows trdioa0 pin function programmable i/o po rt or trdclk (external clock) input trdiob0 pin function pwm1 output normal-phase output trdiod0 pin function pwm1 ou tput counter-phase output trdioa1 pin function pwm2 output normal-phase output trdioc1 pin function pwm2 ou tput counter-phase output trdiob1 pin function pwm3 output normal-phase output trdiod1 pin function pwm3 ou tput counter-phase output trdioc0 pin function output inverted every pwm period int0 pin function programmable i/o port, pulse output forced cutoff signal input, or int0 interrupt input read from timer the count value can be read by reading the trd0 register. write to timer the value can be written to the trd0 register. select functions ? the active level of normal-phase and counter-phase and initial output level selected individually. ? buffer operation (refer to 14.3.2 buffer operation .) ? pulse output forced cutoff signal input (refer to 14.3.4 pulse output forced cutoff .) m+1 normal-phase n+1 (when ?l? is selected as the active level) counter-phase m-n free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 228 of 485 rej09b0244-0300 figure 14.76 registers trdstr and trdmr in reset synchronous pwm mode timer rd mode register symbol address after reset trdmr 0138h 00001110b bit symbol bit name function rw rw bfc1 bfd1 trdgrd1 register function select bit 0 : general register 1 : buffer register of trdgrb1 register trdgrc0 register function select bit 0 : general register 1 : buffer register of trdgra0 register bfc0 rw rw trdgrd0 register function select bit 0 : general register 1 : buffer register of trdgrb0 register trdgrc1 register function select bit 0 : general register 1 : buffer register of trdgra1 register rw rw ? (b3-b1) ? timer rd synchronous bit set this bit to 0 (registers trd0 and trd1 operate independently) in reset synchronous pwm mode. nothing is assigned. if necessary, set to 0. when read, the content is 1. b7 b6 b5 b4 b3 b2 bfd0 b1 b0 0 sync timer rd start register (1) symbol address after reset trdstr 0137h 11111100b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. when the csel0 bit is set to 1, w rite 0 to the tstart0 bit. when the csel1 bit is set to 1, w rite 0 to the tstart1 bit. when the csel0 bit is set to 0 and the compare match signal (trdioa0) is generated, this bit is set to 0 (count stops). when the csel1 bit is set to 0 and the compare match signal (trdioa1) is generated, this bit is set to 0 (count stops). b3 b2 csel1 b1 b0 tsta rt0 b7 b6 b5 b4 rw tsta rt1 rw trd1 count start flag (5) 0 : count stops (3) 1 : count starts trd0 count start flag (4) 0 : count stops (2) 1 : count starts trd0 count operation select bit 0 : count stops at compare match w ith the trdgra0 register 1 : count continues at compare match w ith the trdgra0 register csel0 rw ? (b7-b4) nothing is assigned. if necessary, set to 0. when read, the content is 1. set the trdstr register using the mov instruction (do not use the bit handling instruction). refer to 14.3.12.1 t rdst r re g is t e r of no t e s o n t im e r rd . rw trd1 count operation select bit 0 : count stops at compare match w ith the trdgra1 register 1 : count continues at compare match w ith the trdgra1 register ? free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 229 of 485 rej09b0244-0300 figure 14.77 trdfcr register in reset synchronous pwm mode timer rd function control register symbol address after reset trdfcr 013ah 10000000b bit symbol bit name function rw notes: 1. 2. 3. when bits cmd1 to cmd0 are set to 00b (timer mode, pwm mode, or pwm3 mode), the setting of the pwm3 bit is enabled. b3 b2 ols1 b1 b0 01 b7 b6 b5 b4 rw cmd1 rw combination mode select bits (1, 2) set to 01b (reset synchronous pwm mode) in reset synchronous pwm mode. cmd0 normal-phase output level select bit (in reset synchronous pwm mode or c omplement ar y pwm mode) 0 : initial output ?h? active level ?l? 1 : initial output ?l? active level ?h? set bits cmd1 to cmd0 w hen both the tstart0 and tstart1 bits are set to 0 (count stops). ols0 rw rw counter-phase output level select bit (in reset synchronous pwm mode or c omplement ar y pwm mode) 0 : initial output ?h? active level ?l? 1 : initial output ?l? active level ?h? a/d trigger enable bit (in complementary pwm mode) this bit is disabled in reset synchronous pwm mode. rw pwm3 rw adtrg adeg a/d trigger edge select bit (in complementary pwm mode) this bit is disabled in reset synchronous pwm mode. rw pwm3 mode select bit (3) this bit is disabled in reset synchronous pwm mode. when bits cmd1 to cmd0 are set to 01b, 10b, or 11b, the mcu enters reset synchronous pwm mode or complementary pwm mode in spite of the setting of the trdpmr register. stclk external clock input select bit 0 : external clock input disabled 1 : external clock input enabled rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 230 of 485 rej09b0244-0300 figure 14.78 registers trdoer1 to trdoer2 in reset synchronous pwm mode timer rd output master enable register 1 symbol address after reset trdoer1 013bh ffh bit symbol bit name function rw b3 b2 ed0 b1 b0 1 ea 0 b7 b6 b5 b4 rw eb0 rw trdioa0 output disable bit set this bit to 1 (the trdioa0 pin is used as a programmable i/o port) in reset synchronous pwm mode. trdiob0 output disable bit 0 : enable output 1 : disable output (the trdiob0 pin is used as a programmable i/o port.) trdioc0 output disable bit 0 : enable output 1 : disable output (the trdioc0 pin is used as a programmable i/o port.) ec0 rw rw trdioa1 output disable bit 0 : enable output 1 : disable output (the trdioa1 pin is used as a programmable i/o port.) rw rw trdiod0 output disable bit 0 : enable output 1 : disable output (the trdiod0 pin is used as a programmable i/o port.) trdioc1 output disable bit 0 : enable output 1 : disable output (the trdioc1 pin is used as a programmable i/o port.) ed1 rw ea 1 eb1 rw trdiod1 output disable bit 0 : enable output 1 : disable output (the trdiod1 pin is used as a programmable i/o port.) trdiob1 output disable bit 0 : enable output 1 : disable output (the trdiob1 pin is used as a programmable i/o port.) ec1 timer rd output master enable register 2 symbol address after reset trdoer2 013ch 01111111b bit symbol bit name function rw int0 _ ____ of pulse output forced 0 : pulse output forced cutoff input disabled 1 : pulse output forced cutoff input enabled (all bits in the trdoer1 register are set to 1 (disable output) w hen ?l? is applied to the int0 _ ____ pin.) note: 1. b3 b2 b1 b0 b7 b6 b5 b4 ref er to 14.3.4 pulse output forced cutoff. ? ? (b6-b0) nothing is assigned. if necessary, set to 0. when read, the content is 1. rw pto cutoff signal input enabled bit (1) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 231 of 485 rej09b0244-0300 figure 14.79 trdcr0 register in reset synchronous pwm mode timer rd control register 0 (3) symbol address after reset trdcr0 0140h 00h bit symbol bit name function rw notes: 1. 2. 3. the trdcr1 register is not used in reset synchronous pwm mode. bits ckeg1 to ckeg0 are enabled w hen bits tck2 to tck0 are set to 101b (trdclk input) and the stclk bit in the trdfcr register is set to 1 (external clock input enabled). rw ckeg1 cclr0 rw set to 001b (trd0 register cleared at compare match w ith trdgra0 register) in reset synchronous pwm mode. trd0 counter clear select bits this setting is enabled w hen the stclk bit in the trdfcr register is set to 1 (external clock input enabled). b3 b2 ckeg0 b1 b0 tck2 001 b7 b6 b5 b4 rw rw rw cclr2 cclr1 rw count source select bits b2 b1b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : trdclk input (1) 1 1 0 : foco40m 1 1 1 : do not set. external clock edge select bits (2) b4 b3 0 0 : count at the rising edge 0 1 : count at the fa lling edge 1 0 : count at both edges 1 1 : do not set. rw tck1 rw tck0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 232 of 485 rej09b0244-0300 figure 14.80 registers trdsr0 to trdsr1 in reset synchronous pwm mode timer rd status register i (i = 0 or 1) symbol address after reset trdsr0 trdsr1 0143h 0153h 11100000b 11000000b bit symbol bit name function rw notes: 1. 2. 3. including w hen the bfji bit in the trdmr register is set to 1 (trdgrji is used as the buffer register). the w riting results are as follow s: ? this bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. ? this bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0). ? this bit remains unchanged if 1 is w ritten to it. b3 b2 imfd b1 b0 b7 b6 b5 b4 rw imfb rw input capture/compare match flag a [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrai register. input capture/compare match flag b [source for setting this bit to 0?] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrbi register. imfa input capture/compare match flag c [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrci register (3) . nothing is assigned to b5 in the trdsr0 register. when w riting to b5, w rite 0. when reading, the content is 1. imfc rw rw input capture/compare match flag d [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrdi register (3) . overflow flag [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the trdi register overflow s. ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. rw ov f udf underflow flag (1) this bit is disabled in reset synchronous pwm mode. rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 233 of 485 rej09b0244-0300 figure 14.81 registers trdier0 to trdier1 in reset synchronous pwm mode figure 14.82 trd0 registrar in reset synchronous pwm mode timer rd interrupt enable register i (i = 0 or 1) symbol address after reset trdier0 trdier1 0144h 0154h 11100000b 11100000b bit symbol bit name function rw b3 b2 imied b1 b0 b7 b6 b5 b4 rw imieb rw input capture/compare match interrupt enable bit a 0 : disable interrupt (imia) by the imfa bit 1 : enable interrupt (imia) by the imfa bit input capture/compare match interrupt enable bit b 0 : disable interrupt (imib) by the imfb bit 1 : enable interrupt (imib) by the imfb bit imiea rw input capture/compare match interrupt enable bit d 0 : disable interrupt (imid) by the imfd bit 1 : enable interrupt (imid) by the imfd bit overflow /underflow interrupt enable bit 0 : disable interrupt (ovi) by the ovf bit 1 : enable interrupt (ovi) by the ovf bit rw input capture/compare match interrupt enable bit c 0 : disable interrupt (imic) by the imfc bit 1 : enable interrupt (imic) by the imfc bit imiec rw ov ie ? (b7-b5) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. timer rd counter 0 (1, 2) symbol address after reset trd0 0147h-0146h 0000h setting range rw notes: 1. 2. the trd1 register is not used in reset synchronous pwm mode. function count a count source. count operation is incremented. when an overflow occurs, the ovf bit in the trdsr0 register is set to 1. 0000h to ffffh rw access the trd0 register in 16-bit units. do not access it in 8-bit units. b0 b7 ( b8) b0 ( b15) b7 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 234 of 485 rej09b0244-0300 figure 14.83 registers trdgrai, trdgrbi, trdgrci, and trdgrdi in r eset synchronous pwm mode the following registers are disabled in the re set synchronous pwm mode : trdpmr, trdocr, trddf0, trddf1, trdiora0, trdiorc0, trdpocr0, trdiora1, trdiorc1, and trdpocr1. bfc0, bfd0, bfc1, bfd1: bits in trdmr register table 14.30 trdgrji register functions in reset synchronous pwm mode register setting register function pwm output pin trdgra0 ? general register. set the pwm period. (output inverted every pwm period and trdioc0 pin) trdgrb0 ? general register. set the changing point of pwm1 output. trdiob0 trdiod0 trdgrc0 bfc0 = 0 (these registers are not used in reset synchronous pwm mode.) ? trdgrd0 bfd0 = 0 trdgra1 ? general register. set the changing point of pwm2 output. trdioa1 trdioc1 trdgrb1 ? general register. set the changing point of pwm3 output. trdiob1 trdiod1 trdgrc1 bfc1 = 0 (these points are not used in reset synchronous pwm mode.) ? trdgrd1 bfd1 = 0 trdgrc0 bfc0 = 1 buffer register. set the next pwm period. (refer to 14.3.2 buffer operation. ) (output inversed every pwm period and trdioc0 pin) trdgrd0 bfd0 = 1 buffer register. set the changing point of the next pwm1 output. (refer to 14.3.2 buffer operation .) trdiob0 trdiod0 trdgrc1 bfc1 = 1 buffer register. set the changing point of the next pwm2 output. (refer to 14.3.2 buffer operation .) trdioa1 trdioc1 trdgrd1 bfd1 = 1 buffer register. set the changing point of the next pwm3 output. (refer to 14.3.2 buffer operation .) trdiob1 trdiod1 timer rd general registers ai, bi, ci, and di (i = 0 or 1) (1) symbol address after reset trdgra 0 trdgrb0 trdgrc0 trdgrd0 trdgra 1 trdgrb1 trdgrc1 trdgrd1 0149h-0148h 014bh-014ah 014dh-014ch 014fh-014eh 0159h-0158h 015bh-015ah 015dh-015ch 015fh-015eh ffffh ffffh ffffh ffffh ffffh ffffh ffffh ffffh rw note: 1. ( b8) b0 ( b15) b7 b0 b7 rw function ref er to table 14.30 trdgrji register functions in reset synchronous pwm mode. access registers trdgrai to trdgrdi in 16-bit units. do not access them in 8-bit units. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 235 of 485 rej09b0244-0300 figure 14.84 operating example of reset synchronous pwm mode initial output ?h? active level ?l? m n p value in trd0 register count source m+1 trdiod0 output q m-n trdiod1 output m: value set in trdgra0 register n: value set in trdgrb0 register p: value set in trdgra1 register q: value set in trdgrb1 register active level ?l? set to 0 by a program trdiob0 output imfa bit in trdsr0 register 1 0 imfb bit in trdsr0 register 1 0 imfa bit in trdsr1 register 1 0 imfb bit in trdsr1 register 1 0 tstarti bit in trdstr register 1 0 n+1 trdioc1 output trdioa1 output m-q m-p trdiob1 output trdioc0 output p+1 initial output ?h? i = 0 or 1 the above applies under the following conditions: bits ols1 and ols0 in the trdfcr register are set to 0 (initial output level ?h?, active level ?l?). 0000h set to 0 by a program set to 0 by a program set to 0 by a program transfer from the buffer register to the general register during buffer operation transfer from the buffer register to the general register during buffer operation q+1 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 236 of 485 rej09b0244-0300 14.3.9 complementary pwm mode in this mode, 3 normal-phases and 3 counter-phases of the pwm waveform are output with the same period (three-phase, triangular wave modulation, and with dead time). figure 14.85 shows a block diagram of complementary pwm mode, and table 14.31 lists the complementary pwm mode specifications. figures 14.86 to 14.94 show the registers associated with complementary pwm mode, figure 14.95 shows the output model of complementary pwm mode, and figure 14.96 shows an operating example of complementary pwm mode. figure 14.85 block diagram of complementary pwm mode period trdioc0 trdiob0 trdiod0 trdioa1 trdioc1 trdiob1 trdiod1 pwm1 pwm2 pwm3 waveform control trdgrb0 register trdgra1 register trdgrb1 register normal-phase counter-phase trdgra0 register trdgrd0 register trdgrc1 register trdgrd1 register buffer normal-phase counter-phase normal-phase counter-phase free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 237 of 485 rej09b0244-0300 i = 0 or 1, j = either a, b, c, or d note: 1. after a count starts, the pwm period is fixed. table 14.31 complementary pwm mode specifications item specification count sources f1, f2, f4, f8, f32, foco40m external signal input to the trdclk pin (valid edge selected by a program) set bits tck2 to tck0 in the trdcr1 register to the same value (same count source) as bits tck2 to tck0 in the trdcr0 register. count operations increment or decrement registers trd0 and trd1 are decrement ed with the compare match in registers trd0 and trdgra0 during increment oper ation. the trd1 register value is changed from 0000h to ffffh during decreme nt operation, and registers trd0 and trd1 are incremented. pwm operations pwm period: 1/fk (m+2-p) 2 (1) dead time: p active level width of normal-phase: 1/fk (m-n-p+1) 2 active level width of counter-phase: 1/fk (n+1-p) 2 fk: frequency of count source m: value set in the trdgra0 register n: value set in the trdgrb0 register (pwm1 output) value set in the trdgra1 register (pwm2 output) value set in the trdgrb1 register (pwm3 output) p: value set in the trd0 register count start condition 1 (count starts) is written to bits tstart0 and tstart1 in the trdstr register. count stop conditions 0 (count stops) is written to bits tstart0 and tstart1 in the trdstr register when the csel0 bit in the trdstr register is set to 1. (the pwm output pin holds output level before the count stops.) interrupt request generation timing ? compare match (the content of the trdi register matches c ontent of the trdgrji register.) ? the trd1 register underflows trdioa0 pin function programmable i/o port or trdclk (external clock) input trdiob0 pin function pwm1 output normal-phase output trdiod0 pin function pwm1 output counter-phase output trdioa1 pin function pwm2 output normal-phase output trdioc1 pin function pwm2 output counter-phase output trdiob1 pin function pwm3 output normal-phase output trdiod1 pin function pwm3 output counter-phase output trdioc0 pin function output inverted every 1/2 period of pwm int0 pin function programmable i/o port, pulse output forced cutoff signal input or int0 interrupt input read from timer the count value can be read by reading the trdi register. write to timer the value can be written to the trdi register. select functions ? pulse output forced cutoff signal input (refer to 14.3.4 pulse output forced cutoff. ) ? the active level of normal-phase and counter-phase and initial output level selected individually ? transfer timing from the buffer register selected ? a/d trigger generated n+1 normal-phase (when ?l? is selected as the active level) counter-phase m+2-p n+1-p p m-p-n+1 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 238 of 485 rej09b0244-0300 figure 14.86 trdstr register in complementary pwm mode timer rd start register (1) symbol address after reset trdstr 0137h 11111100b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. when the csel0 bit is set to 1, w rite 0 to the tstart0 bit. when the csel1 bit is set to 1, w rite 0 to the tstart1 bit. when the csel0 bit is set to 0 and the compare match signal (trdioa0) is generated, this bit is set to 0 (count stops). when the csel1 bit is set to 0 and the compare match signal (trdioa1) is generated, this bit is set to 0 (count stops). set the trdstr register using the mov instruction (do not use the bit handling instruction). refer to 14.3.12.1 t rdst r re g is t e r of notes on timer rd . trd0 count operation select bit 0 : count stops at compare match w ith the trdgra0 register 1 : count continues at compare match w ith the trdgra0 register csel0 rw rw trd1 count operation select bit 0 : count stops at compare match w ith the trdgra1 register 1 : count continues at compare match w ith the trdgra1 register ? ? (b7-b4) rw tsta rt1 rw trd1 count start flag (5) 0 : count stops (3) 1 : count starts trd0 count start flag (4) 0 : count stops (2) 1 : count starts nothing is assigned. if necessary, set to 0. when read, the content is 1. b7 b6 b5 b4 b3 b2 csel1 b1 b0 tsta rt0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 239 of 485 rej09b0244-0300 figure 14.87 trdmr register in complementary pwm mode timer rd mode register symbol address after reset trdmr 0138h 00001110b bit symbol bit name function rw rw bfc1 bfd1 trdgrd1 register function select bit 0 : general register 1 : buffer register of trdgrb1 register trdgrc0 register function select bit set this bit to 0 (general register) in c omplement ar y pwm mode. bfc0 rw rw trdgrd0 register function select bit 0 : general register 1 : buffer register of trdgrb0 register trdgrc1 register function select bit 0 : general register 1 : buffer register of trdgra1 register rw rw ? (b3-b1) ? timer rd synchronous bit set this bit to 0 (registers trd0 and trd1 operate independently) in complementary pwm mode. nothing is assigned. if necessary, set to 0. when read, the content is 1. 0 b7 b6 b5 b4 b3 b2 bfd0 b1 b0 0 sync free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 240 of 485 rej09b0244-0300 figure 14.88 trdfcr register in complementary pwm mode timer rd function control register symbol address after reset trdfcr 013ah 10000000b bit symbol bit name function rw notes: 1. 2. 3. 4. set the adcap bit in the adc0n0 register to 1 (starts by timer rd). when setting bits cmd1 to cmd0 to 10b or 11b, the mcu enters complementary pwm mode in spite of the setting of the trdpmr register. stclk external clock input select bit 0 : external clock input disabled 1 : external clock input enabled rw rw pwm3 rw adtrg adeg a/d trigger edge select bit (in complementary pwm mode) 0 : a/d trigger is generated at compare match betw een registers trd0 and trdgra0 1 : a/d trigger is generated at underflow in the trd1 register rw pwm3 mode select bit (4) this bit is disabled in complementary pwm mode. normal-phase output level select bit (in reset synchronous pwm mode or c omplement ar y pwm mode) 0 : initial output ?h? active level ?l? 1 : initial output ?l? active level ?h? set bits cmd1 to cmd0 w hen both the tstart0 and tstart1 bits are set to 0 (count stops). ols0 rw rw counter-phase output level select bit (in reset synchronous pwm mode or c omplement ar y pwm mode) 0 : initial output ?h? active level ?l? 1 : initial output ?l? active level ?h? a/d trigger enable bit (in complementary pwm mode) 0 : disable a/d trigger 1 : enable a/d trigger (3) rw cmd1 rw combination mode select bits (1,2) b1 b0 1 0 : complementary pwm mode (transfer from the buffer register to the general register at the underflow in the trd1 register) 1 1 : complementary pwm mode (transfer from the buffer register to the general register at the compare match w ith registers trd0 and trdgra0.) other than above : do not set. cmd0 b7 b6 b5 b4 when bits cmd1 to cmd0 are set to 00b (timer mode, pwm mode, or pwm3 mode), the setting of the pwm3 bit is enabled. b3 b2 ols1 b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 241 of 485 rej09b0244-0300 figure 14.89 registers trdoer1 to trdoer2 in complementary pwm mode timer rd output master enable register 1 symbol address after reset trdoer1 013bh ffh bit symbol bit name function rw ed1 rw ea 1 eb1 rw trdiod1 output disable bit 0 : enable output 1 : disable output (the trdiod1 pin is used as a programmable i/o port.) trdiob1 output disable bit 0 : enable output 1 : disable output (the trdiob1 pin is used as a programmable i/o port.) ec1 trdioc0 output disable bit 0 : enable output 1 : disable output (the trdioc0 pin is used as a programmable i/o port.) ec0 rw rw trdioa1 output disable bit 0 : enable output 1 : disable output (the trdioa1 pin is used as a programmable i/o port.) rw rw trdiod0 output disable bit 0 : enable output 1 : disable output (the trdiod0 pin is used as a programmable i/o port.) trdioc1 output disable bit 0 : enable output 1 : disable output (the trdioc1 pin is used as a programmable i/o port.) rw eb0 rw trdioa0 output disable bit set this bit to 1 (the trdioa0 pin is used as a programmable i/o port) in c omplement ar y pwm mode. trdiob0 output disable bit 0 : enable output 1 : disable output (the trdiob0 pin is used as a programmable i/o port.) b7 b6 b5 b4 b3 b2 ed0 b1 b0 1 ea 0 timer rd output master enable register 2 symbol address after reset trdoer2 013ch 01111111b bit symbol bit name function rw int0 _ ____ of pulse output forced 0 : pulse output forced cutoff input disabled cutoff signal input enabled bit (1) 1 : pulse output forced cutoff input enabled (all bits in the trdoer1 register are set to 1 (disable output) w hen ?l? is applied to the int0 _ ____ pin.) note: 1. ? (b6-b0) nothing is assigned. if necessary, set to 0. when read, the content is 1. rw pto b7 b6 b5 b4 ref er to 14.3.4 pulse output forced cutoff. b3 b2 b1 b0 ? free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 242 of 485 rej09b0244-0300 figure 14.90 registers trdcr0 to trdcr1 in complementary pwm mode timer rd control register i (i = 0 or 1) symbol address after reset trdcr0 trdcr1 0140h 0150h 00h 00h bit symbol bit name function rw notes: 1. 2. 3. bits ckeg1 to ckeg0 are enabled w hen bits tck2 to tck0 are set to 101b (trdclk input) and the stclk bit in the trdfcr register is set to 1 (external clock input enabled). rw ckeg1 cclr0 rw set to 000b (disable clearing (free-running operation)) in complementary pwm mode. trdi counter clear select bits this setting is enabled w hen the stclk bit in the trdfcr register is set to 1 (external clock input enabled). set bits tck2 to tck0 and bits ckeg1 to ckeg0 in registers trdcr0 and trdcr1 to the same values. b3 b2 ckeg0 b1 b0 tck2 000 b7 b6 b5 b4 rw rw rw cclr2 cclr1 rw count source select bits (2) b2 b1 b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : trdclk input (1) 1 1 0 : foco40m 1 1 1 : do not set. external clock edge select bits (2,3) b4 b3 0 0 : count at the rising edge 0 1 : count at the fa lling edge 1 0 : count at both edges 1 1 : do not set. rw tck1 rw tck0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 243 of 485 rej09b0244-0300 figure 14.91 registers trdsr0 to trdsr1 in complementary pwm mode timer rd status register i (i = 0 or 1) symbol address after reset trdsr0 trdsr1 0143h 0153h 11100000b 11000000b bit symbol bit name function rw notes: 1. 2. 3. b3 b2 imfd b1 b0 b7 b6 b5 b4 rw imfb rw input capture/compare match flag a [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrai register. input capture/compare match flag b [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrbi register. imfa input capture/compare match flag c [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrci register (3) . nothing is assigned to b5 in the trdsr0 register. when w riting to b5, w rite 0. when reading, the content is 1. imfc rw rw input capture/compare match flag d [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrdi register (3) . overflow flag [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the trdi register overflow s. rw ov f udf underflow flag (1) [source for setting this bit to 0] write 0 after read (2) . [source for setting this bit to 1] when the trd1 register underflow s. rw including w hen the bfji bit in the trdmr register is set to 1 (trdgrji is used as the buffer register). ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. the w riting results are as follow s: ? this bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. ? this bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0). ? this bit remains unchanged if 1 is w ritten to it. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 244 of 485 rej09b0244-0300 figure 14.92 registers trdier0 to trdier1 in complementary pwm mode timer rd interrupt enable register i (i = 0 or 1) symbol address after reset trdier0 trdier1 0144h 0154h 11100000b 11100000b bit symbol bit name function rw ov ie ? (b7-b5) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. rw input capture/compare match interrupt enable bit d 0 : disable interrupt (imid) by the imfd bit 1 : enable interrupt (imid) by the imfd bit overflow /underflow interrupt enable bit 0 : disable interrupt (ovi) by the ovf and udf bits 1 : enable interrupt (ovi) by the ovf and udf bits rw input capture/compare match interrupt enable bit c 0 : disable interrupt (imic) by the imfc bit 1 : enable interrupt (imic) by the imfc bit imiec rw rw imieb rw input capture/compare match interrupt enable bit a 0 : disable interrupt (imia) by the imfa bit 1 : enable interrupt (imia) by the imfa bit input capture/compare match interrupt enable bit b 0 : disable interrupt (imib) by the imfb bit 1 : enable interrupt (imib) by the imfb bit imiea b7 b6 b5 b4 b3 b2 imied b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 245 of 485 rej09b0244-0300 figure 14.93 registers trd0 to trd1 in complementary pwm mode figure 14.94 registers trdgra i, trdgrbi, trdgrc1, and trdgrd i in complementary pwm mode the following registers are disabled in the co mplementary pwm mode: trdpmr, trdocr, trddf0, trddf1, trdiora0, trdiorc0, trdpocr0, trdiora1, trdiorc1, and trdpocr1. timer rd counter 0 (1) symbol address after reset trd0 0147h-0146h 0000h setting range rw note: 1. function set the dead time. count a count source. count operation is incremented or decremented. when an overflow occurs, the ovf bit in the trdsr0 register is set to 1. 0000h to ffffh rw access the trd0 register in 16-bit units. do not access it in 8-bit units. b0 b7 ( b8) b0 ( b15) b7 timer rd counter 1 (1) symbol address after reset trd1 0157h-0156h 0000h setting range rw note: 1. ( b8) b0 ( b15) b7 access the trd1 register in 16-bit units. do not access it in 8-bit units. b0 b7 function select 0000h. count a count source. count operation is incremented or decremented. when an underflow occurs, the udf bit in the trdsr1 register is set to 1. 0000h to ffffh rw timer rd general registers ai, bi, c1, and di (i = 0 or 1) (1, 2) symbol address after reset trdgra 0 trdgrb0 trdgrd0 trdgra 1 trdgrb1 trdgrc1 trdgrd1 0149h-0148h 014bh-014ah 014fh-014eh 0159h-0158h 015bh-015ah 015dh-015ch 015fh-015eh ffffh ffffh ffffh ffffh ffffh ffffh ffffh rw notes: 1. 2. the trdgrc0 register is not used in complementary pwm mode. rw function ref er to table 14.32 trdgrji register functions in com plem entary pwm mode . access registers trdgrai to trdgrdi in 16-bit units. do not access them in 8-bit units. b0 b7 ( b8) b0 ( b15) b7 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 246 of 485 rej09b0244-0300 bfc0, bfd0, bfc1, bfd1: bits in trdmr register since values cannot be written to the trdgrb0, trdgra1, or trdgrb1 register directly after count operation starts (prohibited item), use the trdgrd0, trdgrc1, or trdgrd1 register as a buffer register. however, to write data to the trdgrd0, trdgrc1, or trdgrd1 register, set bits bfd0, bfc1, and bfd1 to 0 (general register). after this, bits bfd0, bfc1, and bfd1 may be set to 1 (buffer register). table 14.32 trdgrji register functions in complementary pwm mode register setting register function pwm output pin trdgra0 ? general register. set the pw m period at initialization. setting range: setting value or above in trd0 register ffffh - trd0 register setting value or below do not write to this register when the tstart0 and tstart1 bits in the trdstr register are set to 1 (count starts). (output inverted every half period of trdioc0 pin) trdgrb0 ? general register. set the changi ng point of pwm1 output at initialization. setting range: setting value or above in trd0 register trdgra0 register - trd0 register setting value or below do not write to this register when the tstart0 and tstart1 bits in the trdstr register are set to 1 (count starts). trdiob0 trdiod0 trdgra1 ? general register. set the changi ng point of pwm2 output at initialization. setting range: setting value or above in trd0 register trdgra0 register - trd0 register setting value or below do not write to this register when the tstart0 and tstart1 bits in the trdstr register are set to 1 (count starts). trdioa1 trdioc1 trdgrb1 ? general register. set the changi ng point of pwm3 output at initialization. setting range: setting value or above in trd0 register trdgra0 register - trd0 register setting value or below do not write to this register when the tstart0 and tstart1 bits in the trdstr register are set to 1 (count starts). trdiob1 trdiod1 trdgrc0 ? this register is n ot used in complementary pwm mode. ? trdgrd0 bfd0 = 1 buffer register. set the changing point of next pwm1 output. (refer to 14.3.2 buffer operation. ) setting range: setting value or above in trd0 register trdgra0 register - trd0 register setting value or below set this register to the same value as the trdgrb0 register for initialization. trdiob0 trdiod0 trdgrc1 bfc1 = 1 buffer register. set the changing point of next pwm2 output. (refer to 14.3.2 buffer operation. ) setting range: setting value or above in trd0 register trdgra0 register - trd0 register setting value or below set this register to the same value as the trdgra1 register for initialization. trdioa1 trdioc1 trdgrd1 bfd1 = 1 buffer register. set the changing point of next pwm3 output. (refer to 14.3.2 buffer operation. ) setting range: setting value or above in trd0 register trdgra0 register - trd0 register setting value or below set this register to the same value as the trdgrb1 register for initialization. trdiob1 trdiod1 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 247 of 485 rej09b0244-0300 figure 14.95 output model of complementary pwm mode value in trdi register trdiod0 output 0000h value in trdgra0 register value in trdgrb0 register value in trdgra1 register value in trdgrb1 register trdiob0 output trdioc1 output trdioa1 output trdiod1 output trdiob1 output trdioc0 output value in trd0 register value in trd1 register i = 0 or 1 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 248 of 485 rej09b0244-0300 figure 14.96 operating example of complementary pwm mode m+2-p p n+1 n+1-p p n+1-p n n n m-p-n+1 m n value in trdi register count source trdiod0 output p m: value set in trdgra0 register n: value set in trdgrb0 register p: value set in trd0 register trdiob0 output imfa bit in trdsr0 register 1 0 trdgrb0 register bits tstart0 and tstart1 in trdstr register 1 0 trdioc0 output 0000h m+1 (m-p-n+1) 2 width of normal- phase active level dead time (n+1-p) 2 width of counter-phase active level set to ffffh 1 0 udf bit in trdsr1 register 1 0 following data modify with a program trdgrd0 register transfer (when bits cmd1 to cmd0 are set to 11b) transfer (when bits cmd1 to cmd0 are set to 10b) value in trd1 register value in trd0 register cmd0, cmd1: bits in trdfcr register i = 0 or 1 the above applies under the following conditions: bits ols1 and ols0 in trdfcr are set to 0 (initial output level ?h?, active level ?l? for normal-phase and counter-phase) set to 0 by a program active level ?l? initial output ?h? initial output ?h? set to 0 by a program set to 0 by a program imfb bit in trdsr0 register free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 249 of 485 rej09b0244-0300 14.3.9.1 transfer timing from buffer register ? transfer from the trdgrd0, trdgrc1, or trdg rd1 register to the trdgrb0, trdgra1, or trdgrb1 register. when bits cmd1 to cmd0 in the trdfcr register ar e set to 10b, the content is transferred when the trd1 register underflows. when bits cmd1 to cmd0 are set to 11b, the conten t is transferred at compare match between registers trd0 and trdgra0. 14.3.9.2 a/d trigger generation compare match between registers trd0 and trdgra0 and trd1 underflow can be used as the conversion start trigger of the a/d converter. the trigger is se lected by bits adeg and adt rg in the trdfcr register. also, set the adcap bit in the adcon0 register to 1 (starts by timer rd). free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 250 of 485 rej09b0244-0300 14.3.10 pwm3 mode in this mode, 2 pwm waveforms are output with the same period. figure 14.97 shows a block diagram of pwm3 mode, and table 14.33 lists the pwm3 mode specifications. figures 14.98 to 14.106 show the registers associ ated with pwm3 mode, and figure 14.107 shows an operating example of pwm3 mode. figure 14.97 block diagram of pwm3 mode trdioa0 output control trdgrc0 compare match signal trdiob0 output control comparator trdgra0 trd0 trdgrc1 compare match signal comparator trdgra1 trdgrd0 comparator trdgrb0 trdgrd1 comparator trdgrb1 compare match signal compare match signal buffer free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 251 of 485 rej09b0244-0300 i = 0 or 1, j = either a, b, c, or d table 14.33 pwm3 mode specifications item specification count sources f1, f2, f4, f8, f32, foco40m count operations the trd0 register is incremented (the trd1 is not used). pwm waveform pwm period: 1/fk (m+1) active level width of t rdioa0 output: 1/fk (m-n) active level width of trdi ob0 output: 1/fk (p-q) fk: frequency of count source m: value set in the trdgra0 register n: value set in the trdgra1 register p: value set in the trdgrb0 register q: value set in the trdgrb1 register count start condition 1 (count starts) is written to the tstart0 bit in the trdstr register. count stop conditions ? 0 (count stops) is written to the tstart0 bit in the trdstr register when the csel0 bit in the trdstr register is set to 1. the pwm output pin holds output level before the count stops ? when the csel0 bit in the trdstr register is set to 0, the count stops at the compare match with the trdgra0 register. the pwm output pin holds level after output change by compare match. interrupt request generation timing ? compare match (the content of the trdi register matches content of the trdgrji register.) ? the trd0 register overflows trdioa0, trdiob0 pin functions pwm output trdioc0, trdiod0, trdioa1 to trdiod1 pin functions programmable i/o port int0 pin function programmable i/o port, pulse output forced cutoff signal input, or int0 interrupt input read from timer the count value can be read by reading the trd0 register. write to timer the value can be written to the trd0 register. select functions ? pulse output forced cutoff signal input (refer to 14.3.4 pulse output forced cutoff. ) ? buffer operation (refer to 14.3.2 buffer operation. ) ? active level selectable by pin m+1 trdioa0 output trdiob0 output (when ?h? is selected as the active level) p-q m-n n+1 p+1 q+1 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 252 of 485 rej09b0244-0300 figure 14.98 registers trdstr and trdmr in pwm3 mode timer rd start register (1) symbol address after reset trdstr 0137h 11111100b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. ? (b7-b4) nothing is assigned. if necessary, set to 0. when read, the content is 1. set the trdstr register using the mov instruction (do not use the bit handling instruction). refer to 14.3.12.1 t rdst r re g is t e r of no t e s o n t im e r rd . rw trd1 count operation select bit [this bit is not used in pwm3 mode] 0 : count stops at compare match w ith the trdgra1 register 1 : count continues at compare match w ith the trdgra1 register ? trd0 count operation select bit 0 : count stops at compare match w ith the trdgra0 register 1 : count continues at compare match w ith the trdgra0 register csel0 rw rw tsta rt1 rw trd1 count start flag (5) 0 : count stops (3) 1 : count starts trd0 count start flag (4) 0 : count stops (2) 1 : count starts b7 b6 b5 b4 b3 b2 csel1 b1 b0 tsta rt0 when the csel0 bit is set to 1, w rite 0 to the tstart0 bit. when the csel1 bit is set to 1, w rite 0 to the tstart1 bit. when the csel0 bit is set to 0 and the compare match signal (trdioa0) is generated, this bit is set to 0 (count stops). when the csel1 bit is set to 0 and the compare match signal (trdioa1) is generated, this bit is set to 0 (count stops). timer rd mode register symbol address after reset trdmr 0138h 00001110b bit symbol bit name function rw b3 b2 bfd0 b1 b0 sync b7 b6 b5 b4 rw ? (b3-b1) ? timer rd synchronous bit set this bit to 0 (trd0 and trd1 operate independently) in pwm3 mode. nothing is assigned. if necessary, set to 0. when read, the content is 1. rw trdgrd0 register function select bit 0 : general register 1 : buffer register of trdgrb0 register trdgrc1 register function select bit 0 : general register 1 : buffer register of trdgra1 register rw trdgrc0 register function select bit 0 : general register 1 : buffer register of trdgra0 register bfc0 rw rw bfc1 bfd1 trdgrd1 register function select bit 0 : general register 1 : buffer register of trdgrb1 register free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 253 of 485 rej09b0244-0300 figure 14.99 trdfcr register in pwm3 mode timer rd function control register symbol address after reset trdfcr 013ah 10000000b bit symbol bit name function rw notes: 1. 2. stclk external clock input select bit set this bit to 0 (external clock input disabled) in pwm3 mode. rw rw pwm3 rw adtrg adeg a/d trigger edge select bit (enabled in complementary pwm mode) this bit is disabled in pwm3 mode. rw pwm3 mode select bit (2) set this bit to 0 (pwm3 mode) in pwm3 mode. normal-phase output level select bit (enabled in reset synchronous pwm mode or complementary pwm mode) this bit is disabled in pwm3 mode. set bits cmd1 to cmd0 w hen both the tstart0 and tstart1 bits are set to 0 (count stops). ols0 rw rw counter-phase output level select bit (enabled in reset synchronous pwm mode or complementary pwm mode) this bit is disabled in pwm3 mode. a/d trigger enable bit (enabled in complementary pwm mode) this bit is disabled in pwm3 mode. rw cmd1 rw combination mode select bits (1) set to 00b (timer mode, pwm mode, or pwm3 mode) in pwm3 mode. cmd0 b7 b6 b5 b4 00 when bits cmd1 to cmd0 are set to 00b (timer mode, pwm mode, or pwm3 mode), the setting of the pwm3 bit is enabled. b3 b2 ols1 b1 b0 00 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 254 of 485 rej09b0244-0300 figure 14.100 registers trdoer1 to trdoer2 in pwm3 mode timer rd output master enable register 1 symbol address after reset trdoer1 013bh ffh bit symbol bit name function rw b3 b2 ed0 b1 b0 11 ea 0 b7 b6 b5 b4 1111 ec0 rw rw eb0 rw trdioa0 output disable bit 0 : enable output 1 : disable output (the trdioa0 pin is used as a programmable i/o port.) trdiob0 output disable bit 0 : enable output 1 : disable output (the trdiob0 pin is used as a programmable i/o port.) trdiod0 output disable bit rw trdioa1 output disable bit rw rw set these bits to 1 (programmable i/o port) in pwm3 mode. trdioc0 output disable bit ed1 rw ea 1 eb1 rw trdiod1 output disable bit trdiob1 output disable bit ec1 trdioc1 output disable bit timer rd output master enable register 2 symbol address after reset trdoer2 013ch 01111111b bit symbol bit name function rw int0 _ ____ of pulse output forced 0 : pulse output forced cutoff input disabled 1 : pulse output forced cutoff input enabled (all bits in the trdoer1 register are set to 1 (disable output) w hen ?l? is applied to the int0 _ ____ pin.) note: 1. ref er to 14.3.4 pulse output forced cutoff. ? ? (b6-b0) nothing is assigned. if necessary, set to 0. when read, the content is 1. rw pto cutoff signal input enabled bit (1) b7 b6 b5 b4 b3 b2 b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 255 of 485 rej09b0244-0300 figure 14.101 trdocr register in pwm3 mode timer rd output control register (1) symbol address after reset trdocr 013dh 00h bit symbol bit name function rw notes: 1. 2. if the pin function is set for w aveform output (refer to tables 14.12 and 14.13 ), the initial output level is output w hen the trdocr r egis ter is s et. toa 1 tob1 rw trdiod1 initial output level select bit trdiob1 initial output level select bit toc1 trdioc1 initial output level select bit these bits are disabled in pwm3 mode. trdioc0 initial output level select bit write to the trdocr register w hen both bits tstart0 and tstart1 in the trdstr register are set to 0 (count toc0 rw rw trdioa1 initial output level select bit rw rw trdiod0 initial output level select bit tod1 rw rw tob0 rw trdioa0 output level select bit (2) 0 : active level ?h?, initial output ?l?, output ?h? at compare match w ith the trdgra 1r egis ter , output ?l? at compare match w ith the trdgra 0 r egis ter 1 : active level ?l?, initial output ?h?, output ?l? at compare match w ith the trdgra 1r egis ter , output ?h? at compare match w ith the trdgra 0 r egis ter trdiob0 output level select bit (2) 0 : active level ?h?, initial output ?l?, output ?h? at compare match w ith the trdgrb1register, output ?l? at compare match w ith the trdgrb0 register 1 : active level ?l?, initial output ?h?, output ?l? at compare match w ith the trdgrb1register, output ?h? at compare match w ith the trdgrb0 register b7 b6 b5 b4 b3 b2 tod0 b1 b0 toa 0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 256 of 485 rej09b0244-0300 figure 14.102 trdcr0 register in pwm3 mode timer rd control register 0 (2) symbol address after reset trdcr0 0140h 00h bit symbol bit name function rw notes: 1. 2. bits ckeg1 to ckeg0 are enabled w hen bits tck2 to tck0 are set to 101b (trdclk input) and the stclk bit in the trdfcr register is set to 1 (external clock input enabled). rw ckeg1 cclr0 rw set to 001b (the trd0 register cleared at compare match w ith trdgra0 register) in pwm3 mode. trd0 counter clear select bits rw b3 b2 ckeg0 b1 b0 tck2 001 b7 b6 b5 b4 count source select bits b2 b1b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : do not set. 1 1 0 : foco40m 1 1 1 : do not set. external clock edge select bits (1) these bits are disabled in pwm3 mode. the trdcr1 register is not used in pwm3 mode. rw tck1 rw tck0 rw rw rw cclr2 cclr1 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 257 of 485 rej09b0244-0300 figure 14.103 registers trdsr0 to trdsr1 in pwm3 mode timer rd status register i (i = 0 or 1) symbol address after reset trdsr0 0143h 11100000b trdsr1 0153h 11000000b bit symbol bit name function rw notes: 1. 2. udf underflow flag (1) this bit is disabled in pwm3 mode. rw b2 imfd b1 b0 rw b7 b6 b5 b4 b3 rw imfb rw input capture/compare match flag a [source for setting this bit to 0] write 0 after read (1) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrai register. input capture/compare match flag b [source for setting this bit to 0] write 0 after read (1) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrbi register. imfa ov f input capture/compare match flag c [source for setting this bit to 0] write 0 after read (1) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrci register (2) . imfc overflow flag [source for setting this bit to 0] write 0 after read (1) . [source for setting this bit to 1] when the trdi register overflow s. rw rw input capture/compare match flag d [source for setting this bit to 0] write 0 after read (1) . [source for setting this bit to 1] when the value in the trdi register matches w ith the value in the trdgrdi register (2) . including w hen the bfji (j = c or d) bit in the trdmr register is set to 1 (trdgrji is used as the buffer register). ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. the w riting results are as follow s: ? this bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. ? this bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0). ? this bit remains unchanged if 1 is w ritten to it. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 258 of 485 rej09b0244-0300 figure 14.104 registers trdier0 to trdier1 in pwm3 mode figure 14.105 trd0 register in pwm3 mode timer rd interrupt enable register i (i = 0 or 1) symbol address after reset trdier0 0144h 11100000b trdier1 0154h 11100000b bit symbol bit name function rw b3 b2 imied b1 b0 b7 b6 b5 b4 rw imieb rw input capture/compare match interrupt enable bit a 0 : disable interrupt (imia) by the imfa bit 1 : enable interrupt (imia) by the imfa bit input capture/compare match interrupt enable bit b 0 : disable interrupt (imib) by the imfb bit 1 : enable interrupt (imib) by the imfb bit imiea rw input capture/compare match interrupt enable bit d 0 : disable interrupt (imid) by the imfd bit 1 : enable interrupt (imid) by the imfd bit overflow /underflow interrupt enable bit 0 : disable interrupt (ovi) by the ovf bit 1 : enable interrupt (ovi) by the ovf bit rw input capture/compare match interrupt enable bit c 0 : disable interrupt (imic) by the imfc bit 1 : enable interrupt (imic) by the imfc bit imiec rw ov ie ? (b7-b5) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. timer rd counter 0 (1, 2) symbol address after reset trd0 0147h-0146h 0000h setting range rw notes: 1. 2. the trd1 register is not used in pwm3 mode. ( b8) b0 ( b15) b7 access the trd0 register in 16-bit units. do not access it in 8-bit units. b0 b7 function count a count source. count operation is incremented. when an overflow occurs, the ovf bit in the trdsr0 register is set to 1. 0000h to ffffh rw free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 259 of 485 rej09b0244-0300 figure 14.106 registers trdg rai, trdgrbi, trdgrci, and trdgrdi in pwm3 mode the following registers are di sabled in the pwm3 mode function: trdpmr, trddf0, trddf1, trdiora0, trdiorc0, trdpocr0, trdiora1, trdiorc1, and trdpocr1. timer rd general registers ai, bi, ci, and di (i = 0 or 1) (1) symbol address after reset trdgra 0 trdgrb0 trdgrc0 trdgrd0 trdgra 1 trdgrb1 trdgrc1 trdgrd1 0149h-0148h 014bh-014ah 014dh-014ch 014fh-014eh 0159h-0158h 015bh-015ah 015dh-015ch 015fh-015eh ffffh ffffh ffffh ffffh ffffh ffffh ffffh ffffh rw note: 1. rw function ref er to table 14.34 trdgrji register functions in pwm3 mode. access registers trdgrai to trdgrdi in 16-bit units. do not access them in 8-bit units. b0 b7 ( b8) b0 ( b15) b7 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 260 of 485 rej09b0244-0300 bfc0, bfd0, bfc1, bfd1: bits in trdmr register registers trdgrc0, trdgrc1, trdgrd0, and trdgrd1 are not used in pwm3 mode. to use them as buffer registers, set bits bfc0, bfc1, bfd0, and bfd1 to 0 (general register) and write a value to the trdgrc0, trdgrc1, trdgrd0, or trdgrd1 register. after this, b its bfc0, bfc1, bfd0, and bfd1 may be set to 1 (buffer register). table 14.34 trdgrji register functions in pwm3 mode register setting register function pwm output pin trdgra0 ? general register. set the pwm period. setting range: value set in trdgra1 register or above trdioa0 trdgra1 general register. set the changing point (the active level timing) of pwm output. setting range: value set in trdgra0 register or below trdgrb0 general register. set the changing point (the timing that returns to initial output level) of pwm output. setting range: value set in trdgrb1 register or above value set in trdgra0 register or below trdiob0 trdgrb1 general register. set the changing point (active level timing) of pwm output. setting range: value set in trdgrb0 register or below trdgrc0 bfc0 = 0 (these registers is not used in pwm3 mode.) ? trdgrc1 bfc1 = 0 trdgrd0 bfd0 = 0 trdgrd1 bfd1 = 0 trdgrc0 bfc0 = 1 buffer register. set the next pwm period. (refer to 14.3.2 buffer operation .) setting range: value set in trdgrc1 register or above trdioa0 trdgrc1 bfc1 = 1 buffer register. set the changing point of next pwm output. (refer to 14.3.2 buffer operation .) setting range: value set in trdgrc0 register or below trdgrd0 bfd0 = 1 buffer register. set the changing point of next pwm output. (refer to 14.3.2 buffer operation .) setting range: value set in trdgrd1 register or above, setting value or below in trdgrc0 register. trdiob0 trdgrd1 bfd1 = 1 buffer register. set the changing point of next pwm output. (refer to 14.3.2 buffer operation .) setting range: value set in trdgrd0 register or below free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 261 of 485 rej09b0244-0300 figure 14.107 operating example of pwm3 mode value in trd0 register count source trdioa0 output 0000h ffffh trdiob0 output m: value set in trdgra0 register n: value set in trdgra1 register p: value set in trdgrb0 register q: value set in trdgrb1 register m n p q tstart0 bit in trdstr register 1 0 set to 0 by a program set to 0 by a program m+1 n+1 m-n p+1 q+1 p-q count stop output ?h? at compare match with the trdgra1 register set to 0 by a program set to 0 by a program set to 0 by a program transfer m m following data transfer m output ?l? at compare match with the trdgra0 register transfer from buffer register to general register transfer from buffer register to general register initial output ?l? j = either a or b the above applies under the following conditions: ? both the toa0 and tob0 bits in the trdocr register are set to 0 (initial output level ?l?, output ?h? by compare match with t he trdgrj1 register, output ?l? at compare match with the trdgrj0 register). ? the bfc0 bit in the trdmr register is set to 1 (the trdgrc0 re gister is used as the buffer register of the trdgra0 register). csel0 bit in trdstr register 1 0 imfa bit in trdsr0 register 1 0 imfb bit in trdsr0 register 1 0 trdgra0 register trdgrc0 register free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 262 of 485 rej09b0244-0300 14.3.11 timer rd interrupt timer rd generates the timer rd interrupt request based on 6 sources for each channe l. the timer rd interrupt has 1 trdiic register (bits ir, and ilvl0 to ilvl2), and 1 vector for each channel. table 14.35 lists the registers associated with timer rd interrupt, and figure 14.108 shows a block diagram of timer rd interrupt. figure 14.108 block diagram of timer rd interrupt as with other maskable interrupts, the timer rd interrupt is controlled by the combination of the i flag, ir bit, bits ilvl0 to ilvl2, and ipl. however, since the inte rrupt source (timer rd interrupt) is generated by a combination of multiple interrupt request sources, the following differences from other maskable interrupts apply: ? when bits in the trdsri register corresponding to bits set to 1 in the trdieri register are set to 1 (enable interrupt), the ir bit in the trdiic regi ster is set to 1 (interrupt requested). ? when either bits in the trdsri register or bits in the trdieri register corresponding to bits in the trdsri register, or both of them, are set to 0, the ir bit is set to 0 (interrupt not requested). therefore, even though the interrupt is not acknowledged after the ir bit is set to 1, the interrupt request will not be maintained. ? when the conditions of other request sources are met, the ir bit remains 1. ? when multiple bits in the trdieri register are se t to 1, which request source causes an interrupt is determined by the trdsri register. ? since each bit in the trdsri register is not automatical ly set to 0 even if the interrupt is acknowledged, set each bit to 0 in the interrupt routine. for information on how to set these bits to 0, refer to the descriptions of the registers used in the different modes ( figures 14.40, 14.55, 14.68, 14.80, 14.91, and 14.103 ). table 14.35 registers associat ed with timer rd interrupt timer rd status register timer rd interrupt enable register timer rd interrupt control register channel 0 trdsr0 trdier0 trd0ic channel 1 trdsr1 trdier1 trd1ic timer rd interrupt request (ir bit in trdiic register) imfa bit imiea bit imfb bit imieb bit imfc bit imiec bit imfd bit imied bit udf bit ovf bit ovie bit i = 0 or 1 imfa, imfb, imfc, imfd, ovf, udf: bits in trdsri register imiea, imieb, imiec, imied, ovie: bits in trdier register channel i free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 263 of 485 rej09b0244-0300 refer to registers trdsr0 to trdsr1 in each mode (figures 14.40, 14.55, 14.68, 14.80, 14.91, and 14.103) for the trdsri register. refer to registers trdier0 to trdier1 in each mode (figures 14.41, 14.56, 14.69, 14.81, 14.92, and 14.104) for the trdieri register. refer to 12.1.6 interrupt control for information on the trdiic register and 12.1.5.2 relocatable vector tables for the interrupt vectors. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 264 of 485 rej09b0244-0300 14.3.12 notes on timer rd 14.3.12.1 trdstr register ? set the trdstr register using the mov instruction. ? when the cseli (i = 0 to 1) is set to 0 (the c ount stops at compare matc h of registers trdi and trdgrai), the count does not stop and the tstarti b it remains unchanged even if 0 (count stops) is written to the tstarti bit. ? therefore, set the tstarti bit to 0 to change other bits without changing the tstarti bit when the cseli bit is se to 0. ? to stop counting by a program, set the tstarti bit after setting the cseli bit to 1. although the cseli bit is set to 1 and the tstarti bit is set to 0 at the same time (with 1 instruction), the count cannot be stopped. ? table 14.36 lists the trdioji (j = a, b, c, or d) pin output level when count stops to use the trdioji (j = a, b, c, or d) pin with the timer rd output. 14.3.12.2 trdi register (i = 0 or 1) ? when writing the value to the trdi register by a pr ogram while the tstarti bit in the trdstr register is set to 1 (count starts), avoid overlapping with the timing for setting the trdi register to 0000h, and then write. if the timing for setting the trdi register to 0000h overlaps with the timing for writing the value to the trdi register, the value is not written and the trdi register is set to 0000h. these precautions are applicable when selecting the following by bits cclr2 to cclr0 in the trdcri register. - 001b (clear by the trdi register at co mpare match with the trdgrai register.) - 010b (clear by the trdi register at co mpare match with the trdgrbi register.) - 011b (synchronous clear) - 101b (clear by the trdi register at co mpare match with the trdgrci register.) - 110b (clear by the trdi register at compare match with the trdgrdi register.) ? when writing the value to the trdi register and cont inuously reading the same register, the value before writing may be read. in this cas e, execute the jmp.b instruction between the writing and reading. program example mov.w #xxxxh, trd0 ;writing jmp.b l1 ;jmp.b l1: mov.w trd0,data ;reading 14.3.12.3 trdsri register (i = 0 or 1) when writing the value to the trdsri register and con tinuously reading the same register, the value before writing may be read. in this cas e, execute the jmp.b instruction between the writing and reading. program example mov.b #xxh, trdsr0 ;writing jmp.b l1 ;jmp.b l1: mov.b trdsr0,data ;reading table 14.36 trdioji (j = a, b, c, or d) pin output level when count stops count stop trdioji pin output when count stops when the cseli bit is set to 1, se t the tstarti bit to 0 and the count stops. hold the output level immediately before the count stops. when the cseli bit is set to 0, the count stops at compare match of registers trdi and trdgrai. hold the output level after output changes by compare match. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 265 of 485 rej09b0244-0300 14.3.12.4 count source switch ? switch the count source after the count stops. change procedure (1) set the tstarti (i = 0 or 1) bit in the trdstr register to 0 (count stops). (2) change bits tck2 to tck0 in the trdcri register. ? when changing the count source from foco40m to another source and stopping foco40m, wait 2 cycles of f1 or more after setting the clock switch, and then stop foco40m. change procedure (1) set the tstarti (i = 0 or 1) bit in the trdstr register to 0 (count stops). (2) change bits tck2 to tck0 in the trdcri register. (3) wait 2 or more cycles of f1. (4) set the fra00 bit in the fra0 register to 0 (high-speed on-chip oscillator stops). 14.3.12.5 input capture function ? set the pulse width of the input capture signal to 3 or more cycles of the timer rd operation clock (refer to table 14.11 timer rd operation clocks ). ? the value in the trdi register is transferred to the trdgrji regist er 2 to 3 cycles of the timer rd operation clock after the input capture signal is applied to the trdioji pin (i = 0 or 1, j = either a, b, c, or d) (no digital filter). 14.3.12.6 reset synchronous pwm mode ? when reset synchronous pwm mode is used fo r motor control, make sure ols0 = ols1. ? set to reset synchronous pwm mode by the following procedure: change procedure (1) set the tstart0 bit in the trdstr register to 0 (count stops). (2) set bits cmd1 to cmd0 in the trdfcr register to 00b (timer mode, pwm mode, and pwm3 mode). (3) set bits cmd1 to cmd0 to 01b (reset synchronous pwm mode). (4) set the other registers asso ciated with timer rd again. 14.3.12.7 complementary pwm mode ? when complementary pwm mode is used for motor control, make sure ols0 = ols1. ? change bits cmd1 to cmd0 in the trdf cr register in the following procedure. change procedure: when setting to complementary pwm mode (including re-set), or changing the transfer timing from the buffer register to the general register in complementary pwm mode. (1) set both the tstart0 and tstart1 bits in the trdstr register to 0 (count stops). (2) set bits cmd1 to cmd0 in the trdfcr register to 00b (timer mode, pwm mode, and pwm3 mode). (3) set bits cmd1 to cmd0 to 10b or 11b (complementary pwm mode). (4) set the registers associated with other timer rd again. change procedure: when st opping complementary pwm mode (1) set both the tstart0 and tstart1 bits in the trdstr register to 0 (count stops). (2) set bits cmd1 to cmd to 00b (timer mode, pwm mode, and pwm3 mode). ? do not write to trdgra0, trdgrb0, trdgra1, or trdgrb1 register during operation. when changing the pwm waveform, transfer the values written to registers trdgrd0, trdgrc1, and trdgrd1 to registers trdgrb0, trdgra1, and trdgrb1 using the buffer operation. however, to write data to the trdgrd0, trdgrc1, or trdgrd1 register, set bits bfd0, bfc1, and bfd1 to 0 (general register). afte r this, bits bfd0, bfc1, and bfd1 may be set to 1 (buffer register). the pwm period cannot be changed. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 266 of 485 rej09b0244-0300 ? if the value in the trdgra0 register is assumed to be m, the trd0 register counts m-1, m, m+1, m, m-1, in that order, when changing from increment to decr ement operation. when changing from m to m+1, the imfa bit is set to 1. also, bits cmd1 to cmd0 in the trdfcr register are set to 11b (complementary pwm mode, buffer data transferred at compare match between registers trd0 and trdgra0), the content in the buffer registers (trdgrd0, trdgrc1, and trdgrd1) is transferred to the general re gisters (trdgrb0, trdgra1, and trdgrb1). during m+1, m, and m-1 operation, the imfa bit remains unchanged and data are not transferred to registers such as the trdgra0 register. figure 14.109 operation at compare match between registers trd0 and trdgra0 in complementary pwm mode no change imfa bit in trdsr0 register transferred from buffer register trdgrb0 register trdgra1 register trdgrb1 register count value in trd0 register setting value in trdgra0 register m m+1 set to 0 by a program not transferred from buffer register when bits cmd1 to cmd0 in the trdfcr register are set to 11b (transfer from the buffer register to the general register at compare match of between registers trd0 and trdgra0). 1 0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 267 of 485 rej09b0244-0300 ? the trd1 register counts 1, 0, ffffh, 0, 1, in th at order, when changing fr om decrement to increment operation. the udf bit is set to 1 when changing between 1, 0, and ffffh operation. also, when bits cmd1 to cmd0 in the trdfcr register are set to 10b (com plementary pwm mode, buffer data transferred at underflow in the trd1 register), the content in the buffer registers (trdgrd0, trdgrc1, and trdgrd1) is transferred to th e general registers (trdgrb0, trdgra1, and trdgrb1). during ffffh, 0, 1 operation, data are not transferred to registers such as the trdgrb0 register. also, at this time, the ovf bit remains unchanged. figure 14.110 operation when trd1 register underflows in complementary pwm mode no change udf bit in trdsr0 register transferred from buffer register trdgrb0 register trdgra1 register trdgrb1 register count value in trd0 register set to 0 by a program not transferred from buffer register when bits cmd1 to cmd0 in the trdfcr register are set to 10b (transfer from the buffer register to the general register when the trd1 register underflows). ovf bit in trdsr0 register ffffh 1 0 1 0 0 1 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 268 of 485 rej09b0244-0300 ? select with bits cmd1 to cmd0 the timing of data tr ansfer from the buffer register to the general register. however, transfer takes place with th e following timing in spite of the value of bits cmd1 to cmd0 in the following cases: value in buffer register value in trdgra0 register: transfer take place at unde rflow of the trd1 register. after this, when the buffer register is set to 0001h or above and a smaller value than the value of the trdgra0 register, and the trd1 register underflows for the first time after setting, the value is transferred to the general re gister. after that, the value is transferred with the timing selected by bits cmd1 to cmd0. figure 14.111 operation when value in buffer register value in trdgra0 register in complementary pwm mode 0000h trdgrd0 register trdiob0 output n3 n2 m+1 n3 n2 n1 n2 n1 n3 n2 n2 n1 n1 trdgrb0 register transfer at underflow of trd1 register because of n3 > m transfer at underflow of trd1 register because of first setting to n2 < m trdiod0 output m: value set in trdgra0 register the above applies under the following conditions: ? bits cmd1 to cmd0 in the trdfcr register are set to 11b (data in the buffer register is transferred at compare match between registers trd0 and trdgra0 in complementary pwm mode). ? both the osl0 and ols1 bits in the trdfcr register ar e set to 1 (active ?h? for normal-phase and counter-phase). count value in trd0 register count value in trd1 register transfer with timing set by bits cmd1 to cmd0 transfer with timing set by bits cmd1 to cmd0 transfer transfer transfer transfer free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 269 of 485 rej09b0244-0300 when the value in the buffer register is set to 0000h: transfer takes place at compare match between registers trd0 and trdgra0. after this, when the buffer register is set to 0001h or above and a smaller value than the value of the trdgra0 register, and a compare match occurs betw een registers trd0 and trdgra0 for the first time after setting, the value is transferred to the general register. after that, the value is transferred with the timing selected by bits cmd1 to cmd0. figure 14.112 operation when value in buffer regi ster is set to 0000h in complementary pwm mode 14.3.12.8 count source foco40m ? the count source foco40m can be used with supply voltage vcc = 3.0 to 5.5 v. for supply voltage other than that, do not set bits tck2 to tck0 in re gisters trdcr0 and trdcr to 110b (select foco40m as the count source). 0000h trdgrd0 register trdiob0 output n1 m+1 n2 n1 0000h n1 0000h n1 n1 n2 trdgrb0 register transfer transfer at compare match between registers trd0 and trdgra0 because content in trdgrd0 register is set to 0000h transfer at compare match between registers trd0 and trdgra0 because of first setting to 0001h n1 < m transfer with timing set by bits cmd1 to cmd0 trdiod0 output m: value set in trdgra0 register the above applies under the following conditions: ? bits cmd1 to cmd0 in the trdfcr register are set to 10b (data in the buffer register is transferred at underflow of the trd1 register in pwm mode). ? both the ols0 and ols1 bits in the trdfcr register are set to 1 (active ?h? for normal-phase and counter-phase). count value in trd0 register count value in trd1 register transfer with timing set by bits cmd1 to cmd0 transfer transfer transfer free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 270 of 485 rej09b0244-0300 14.4 timer re timer re has the 4-bit counter and 8-bit counter. timer re has the following 2 modes: ? real-time clock mode generate 1-second signal from fc4 and count seconds, minutes, hours, and days of the week. ? output compare mode count a count source and detect compare matches. the count source for timer re is the operating clock that regulates the timing of timer operations. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 271 of 485 rej09b0244-0300 14.4.1 real-time clock mode in real-time clock mode, a 1-second si gnal is generated from fc4 using a divide-by-2 frequency divider, 4-bit counter, and 8-bit counter and used to count seconds, minutes, hours, a nd days of the week. figure 14.113 shows a block diagram of real-time clock mode and table 14.37 lists the real-time clock mode specifications. figures 14.114 to 14.118, and figures 14.120 and 14.121 show the registers associated with real-time clock mode. table 14.38 lists the interrupt sources, figure 14.119 shows the definition of time representation and figure 14.122 shows the operating example in real-time clock mode. figure 14.113 block diagram of real-time clock mode trewk register trehr register tremin register tresec register h12_h24 bit pm bit mnie hrie wkie 000 dyie seie timer re interrupt int bit bsy bit 8-bit counter 4-bit counter overflow (1s) overflow 1/2 (1/256) (1/16) fc4 h12_h24, pm, int: bits in trecr1 register bsy: bit in registers tresec, tremin, trehr, and trewk timing control data bus overflow overflow free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 272 of 485 rej09b0244-0300 table 14.37 real-time clock mode specifications item specification count source fc4 count operation increment count start condition 1 (count starts) is wr itten to tstart bit in trecr1 register count stop condition 0 (count stops) is written to tstart bit in trecr1 register interrupt request generation timing select any one of the following: ? update second data ? update minute data ? update hour data ? update day of week data ? when day of week data is set to 000b (sunday) treo pin function programmable i/o ports or output of f2, f4, or f8 read from timer when readin g tresec, tremin, trehr, or trewk register, the count value can be read. the values re ad from registers tresec, tremin, and trehr are represented by the bcd code. write to timer when bits tstart and tcstf in the trecr1 register are set to 0 (timer stops), the value can be written to registers tresec, tremin, trehr, and trewk. the values written to registers tresec, tremin, and trehr are represented by the bcd codes. select function ? 12-hour mode/24-hour mode switch function free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 273 of 485 rej09b0244-0300 figure 14.114 tresec register in real-time clock mode figure 14.115 tremin register in real-time clock mode timer re second data register symbol address after reset tresec 0118h 00h bit symbol bit name function setting range rw sc10 rw sc11 bsy ro sc12 rw rw timer re busy flag 2nd digit of second count bits when counting 0 to 5, 60 seconds are counted. 0 to 5 (bcd code) sc00 rw 1st digit of second count bits sc01 rw count 0 to 9 every second. when the digit moves up, 1 is added to the 2nd digit of second. 0 to 9 (bcd code) sc02 rw rw b7 b6 b5 b4 this bit is set to 1 w hile registers tresec, tremin, trehr, and trewk are updated. b3 b2 sc03 b1 b0 timer re minute data register symbol address after reset tremin 0119h 00h bit symbol bit name function setting range rw 2nd digit of minute count bits when counting 0 to 5, 60 minutes are counted. 0 to 5 (bcd code) this bit is set to 1 w hile registers tresec, tremin, trehr, and trewk are updated. b3 b2 mn03 b1 b0 b7 b6 b5 b4 mn00 rw 1st digit of minute count bits mn01 rw count 0 to 9 every minute. when the digit moves up, 1 is added to the 2nd digit of minute. 0 to 9 (bcd code) mn02 rw bsy ro mn12 rw mn10 rw mn11 rw rw timer re busy flag free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 274 of 485 rej09b0244-0300 figure 14.116 trehr register in real-time clock mode figure 14.117 trewk register in real-time clock mode timer re hour data register symbol address after reset trehr 011ah 00h bit symbol bit name function setting range rw this bit is set to 1 w hile registers tresec, tremin, trehr, and trewk are updated. 2nd digit of hour count bits count 0 to 1 w hen the h12_h24 bit is set to 0 (12-hour mode). count 0 to 2 w hen the h12_h24 bit is set to 1 (24-hour mode). 0 to 2 (bcd code) nothing is assigned. if necessary, set to 0. when read, the content is 0. b3 b2 hr03 b1 b0 b7 b6 b5 b4 hr00 rw 1st digit of hour count bits hr01 rw count 0 to 9 every hour. when the digit moves up, 1 is added to the 2nd digit of hour. 0 to 9 (bcd code) hr02 rw bsy ro ? (b6) rw hr10 rw hr11 ? rw timer re busy flag timer re day of week data register symbol address after reset trewk 011bh 00h bit symbol bit name function rw ? bsy ro nothing is assigned. if necessary, set to 0. when read, the content is 0. timer re busy flag this bit is set to 1 w hile registers tresec, tremin, trehr, and trewk are updated. rw wk1 rw day of w eek count bits b2 b1 b0 0 0 0 : sunday 0 0 1 : monday 0 1 0 : tuesday 0 1 1 : wednesday 1 0 0 : thursday 1 0 1 : friday 1 1 0 : saturday 1 1 1 : do not set. wk2 rw b7 b6 b5 b4 b3 b2 ? (b6-b3) b1 b0 wk0 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 275 of 485 rej09b0244-0300 figure 14.118 trecr1 register in real-time clock mode figure 14.119 definition of time representation timer re control register 1 symbol address after reset trecr1 011ch 00h bit symbol bit name function rw note: 1. rw rw h12_h24 operating mode select bit 0 : 12-hour mode 1 : 24-hour mode rw interrupt request timing bit set to 1 in real-time clock mode. pm a.m./p.m. bit when the h12_h24 bit is set to 0 (12-hour mode)(1) 0 : a.m. 1 : p.m. when the h12_h24 bit is set to 1 (24-hour mode), its value is undefined. trerst timer re reset bit when setting this bit to 0, after setting it to 1, the f ollow ings w ill occur. ? re g is t e r s tresec, tremin, trehr, trewk, and trecr2 are set to 00h. ? bits tcstf, int, pm, h12_h24, and tstart in the trecr1 register are set to 0. ? the 8-bit counter is set to 00h and the 4-bit counter is set to 0h. treo pin output enable bit 0 : disable clock output 1 : enable clock output this bit is automatically modified w hile timer re counts. toena rw rw tsta rt timer re count start bit 0 : count stops 1 : count starts rw ? tcstf ro nothing is assigned. if necessary, set to 0. when read, the content is 0. timer re count status flag 0 : count stopped 1 : counting b7 b6 b5 b4 b3 b2 int b1 b0 ? (b0) noon h12_h24 bit = 1 (24-hour mode) contents of pm bit 0 (a.m.) 1 (p.m.) contents of trehr register h12_h24 bit = 0 (12-hour mode) contents in trewk register 000 (sunday) 0 1 2 3 4 5 7 9 11 13 15 17 6 8 10 12 14 16 0 1 2 3 4 5 7 9 11 1 3 5 6 8 10 0 2 4 h12_h24 bit = 1 (24-hour mode) contents of pm bit 1 (p.m.) contents of trehr register h12_h24 bit = 0 (12-hour mode) contents in trewk register 000 (sunday) 18 19 20 21 22 23 1 3 0 2 ??? 6 7 8 9 10 11 1 3 0 2 date changes ??? ??? 0 (a.m.) 001 (monday) ??? pm bit and h12_h24 bits: bits in trecr1 register the above applies to the case when count starts from a.m. 0 on sunday. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 276 of 485 rej09b0244-0300 figure 14.120 trecr2 register in real-time clock mode table 14.38 interrupt sources factor interrupt source interrupt enable bit periodic interrupt triggered every week value in trewk register is set to 000b (sunday) (1-week period) wkie periodic interrupt triggered every day trewk register is updated (1-day period) dyie periodic interrupt triggered every hour trehr register is updated (1-hour period) hrie periodic interrupt triggered every minute tremin register is updated (1-minute period) mnie periodic interrupt triggered every second tresec register is updat ed (1-second period) seie timer re control register 2 symbol address after reset trecr2 011dh 00h bit symbol bit name function rw note: 1. rw rw ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. set to 0 in real-time clock mode. wkie periodic interrupt triggered every w eek enable bit (1) 0 : disable periodic interrupt triggered every w eek 1 : enable periodic interrupt triggered every w eek periodic interrupt triggered every hour enable bit (1) 0 : disable periodic interrupt triggered every hour 1 : enable periodic interrupt triggered every hour do not set multiple enable bits to 1 (enable interrupt). hrie rw rw periodic interrupt triggered every day enable bit (1) 0 : disable periodic interrupt triggered every day 1 : enable periodic interrupt triggered every day comie compare match interrupt enable bit rw mnie rw periodic interrupt triggered every minute enable bit (1) 0 : disable periodic interrupt triggered every minute 1 : enable periodic interrupt triggered every minute periodic interrupt triggered every second enable bit (1) 0 : disable periodic interrupt triggered every second 1 : enable periodic interrupt triggered every second 0 b7 b6 b5 b4 b3 b2 dy ie b1 b0 seie free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 277 of 485 rej09b0244-0300 figure 14.121 trecsr register in real-time clock mode timer re count source select register symbol address after reset trecsr 011eh 00001000b bit symbol bit name function rw note: 1. b3 b2 rcs3 b1 b0 00 10 rcs0 b7 b6 b5 b4 rw rcs1 rw count source select bits set to 00b in real-time clock mode. 4-bit counter select bit set to 0 in real-time clock mode. write to bits rcs5 to rcs6 w hen the toena bit in the trecr1 register is set to 0 (disable clock output). rcs2 rw rw ? (b7) ? real-time clock mode select bit set to 1 in real-time clock mode. nothing is assigned. if necessary, set to 0. when read, the content is 0. ? rw rcs6 rw rcs5 ? (b4) nothing is assigned. if necessary, set to 0. when read, the content is 0. clock output select bits (1) b6 b5 0 0 : f 2 0 1 : f 4 1 0 : f 8 1 1 : do not set. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 278 of 485 rej09b0244-0300 figure 14.122 operating example in real-time clock mode ir bit in treic register 03 ir bit in treic register bits wk2 to wk0 in trewk register (when seie bit in trecr2 register is set to 1 (enable periodic interrupt triggered every second)) (when mnie bit in trecr2 register is set to 1 (enable periodic interrupt triggered every minute)) 1 0 pm bit in trecr1 register bits hr11 to hr00 in trehr register (not changed) set to 0 by acknowledgement of interrupt request or a program 04 bits mn12 to mn00 in tremin register 58 59 00 bsy bit approx. 62.5 ms bits sc12 to sc00 in tresec register 1s bsy: bit in registers tresec, tremin, trehr, and trewk approx. 62.5 ms 1 0 1 0 (not changed) (not changed) free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 279 of 485 rej09b0244-0300 14.4.2 output compare mode in output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and compare value match is detected with the 8-bit co unter. figure 14.123 shows a block diagram of output compare mode, and table 14.39 lists the output compare mode specifications. figures 14.124 to 14.128 show the registers associated with output compare mo de, and figure 14.129 shows the operating example in output compare mode. figure 14.123 block diagram of output compare mode toena bit treo pin fc4 f32 f4 f8 4-bit counter 8-bit counter tresec tremin 1/2 rcs2 = 1 rcs2 = 0 comie bit timer re interrupt f2 match signal = 00b = 01b = 10b = 11b rcs1 to rcs0 rcs6 to rcs5 = 00b = 01b = 10b = 11b trerst, toena: bits in trecr1 register comie: bit in trecr2 register rcs0 to rcs2, rcs5 to rcs6: bits in trecsr register tq r reset trerst bit data bus comparison circuit free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 280 of 485 rej09b0244-0300 table 14.39 output compare mode specifications item specification count sources f4, f8, f32, fc4 count operations ? increment ? when the 8-bit counter content matches with the tremin register content, the value returns to 00h and count continues. the count value is held while count stops. count period ? when rcs2 = 0 (4-bit counter is not used) 1/fi x 2 x (n+1) ? when rcs2 = 1 (4-bit counter is used) 1/fi x 32 x (n+1) fi: frequency of count source n: setting value of tremin register count start condition 1 (count starts) is writt en to the tstart bit in the trecr1 register count stop condition 0 (count stops) is writte n to the tstart bit in the trecr1 register interrupt request generation timing when the 8-bit counter content matches with the tremin register content treo pin function select any one of the following: ? programmable i/o ports ? output f2, f4, or f8 ? compare output read from timer when reading the tresec register, the 8-bit counter value can be read. when reading the tremin register, the compare value can be read. write to timer writing to the tresec register is disabled. when bits tstart and tcstf in the trecr1 register are set to 0 (timer stops), writing to the tremin register is enabled. select functions ? select use of 4-bit counter ? compare output function every time the 8-bit counter value ma tches the tremin register value, treo output polarity is reversed. the treo pin outputs ?l? after reset is deasserted and the timer re is reset by the trerst bit in the trecr1 register. output level is held by setting the tstart bit to 0 (count stops). free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 281 of 485 rej09b0244-0300 figure 14.124 tresec register in output compare mode figure 14.125 tremin register in output compare mode timer re counter data register symbol address after reset tresec 0118h 00h rw b3 b2 b1 b0 ro function 8-bit counter data can be read. although timer re stops counting, the count value is held. the tresec register is set to 00h at the compare match. b7 b6 b5 b4 timer re compare data register symbol address after reset tremin 0119h 00h rw b3 b2 b1 b0 rw function 8-bit compare data is stored. b7 b6 b5 b4 free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 282 of 485 rej09b0244-0300 figure 14.126 trecr1 register in output compare mode figure 14.127 trecr2 register in output compare mode timer re control register 1 symbol address after reset trecr1 011ch 00h bit symbol bit name function rw b3 b2 int b1 b0 0 ? (b0) b7 b6 b5 b4 00 ? tcstf ro nothing is assigned. if necessary, set to 0. when read, the content is 0. timer re count status flag 0 : count stopped 1 : counting rw tsta rt timer re count start bit 0 : count stops 1 : count starts rw interrupt request timing bit set to 0 in output compare mode. pm a.m./p.m. bit trerst treo pin output enable bit 0 : disable clock output 1 : enable clock output toena rw timer re reset bit when setting this bit to 0, after setting it to 1, the f ollow ing w ill occur. ? re g is t e r s tresec, tremin, trehr, trewk, and trecr2 are set to 00h. ? bits tcstf, int, pm, h12_h24, and tstart in the trecr1 register are set to 0. ? the 8-bit counter is set to 00h and the 4-bit counter is set to 0h. rw rw h12_h24 operating mode select bit rw set to 0 in output compare mode. timer re control register 2 symbol address after reset trecr2 011dh 00h bit symbol bit name function rw b3 b2 dy ie b1 b0 00 00 seie b7 b6 b5 b4 0 ? (b7-b6) rw mnie rw periodic interrupt triggered every minute enable bit periodic interrupt triggered every second enable bit periodic interrupt triggered every day enable bit comie compare match interrupt enable bit rw rw ? nothing is assigned. if necessary, set to 0. when read, the content is 0. 0 : disable compare match interrupt 1 : enable compare match interrupt rw rw wkie periodic interrupt triggered every w eek enable bit set to 0 in output compare mode. periodic interrupt triggered every hour enable bit hrie free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 283 of 485 rej09b0244-0300 figure 14.128 trecsr register in output compare mode timer re count source select register symbol address after reset trecsr 011eh 00001000b bit symbol bit name function rw note: 1. b3 b2 rcs3 b1 b0 0 rcs0 b7 b6 b5 b4 rw rcs1 rw count source select bits b1 b0 0 0 : f 4 0 1 : f 8 1 0 : f 32 1 1 : f c4 4-bit counter select bit 0 : not used 1 : used write to bits rcs5 to rcs6 w hen the toena bit in the trecr1 register is set to 0 (disable clock output). rcs2 rw rw ? (b7) ? real-time clock mode select bit set to 0 in output compare mode. nothing is assigned. if necessary, set to 0. when read, the content is 0. ? rw rcs6 rw rcs5 ? (b4) nothing is assigned. if necessary, set to 0. when read, the content is 0. clock output select bits (1) b6 b5 0 0 : f 2 0 1 : f 4 1 0 : f 8 1 1 : compare output free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 284 of 485 rej09b0244-0300 figure 14.129 operating example in output compare mode 00h 8-bit counter content (hexadecimal number) count starts time tstart bit in trecr1 register 1 0 ir bit in treic register 1 0 the above applies under the following conditions. toena bit in trecr1 register = 1 (enable clock output) comie bit in trecr2 register = 1 (enable compare match interrupt) rcs6 to rcs5 bits in trecsr register = 11b (compare output) set to 1 by a program tremin register setting value matched treo output 1 0 tcstf bit in trecr1 register 1 0 output polarity is inverted when the compare matches matched matched 2 cycles of maximum count source set to 0 by acknowledgement of interrupt request or a program free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 285 of 485 rej09b0244-0300 14.4.3 notes on timer re 14.4.3.1 starting and stopping count timer re has the tstart bit for instructing the count to start or stop, and the tcstf bit, which indicates count start or stop. bits tstart an d tcstf are in the trecr1 register. timer re starts counting and the tcstf bit is set to 1 (count starts) when the tstart bit is set to 1 (count starts). it takes up to 2 cycles of the count source until the tcstf bit is set to 1 after setting the tstart bit to 1. during this time, do not access re gisters associated with timer re (1) other than the tcstf bit. also, timer re stops counting when setting the tstart bit to 0 (count stops) and the tcstf bit is set to 0 (count stops). it takes the time for up to 2 cycles of the count source until the tcstf bit is set to 0 after setting the tstart bit to 0. during this ti me, do not access registers associated with timer re other than the tcstf bit. note: 1. registers associated with timer re: tresec, tremin, trehr, trewk, trecr1, trecr2, and trecsr. 14.4.3.2 register setting write to the following registers or bits when timer re is stopped. ? registers tresec, tremin, trehr, trewk, and trecr2 ? bits h12_h24, pm, and int in trecr1 register ? bits rcs0 to rcs3 in trecsr register timer re is stopped when bits tstart and tcstf in the trecr1 register are set to 0 (timer re stopped). also, set all above-mentioned registers and bits (immedia tely before timer re count starts) before setting the trecr2 register. figure 14.130 shows a setting example in real-time clock mode. free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 286 of 485 rej09b0244-0300 figure 14.130 setting example in real-time clock mode stop timer re operation tcstf in trecr1 = 0? tstart in trecr1 = 0 trerst in trecr1 = 1 trerst in trecr1 = 0 setting of registers trecsr, tresec, tremin, trehr, trewk, and bits h12_h24, pm, and int in trecr1 register setting of trecr2 tstart in trecr1 = 1 tcstf in trecr1 = 1? treic 00h (disable timer re interrupt) setting of treic (ir bit 0, select interrupt priority level) timer re register and control circuit reset select clock output select clock source seconds, minutes, hours, days of week, operating mode set a.m./p.m., interrupt timing select interrupt source start timer re operation free datasheet http:///
r8c/24 group, r8c/25 group 14. timers rev.3.00 feb 29, 2008 page 287 of 485 rej09b0244-0300 14.4.3.3 time reading proce dure of real-time clock mode in real-time clock mode, read registers tresec, tr emin, trehr, and trewk wh en time data is updated and read the pm bit in the trecr1 register when th e bsy bit is set to 0 (not while data is updated). also, when reading several registers, an incorrect time will be r ead if data is updated before another register is read after reading any register. in order to prevent this, use the reading procedure shown below. ? using an interrupt read necessary contents of regi sters tresec, tremin, trehr, a nd trewk and the pm bit in the trecr1 register in the timer re interrupt routine. ? monitoring with a program 1 monitor the ir bit in the treic regi ster with a program and read necessa ry contents of registers tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register after the ir bit in the treic register is set to 1 (timer re interrupt request generated). ? monitoring with a program 2 (1) monitor the bsy bit. (2) monitor until the bsy bit is set to 0 after the bsy bit is set to 1 (approximately 62.5 ms while the bsy bit is set to 1). (3) read necessary contents of re gisters tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register after the bsy bit is set to 0. ? using read results if they are the same value twice (1) read necessary contents of re gisters tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register. (2) read the same register as (1) and compare the contents. (3) recognize as the correct value if th e contents match. if the contents do not match, repeat until the read contents match with th e previous contents. also, when reading several registers, r ead them as continuously as possible. free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 288 of 485 rej09b0244-0300 15. serial interface the serial interface consists of two channels (uart0 and uart1). each uarti (i = 0 or 1) has an exclusive timer to generate the transfer clock and operates independently. figure 15.1 shows a uarti (i = 0 or 1) block diag ram. figure 15.2 shows a uarti transmit/receive unit. uarti has two modes: clock synchronous serial i/o mode and clock asynchronous serial i/o mode (uart mode). figures 15.3 to 15.6 show the registers associated with uarti. figure 15.1 uarti (i = 0 or 1) block diagram = 01b f8 f1 = 10b clk1 to clk0 = 00b rxd0 f32 1/16 1/16 1/2 1/(n0+1) uart reception uart transmission clock synchronous type (when internal clock is selected) clock synchronous type reception control circuit transmission control circuit ckdir = 0 ckdir = 1 receive clock transmit clock transmit/ receive unit u0brg register ckdir = 0 internal external ckdir = 1 (uart0) txd0 clk polarity switch circuit clk0 clock synchronous type clock synchronous type (when external clock is selected) clock synchronous type (when internal clock is selected) rxd1 transmit/ receive unit (uart1) txd1 txd1en = 01b f8 f1 = 10b clk1 to clk0 = 00b f32 1/16 1/16 1/2 1/(n0+1) uart reception uart transmission clock synchronous type (when internal clock is selected) clock synchronous type reception control circuit transmission control circuit ckdir = 0 ckdir = 1 receive clock transmit clock u1brg register ckdir = 0 internal external ckdir = 1 clk polarity switch circuit clk1 clock synchronous type clock synchronous type (when external clock is selected) clock synchronous type (when internal clock is selected) u1pinsel u1pinsel free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 289 of 485 rej09b0244-0300 figure 15.2 uarti transmit/receive unit rxdi 1sp 2sp sp sp par prye = 0 par disabled par enabled prye = 1 uart uart (9 bits) d7 d6 d5 d4 d3 d2 d1 d0 uarti receive register uirb register 0000000d8 msb/lsb conversion circuit data bus high-order bits data bus low-order bits d7 d6 d5 d4 d3 d2 d1 d0 uitb register d8 txdi 1sp 2sp sp sp par uarti transmit register 0 i = 0 or 1 sp: stop bit par: parity bit uart (7 bits) uart (8 bits) clock synchronous type clock synchronous type uart (7 bits) clock synchronous type uart (7 bits) clock synchronous type uart (8 bits) uart (9 bits) uart (7 bits) uart (8 bits) clock synchronous type uart (9 bits) uart prye = 1 par enabled par disabled prye = 0 clock synchronous type msb/lsb conversion circuit uart (8 bits) uart (9 bits) free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 290 of 485 rej09b0244-0300 figure 15.3 registers u0tb to u1tb and u0rb to u1rb uarti receive buffer register (i = 0 or 1) (1) symbol address after reset u0rb 00a7h-00a6h undefined u1rb 00afh-00aeh undefined rw notes: 1. 2. nothing is assigned. if necessary, set to 0. when read, the content is undefined. ? (b11-b9) read out the uirb register in 16-bit units. bits sum, per, fer, and oer are set to 0 (no error) w hen bits smd2 to smd0 in the uimr register are set to 000b (serial interface disabled) or the re bit in the uic1 register is set to 0 (receive disabled). the sum bit is set to 0 (no error) w hen bits per, fer, and oer are set to 0 (no error). bits per and fer are set to 0 even w hen the higher byte of the uirb register is read out. also, bits per and fer are set to 0 w hen reading the high-order byte of the uirb register. ro sum error sum flag (2) 0 : no error 1 : error per parity error flag (2) 0 : no parity error 1 : parity error ro fer framing error flag (2) 0 : no framing error 1 : framing error ro oer overrun error flag (2) 0 : no overrun error 1 : overrun error ro bit symbol bit name ( b8) b0 ( b15) b7 b0 b7 ? ? (b7-b0) ? func tion receive data (d7 to d0) ro receive data (d8) ro ? (b8) ? uarti transmit buffer register (i = 0 or 1) (1, 2) symbol address after reset u0tb 00a3h-00a2h undefined u1tb 00abh-00aah undefined rw notes: 1. 2. transmit data nothing is assigned. if necessary, set to 0. when read, the content is undefined. ? (b8-b0) ? (b15-b9) when the transfer data length is 9 bits, w rite data to high byte first, then low byte. use the mov instruction to w rite to this register. function wo ? b0 b7 ( b8) b0 ( b15) b7 free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 291 of 485 rej09b0244-0300 figure 15.4 registers u0brg to u1brg and u0mr to u1mr uarti bit rate register (i = 0 or 1) (1, 2, 3) symbol address after reset u0brg 00a1h undefined u1brg 00a9h undefined setting range rw notes: 1. 2. 3. b7 00h to ffh func tion assuming the set value is n, uibrg divides the count source by n+1 after setting the clk0 to clk1 bits of the uic0 register, w rite to the uibrg register. b0 use the mov instruction to w rite to this register. wo write to this register w hile the serial i/o is neither transmitting nor receiving. uarti transmit/receive mode register (i = 0 or 1) symbol address after reset u0mr 00a0h 00h u1mr 00a8h 00h bit symbol bit name function rw note: 1. internal/external clock select bit 0 : internal clock 1 : external clock (1) stop bit length select bit ? (b7) reserved bit rw odd/even parity select bit enable w hen prye = 1 0 : odd parity 1 : even parity pry e parity enable bit 0 : parity disabled 1 : parity enabled rw set to 0. set the pd1_6 bit in the pd1 register to 0 (input). smd2 rw rw stps rw 0 : 1 stop bit 1 : 2 stop bits ckdir pry rw b7 b6 b5 b4 rw 0 serial i/o mode select bits b2 b1 b0 0 0 0 : serial interface disabled 0 0 1 : clock synchronous serial i/o mode 1 0 0 : uart mode transfer data 7 bits long 1 0 1 : uart mode transfer data 8 bits long 1 1 0 : uart mode transfer data 9 bits long other than above : do not set. smd1 b3 b2 b1 b0 smd0 rw free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 292 of 485 rej09b0244-0300 figure 15.5 registers u0c0 to u1c0 uarti transmit/receive control register 0 (i = 0 or 1) symbol address after reset u0c0 00a4h 00001000b u1c0 00ach 00001000b bit symbol bit name function rw note: 1. rw rw if the brg count source is sw itched, set the uibrg register again. rw data output select bit 0 : txdi pin is for cmos output 1 : txdi pin is for n-channel open drain output uform transfer format select bit 0 : lsb first 1 : msb first nch clk polarity select bit 0 : transmit data is output at f alling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge set to 0. transmit register empty flag 0 : data in transmit register (during transmit) 1 : no data in transmit register (transmit completed) nothing is assigned. if necessary, set to 0. when read, the content is 0. ? (b2) ckpol clk1 rw brg count source select bits (1) b1 b0 0 0 : selects f1 0 1 : selects f8 1 0 : selects f32 1 1 : do not set. rw rw ro ? (b4) ? reserved bit b7 b6 b5 b4 b3 b2 txept b1 b0 0 clk0 free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 293 of 485 rej09b0244-0300 figure 15.6 registers u0c1 to u1c1, u1sr, and pmr uarti transmit/receive control register 1 (i = 0 or 1) symbol address after reset u0c1 00a5h 00000010b u1c1 00adh 00000010b bit symbol bit name function rw notes: 1. 2. b0 nothing is assigned. if necessary, set to 0. when read, the content is 0. transmit enable bit (1) 0 : disables transmission 1 : enables transmission transmit buffer empty flag 0 : disables reception 1 : enables reception uiirs b3 b2 b1 ? receive enable bit b7 b6 b5 b4 rw ti ro 0 : data in uitb register 1 : no data in uitb register te ro rw ri receive complete flag (1) 0 : no data in uirb register 1 : data in uirb r egis ter re set the uirrm bit to 0 (disables continuous receive mode) in uart mode. uarti transmit interrupt cause select bit 0 : transmission buffer empty (ti=1) 1 : transmission completed (txept=1) rw uirrm uarti continuous receive mode enable bit (2) 0 : disables continuous receive mode 1 : enables continuous receive mode rw the ri bit is set to 0 w hen the higher byte of the uirb register is read out. ? (b7-b6) uart1 function select register symbol address after reset u1sr 00f5h undefined rw b7 b0 wo function set to 0fh w hen using uart1. as a result, uart1 can be used for clock synchronous or clock asynchronous serial i/o. do not set values other than 0fh. when read, its content is undefined. port mode registe r symbol address after reset pmr 00f8h 00h bit symbol bit name function rw iicsel rw 0 : selects ssu function 1 : selects i 2 c bus function set to 0. 0 : i/o ports p6_5, p6_6, p6_7 1 : clk1, txd1, rxd1 set to 0. ? reserved bits ssu / i 2 c bus sw itch bit rw b0 0 ? reserved bits u1pinsel port clk1/txd1/rxd1 sw itch bit ? (b3-b0) ? (b6-b5) b3 b2 0 b1 0 0 b7 b6 b5 b4 00 free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 294 of 485 rej09b0244-0300 15.1 clock synchronous serial i/o mode in clock synchronous serial i/o mode, data is transmitted and received using a transfer clock. table 15.1 lists the clock synchronous serial i/o mode sp ecifications. table 15.2 lists the registers used and settings in clock synchronous serial i/o mode. i = 0 or 1 notes: 1. if an external clock is selected , ensure that the external clock is ?h? when the ckpol bit in the uic0 register is set to 0 (tr ansmit data output at fallin g edge and receive data in put at rising edge of transfer clock), and that the external clock is ?l? when the ckpol bit is set to 1 (transmit data output at rising edge and receive data inpu t at falling edge of transfer clock). 2. if an overrun error occu rs, the receive data (b0 to b8) of the uirb register will be undefined. the ir bit in the siric register remains unchanged. table 15.1 clock synchronous serial i/o mode specifications item specification transfer data format ? transfer data length: 8 bits transfer clocks ? ckdir bit in uimr register is set to 0 (internal clock): fi/(2(n+1)) fi = f1, f8, f32 n = value set in uibrg register: 00h to ffh ? the ckdir bit is set to 1 (external clock): input from clki pin transmit start conditions ? before transmission starts, the following requirements must be met (1) - the te bit in the uic1 register is set to 1 (tr ansmission enabled) - the ti bit in the uic1 register is set to 0 (data in the uitb register) receive start conditions ? before reception starts, the following requirements must be met (1) - the re bit in the uic1 register is set to 1 (reception enabled) - the te bit in the uic1 register is set to 1 (tr ansmission enabled) - the ti bit in the uic1 register is set to 0 (data in the uitb register) interrupt request generation timing ? when transmitting, one of the following conditions can be selected - the uiirs bit is set to 0 (transmit buffer empty): when transferring data from the uitb re gister to uarti transmit register (when transmission starts). - the uiirs bit is set to 1 (transmission completes): when completing data transmission from uarti transmit register. ? when receiving when data transfer from the uarti re ceive register to the uirb register (when reception completes). error detection ? overrun error (2) this error occurs if the se rial interface starts receiving the next data item before reading the uirb regi ster and receives the 7t h bit of the next data. select functions ? clk polarity selection transfer data input/output can be se lected to occur synchronously with the rising or the falling edge of the transfer clock. ? lsb first, msb first selection whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be selected. ? continuous receive mode selection receive is enabled immediately by reading the uirb register. free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 295 of 485 rej09b0244-0300 i = 0 or 1 note: 1. set bits which are not in this table to 0 when writing to the above registers in clock synchronous serial i/o mode. table 15.3 lists the i/o pin functions in clock synchro nous serial i/o mode. the txdi pin outputs ?h? level between the operating mode selection of uarti (i = 0 or 1) and transfer start. (if the nch bit is set to 1 (n-channel open-drain output), this pin is in a high-impedance state.) table 15.2 registers used and settings in clock synchronous serial i/o mode (1) register bit function uitb 0 to 7 set data transmission uirb 0 to 7 data reception can be read oer overrun error flag uibrg 0 to 7 set bit rate uimr smd2 to smd0 set to 001b ckdir select the internal clock or external clock uic0 clk1 to clk0 select the count source in the uibrg register txept transmit register empty flag nch select txdi pin output mode ckpol select the transfer clock polarity uform select the lsb first or msb first uic1 te set this bit to 1 to enable transmissi on/reception ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag uiirs select the uarti tr ansmit interrupt source uirrm set this bit to 1 to use continuous receive mode table 15.3 i/o pin functions in clock synchronous serial i/o mode pin name function selection method txd0 (p1_4) output serial data (outputs du mmy data when performing reception only) rxd0 (p1_5) input serial data pd1_5 bit in pd1 register = 0 (p1_5 can be used as an input port when performing transmission only) clk0 (p1_6) output transfer clock c kdir bit in u0mr register = 0 input transfer clock ckdir bit in u0mr register = 1 pd1_6 bit in pd1 register = 0 txd1 (p6_6) output serial data u1pinsel bit in pmr register = 1 (outputs dummy data when perf orming reception only) rxd1 (p6_7) input serial data u1pi nsel bit in pmr register = 1 pd6_7 bit in pd6 register = 0 (p6_7 can be used as an input port when performing transmission only) clk1 (p6_5) output transfer clock u 1pinsel bit in pmr register = 1 ckdir bit in u1mr register = 0 input transfer clock u1pinsel bit in pmr register = 1 pd6_5 bit in pd6 register = 0 ckdir bit in u1mr register = 1 free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 296 of 485 rej09b0244-0300 figure 15.7 transmit and receive timing ex ample in clock synchronous serial i/o mode transfer clock d0 te bit in uic1 register txdi ? example of transmit timing (when internal clock is selected) set data in uitb register transfer from uitb register to uarti transmit register tc clki tclk stop pulsing because the te bit is set to 0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 tc=tclk=2(n+1)/fi fi: frequency of uibrg count source (f1, f8, f32) n: setting value to uibrg register the above applies under the following settings: ? ckdir bit in uimr register = 0 (internal clock) ? ckpol bit in uic0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the tra nsfer clock) ? uiirs bit in uic1 register = 0 (an interrupt request is generated when the transmit buffer is empty) d0 set to 0 when interrupt request is acknowledged, or set by a program write dummy data to uitb register transfer from uitb register to uarti transmit register 1/fext d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 receive data is taken in read out from uirb register transfer from uarti receive register to uirb register ti bit in uic1 register 1 0 1 0 1 0 1 0 txept bit in uic0 register ir bit in sitic register set to 0 when interrupt request is acknowledged, or set by a program ? example of receive timing (when external clock is selected) re bit in uic1 register te bit in uic1 register ti bit in uic1 register 1 0 1 0 1 0 ri bit in uic1 register ir bit in siric register 1 0 1 0 clki rxdi the above applies under the following settings: ? ckdir bit in uimr register = 1 (external clock) ? ckpol bit in uic0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the tra nsfer clock) the following conditions are met when ?h? is applied to the clki pin before receiving data: ? te bit in uic1 register = 1 (enables transmit) ? re bit in uic1 register = 1 (enables receive) ? write dummy data to the uitb register fext: frequency of external clock i = 0 or 1 free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 297 of 485 rej09b0244-0300 15.1.1 polarity select function figure 15.8 shows the transfer clock pola rity. use the ckpol bit in the uic0 (i = 0 or 1) register to select the transfer clock polarity. figure 15.8 transfer clock polarity 15.1.2 lsb first/msb first select function figure 15.9 shows the transf er format. use the uform bit in the uic0 (i = 0 or 1) register to select the transfer format. figure 15.9 transfer format clki (1) d0 txdi ? when the ckpol bit in the uic0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) d1 d2 notes: 1. when not transferring, the clki pin level is ?h?. 2. when not transferring, the clki pin level is ?l?. d3 d4 d5 d6 d7 d0 rxdi d1 d2 d3 d4 d5 d6 d7 clki (2) d0 txdi d1 d2 d3 d4 d5 d6 d7 d0 rxdi d1 d2 d3 d4 d5 d6 d7 ? when the ckpol bit in the uic0 register = 1 (output transmit data at the rising edge and input receive data at the falling edge of the transfer clock) i = 0 or 1 clki d0 txdi ? when uform bit in uic0 register = 0 (lsb first) (1) d1 d2 d3 d4 d5 d6 d7 d0 rxdi d1 d2 d3 d4 d5 d6 d7 clki d7 txdi d6 d5 d4 d3 d2 d1 d0 rxdi ? when uform bit in uic0 register = 1 (msb first) (1) note: 1. the above applies when the ckpol bit in the uic0 register is set to 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock). d7 d6 d5 d4 d3 d2 d1 d0 i = 0 or 1 free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 298 of 485 rej09b0244-0300 15.1.3 continuous receive mode continuous receive mode is selected by setting the uirrm (i = 0 or 1) bit in the uic1 register to 1 (enables continuous receive mode). in this mode, reading the uirb regi ster sets the ti bit in the uic1 register to 0 (data in the uitb register). when the uirrm bit is set to 1, do not write dummy data to the uitb register by a program. free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 299 of 485 rej09b0244-0300 15.2 clock asynchronous serial i/o (uart) mode the uart mode allows data transmission and reception after setting the desire d bit rate and tran sfer data format. table 15.4 lists the uart mode specifications. table 15.5 lists the registers used and settings for uart mode. i = 0 or 1 note: 1. if an overrun error occu rs, the receive data (b0 to b8) of the uirb register will be undefined. the ir bit in the siric register remains unchanged. table 15.4 uart m ode specifications item specification transfer data formats ? character bit (transfer data): selectable among 7, 8 or 9 bits ? start bit: 1 bit ? parity bit: selectable among odd, even, or none ? stop bit: selectable among 1 or 2 bits transfer clocks ? ckdir bit in uimr register is set to 0 (internal clock): fj/(16(n+1)) fj = f1, f8, f32 n = value set in uibrg register: 00h to ffh ? ckdir bit is set to 1 (ext ernal clock): fext/(16(n+1)) fext: input from clki pin, n = value set in uibrg register: 00h to ffh transmit start conditions ? before transmission starts, the following are required - te bit in uic1 register is set to 1 (transmission enabled) - ti bit in uic1 register is se t to 0 (data in uitb register) receive start conditions ? before reception starts, the following are required - re bit in uic1 register is set to 1 (reception enabled) - start bit detected interrupt request generation timing ? when transmitting, one of the following conditions can be selected - uiirs bit is set to 0 (transmit buffer empty): when transferring data from the uitb register to uarti transmit register (when transmission starts). - uiirs bit is set to 1 (transfer ends): when serial interfac.e completes transmitting data from the uarti transmit register ? when receiving when transferring data from the uart i receive register to uirb register (when reception ends). error detection ? overrun error (1) this error occurs if the se rial interface starts receiving the next data item before reading the uirb re gister and receive the bit preceding the final stop bit of the next data item. ? framing error this error occurs when the set numb er of stop bits is not detected. ? parity error this error occurs when parity is enab led, and the number of 1?s in parity and character bits do not match the number of 1?s set. ? error sum flag this flag is set is set to 1 when an overrun, framing, or parity error is generated. free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 300 of 485 rej09b0244-0300 i = 0 or 1 notes: 1. the bits used for transmit/receive data are as follows: bits 0 to 6 when transfer data is 7 bits long; bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long. 2. the following bits are undefined: bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer data is 8 bits long. table 15.6 lists the i/o pin functions in uart mode. after the uarti (i = 0 or 1) operating mode is selected, the txdi pin outputs ?h? level. (if the nch bit is set to 1 (n-channel open-drain output), this pin is in a high- impedance state) until transfer starts.) table 15.5 registers used and settings for uart mode register bit function uitb 0 to 8 set transmit data (1) uirb 0 to 8 receive data can be read (1, 2) oer,fer,per,sum error flag uibrg 0 to 7 set a bit rate uimr smd2 to smd0 set to 100b when transfer data is 7 bits long set to 101b when transfer data is 8 bits long set to 110b when transfer data is 9 bits long ckdir select the internal clock or external clock stps select the stop bit pry, prye select whether parity is included and whether odd or even uic0 clk0, clk1 select the count source for the uibrg register txept transmit register empty flag nch select txdi pin output mode ckpol set to 0 uform lsb first or msb first can be selected when transfer data is 8 bits long. set to 0 when transfer data is 7 or 9 bits long. uic1 te set to 1 to enable transmit ti transmit buffer empty flag re set to 1 to enable receive ri receive complete flag uiirs select the source of uarti transmit interrupt uirrm set to 0 table 15.6 i/o pin functions in uart mode pin name function selection method txd0 (p1_4) output serial data (cannot be us ed as a port when performing reception only) rxd0 (p1_5) input serial data pd1_5 bit in pd1 register = 0 (p1_5 can be used as an input port when performing transmission only) clk0 (p1_6) programmable i/o port ckdir bit in u0mr register = 0 input transfer clock ckdir bit in u0mr register = 1 pd1_6 bit in pd1 register = 0 txd1 (p6_6) output serial data u1pinsel bit in pmr register = 1 (cannot be used as a port when performing reception only) rxd1 (p6_7) input serial data u1pinsel bit in pmr register = 1 pd6_7 bit in pd6 register = 0 (p6_7 can be used as an input port when performing transmission only) clk1 (p6_5) programmable i/o port ckdir bit in u1mr register = 0 input transfer clock u1pinsel bit in pmr register = 1 pd6_5 bit in pd6 register = 0 ckdir bit in u1mr register = 1 free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 301 of 485 rej09b0244-0300 figure 15.10 transmit timing in uart mode d0 tc d1 d2 d3 d4 d5 d6 d7 p sp st d0 d1 d2 d3 d4 d5 d6 d7 p sp st d0 d1 st d0 tc d1 d2 d3 d4 d5 d6 d7 d8 sp sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp sp st d0 d1 st transfer clock te bit in uic1 register txdi set to 0 when interrupt request is acknowledged, or set by a program ? transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit) write data to uitb register tc=16 (n + 1) / fj or 16 (n + 1) / fext fj: frequency of uibrg count source (f1, f8, f32) fext: frequency of uibrg count source (external clock) n: setting value to uibrg register i = 0 to 1 the above timing diagram applies under the following conditions: ? prye bit in uimr register = 1 (parity enabled) ? stps bit in uimr register = 0 (1 stop bit) ? uiirs bit in uic1 register = 1 (an interrupt request is generated when transmit completes) start bit parity bit stop pulsing because the te bit is set to 0 txdi write data to uitb register transfer from uitb register to uarti transmit register ti bit in uic1 register 1 0 1 0 1 0 1 0 txept bit in uic0 register ir bit sitic register stop bit ? transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits) 1 0 stop bit stop bit start bit transfer clock te bit in uic1 register ti bit in uic1 register txept bit in uic0 register ir bit in sitic register 1 0 1 0 1 0 transfer from uitb register to uarti transmit register tc=16 (n + 1) / fj or 16 (n + 1) / fext fj: frequency of uibrg count source (f1, f8, f32) fext: frequency of uibrg count source (external clock) n: setting value to uibrg register i = 0 to 1 set to 0 when interrupt request is acknowledged, or set by a program the above timing diagram applies under the following conditions: ? prye bit in uimr register = 0 (parity disabled) ? stps bit in uimr register = 1 (2 stop bits) ? uiirs bit in uic1 register = 0 (an interrupt request is generated when transmit buffer is empty) free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 302 of 485 rej09b0244-0300 figure 15.11 receive timi ng example in uart mode uibrg output set to 0 when interrupt request is accepted, or set by a program ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) the above timing diagram applies when the register bits are set as follows: ? uimr register prye bit = 0 (parity disabled) ? uimr register stps bit = 0 (1 stop bit) i = 0 or 1 uic1 register re bit start bit stop bit d0 d1 d7 rxdi transfer clock determined to be ?l? receive data taken in reception triggered when transfer clock is generated by falling edge of start bit transferred from uarti receive register to uirb register uic1 register ri bit siric register ir bit 1 0 1 0 1 0 free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 303 of 485 rej09b0244-0300 15.2.1 bit rate in uart mode, the bit rate is the frequency divided by the uibrg (i = 0 or 1) register. figure 15.12 calculation formula of uibrg (i = 0 or 1) register setting value i = 0 or 1 note: 1. for the high-speed on-chip oscillator, the correction value in the fra7 register should be written into the fra1 register. this applies when the high-speed on-chip oscillator is selected as the system clock and bits fra22 to fra20 in the fra2 register are set to 000b (divide-by-2 mode) . for the precision of the hi gh-speed on-chip oscillator, refer to 20. electrical characteristics . table 15.7 bit rate setting example in uart mode (interna l clock selected) bit rate (bps) uibrg count source system clock = 20 mhz system clock = 18.432 mhz (1) system clock = 8 mhz uibrg setting value actual time (bps) setting error (%) uibrg setting value actual time (bps) setting error (%) uibrg setting value actual time (bps) setting error (%) 1200 f8 129 (81h) 1201.92 0.16 119 (77h ) 1200.00 0.00 51 (33h) 1201.92 0.16 2400 f8 64 (40h) 2403.85 0.16 59 (3bh ) 2400.00 0.00 25 (19h) 2403.85 0.16 4800 f8 32 (20h) 4734.85 -1.36 29 (1dh) 4800.00 0.00 12 (0ch) 4807.69 0.16 9600 f1 129 (81h) 9615.38 0.16 119 (77h ) 9600.00 0.00 51 (33h) 9615.38 0.16 14400 f1 86 (56h) 14367.82 -0.22 79 (4fh) 14400.00 0.00 34 (22h) 14285.71 -0.79 19200 f1 64 (40h) 19230.77 0.16 59 (3bh ) 19200.00 0.00 25 (19h) 19230.77 0.16 28800 f1 42 (2ah) 29069.77 0.94 39 (27h) 28800.00 0.00 16 (10h) 29411.76 2.12 38400 f1 32 (20h) 37878.79 -1.36 29 (1dh) 38400.00 0.00 12 (0ch) 38461.54 0.16 57600 f1 21 (15h) 56818.18 -1.36 19 (13h) 57600.00 0.00 8 (08h) 55555.56 -3.55 115200 f1 10 (0ah) 113636.36 -1.36 9 (09h) 115200.00 0.00 ??? uart mode ? internal clock selected uibrg register setting value = fj bit rate 16 - 1 fj: count source frequency of the uibrg register (f1, f8, or f32) ? external clock selected fext bit rate 16 - 1 fext: count source frequency of the uibrg register (external clock) uibrg register setting value = i = 0 or 1 free datasheet http:///
r8c/24 group, r8c/25 group 15. serial interface rev.3.00 feb 29, 2008 page 304 of 485 rej09b0244-0300 15.3 notes on serial interface ? when reading data from the uirb (i = 0 or 1) register eith er in the clock synchronous serial i/o mode or in the clock asynchronous serial i/o mode. ensu re the data is read in 16-bit units. when the high-order byte of the uirb register is read, bits per and fe r in the uirb register and the ri bit in the uic1 register are set to 0. to check receive errors, read the uirb register and then use the read data. example (when reading r eceive buffer register): mov.w 00a6h,r0 ; read the u0rb register ? when writing data to the uitb register in the clock asynchronous serial i/o mode with 9-bit transfer data length, write data to the high-order byte first then the low-order byte, in 8-bit units. example (when reading tran smit buffer register): mov.b #xxh,00a3h ; write the high-order byte of u0tb register mov.b #xxh,00a2h ; write the low-order byte of u0tb register free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 305 of 485 rej09b0244-0300 16. clock synchronous serial interface the clock synchronous serial inte rface is configured as follows. clock synchronous serial interface the clock synchronous serial interface uses the registers at addresses 00b8h to 00bfh. registers, bits, symbols, and functions vary even for the same addresses depending on the mode. refer to the register diagrams of each function for details. also, the differences between clock synchronous communi cation mode and clock synchronous serial mode are the options of the transfer clock, clock output format, and data output format. 16.1 mode selection the clock synchronous serial interface has four modes. table 16.1lists the mode selections. refer to 16.2 clock synchronous serial i/o with chip select (ssu) and the sections that follow for details of each mode. clock synchronous serial i/o with chip select (ssu) clock synchronous communication mode 4-wire bus communication mode i 2 c bus interface i 2 c bus interface mode clock synchronous serial mode table 16.1 mode selections iicsel bit in pmr register bit 7 in 00b8h (ice bit in iccr1 register) bit 0 in 00bdh (ssums bit in ssmr2 register, fs bit in sar register) function mode 0 0 0 clock synchronous serial i/o with chip select clock synchronous communication mode 0 0 1 4-wire bus communication mode 11 0 i 2 c bus interface i 2 c bus interface mode 1 1 1 clock synchronous serial mode free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 306 of 485 rej09b0244-0300 16.2 clock synchronous serial i/ o with chip select (ssu) clock synchronous serial i/o with chip select sup ports clock synchronous serial data communication. table 16.2 lists the clock synchronous serial i/o with ch ip select specifications, a nd figure 16.1 shows a block diagram of clock synchronous serial i/o with chip sel ect. figures 16.2 to 16.9 show clock synchronous serial i/o with chip select associated registers. note: 1. clock synchronous serial i/o with chip se lect has only one interrupt vector table. table 16.2 clock synchronous serial i/ o with chip select specifications item specification transfer data format ? transfer data length: 8 bits continuous transmission and reception of serial data are supported since both transmitter and receiver have buffer structures. operating modes ? clock synchronous communication mode ? 4-wire bus communication mode (including bidirectional communication) master/slave de vice selectable i/o pins ssck (i/o): clock i/o pin ssi (i/o): data i/o pin sso (i/o): data i/o pin scs (i/o): chip-select i/o pin transfer clocks ? when the mss bit in the sscrh register is set to 0 (operates as slave device), external clock is selected (input from ssck pin). ? when the mss bit in the sscrh register is set to 1 (operates as master device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16, f1/8 and f1/4, output from ssck pin) is selected. ? clock polarity and phase of ssck can be selected. receive error detection ? overrun error overrun error occurs during reception and completes in error. while the rdrf bit in the sssr register is set to 1 (data in the ssrdr register) and when next serial data receive is co mpleted, the orer bit is set to 1. multimaster error detection ? conflict error when the ssums bit in the ssmr2 register is set to 1 (4-wire bus communication mode) and the mss bit in the sscrh register is set to 1 (operates as master device) and when starting a serial communication, the ce bit in the sssr register is se t to 1 if ?l? applies to the scs pin input. when the ssums bit in the ssmr2 register is set to 1 (4-wire bus communication mode), the mss bit in the sscrh register is set to 0 (operates as slave device) and the scs pin input changes state from ?l? to ?h?, the ce bit in the sssr register is set to 1. interrupt requests 5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full, overrun error, and conflict error). (1) select functions ? data transfer direction selects msb-first or lsb-first ? ssck clock polarity selects ?l? or ?h? level when clock stops ? ssck clock phase selects edge of data change and data download free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 307 of 485 rej09b0244-0300 figure 16.1 block diagram of clock sync hronous serial i/o with chip select ssmr register data bus transmit/receive control circuit sscrl register sscrh register sser register sssr register ssmr2 register sstdr register sstrsr register ssrdr register selector multiplexer sso ssi scs ssck interrupt requests (txi, tei, rxi, oei, and cei) internal clock generation circuit f1 internal clock (f1/i) i = 4, 8, 16, 32, 64, 128, or 256 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 308 of 485 rej09b0244-0300 figure 16.2 sscrh register ss control register h symbol address after reset sscrh 00b8h 00h bit symbol bit name function rw notes: 1. 2. 3. the ssck pin functions as the transfer clock output pin w hen the mss bit is set to 1 (operates as master device). the mss bit is set to 0 (operates as slave device) w hen the ce bit in the sssr register is set to 1 (conflict error occurs). rsstp receive single stop bit (3) 0 : maintains receive operation after receiving 1 byte of data 1 : completes receive operation after receiving 1 byte of data rw ? (b7) nothing is assigned. if necessary, set to 0. when read, the content is 0. the set clock is used w hen the internal clock is selected. ? master/slave device select bit (2) 0 : operates as slave device 1 : operates as master device rw mss ? (b4-b3) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. cks1 cks2 transfer clock rate select bits (1) b2 b1 b0 0 0 0 : f1/256 0 0 1 : f1/128 0 1 0 : f1/64 0 1 1 : f1/32 1 0 0 : f1/16 1 0 1 : f1/8 1 1 0 : f1/4 1 1 1 : do not set. cks0 rw rw rw the rsstp bit is disabled w hen the mss bit is set to 0 (operates as slave device). b7 b6 b5 b4 b3 b2 b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 309 of 485 rej09b0244-0300 figure 16.3 sscrl register ss control register l symbol address after reset sscrl 00b9h 01111101b bit symbol bit name function rw notes: 1. 2. 3. ? (b0) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. sres clock synchronous serial i/o w ith chip select control part reset bit when this bit is set to 1, the clock synchronous serial i/o w ith chip select control block and sstrsr register are reset. the values of the registers (1) in the clock synchronous serial i/o w ith chip select register are maintained. rw b3 b2 b1 b0 b7 b6 b5 b4 ? (b7) nothing is assigned. if necessary, set to 0. when read, the content is 0. ? ? (b3-b2) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? solp sol w rite protect bit (2) the output level can be changed by the sol bit w hen this bit is set to 0. the solp bit remains unchanged even if 1 is w ritten to it. when read, the content is 1. rw do not w rite to the sol bit during data transfer. the data output after serial data is output can be changed by w riting to the sol bit before or after transfer. when w riting to the sol bit, set the solp bit to 0 and the sol bit to 0 or 1 simultaneously by the mov instruction. registers sscrh, sscrl, ssmr, sser, sssr, ssmr2, sstdr, and ssrdr. sol serial data output value setting bit when read 0 : the serial data output is set to ?l?. 1 : the serial data output is set to ?h?. when w ritten (2,3) 0 : the data output is ?l? after the serial data output. 1 : the data output is ?h? after the serial data output. rw ? (b6) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 310 of 485 rej09b0244-0300 figure 16.4 ssmr register ss mode register symbol address after reset ssmr 00bah 00011000b bit symbol bit name function rw reserved bit note: 1. ref er to 16.2.1.1 association betw een transfer clock polarity, phase, and data for the settings of the cphs and cpos bits. set to 1. when read, the content is 1. rw rw rw ? rw 0 : transfers data msb first 1 : transfers data lsb first ro bc1 bc2 bits counter 2 to 0 b2 b1 b0 0 0 0 : 8 bits left 0 0 1 : 1 bit left 0 1 0 : 2 bits left 0 1 1 : 3 bits left 1 0 0 : 4 bits left 1 0 1 : 5 bits left 1 1 0 : 6 bits left 1 1 1 : 7 bits left bc0 ro ro ssck clock phase select bit (1) 0 : change data at odd edge (dow nload data at even edge) 1 : change data at even edge (dow nload data at odd edge) cpos ssck clock polarity select bit (1) 0 : ?h? w hen clock stops 1 : ?l? w hen clock stops b7 b6 b5 b4 b3 b2 b1 b0 1 msb first/lsb first select bit mls nothing is assigned. if necessary, set to 0. when read, the content is 1. ? (b3) ? (b4) cphs free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 311 of 485 rej09b0244-0300 figure 16.5 sser register ss enable register symbol address after reset sser 00bbh 00h bit symbol bit name function rw b0 b3 b2 b1 b7 b6 b5 b4 rw rw rw ? conflict error interrupt enable bit 0 : disables conflict error interrupt request 1 : enables conflict error interrupt request ? (b2-b1) nothing is assigned. if necessary, set to 0. when read, the content is 0. ceie rw re te teie transmit end interrupt enable bit rw rie tie transmit interrupt enable bit 0 : disables transmit data empty interrupt request 1 : enables transmit data empty interrupt request 0 : disables transmit end interrupt request 1 : enables transmit end interrupt request rw receive enable bit 0 : disables receive 1 : enables receive transmit enable bit 0 : disables transmit 1 : enables transmit 0 : disables receive data full and overrun error interrupt request 1 : enables receive data full and overrun error interrupt request receive interrupt enable bit free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 312 of 485 rej09b0244-0300 figure 16.6 sssr register ss status register (7) symbol address after reset sssr 00bch 00h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. when accessing the sssr register continuously, insert one or more nop instructions betw een the instructions to access it. b0 writing 1 to ce, orer, rdrf, tend, or tdre bits invalid. to set any of these bits to 0, first read 1 then w rite 0. the rdrf bit is set to 0 w hen reading out the data from the ssrdr register. nothing is assigned. if necessary, set to 0. when read, the content is 0. tdre transmit data empty (1, 5, 6) 0 : data is not transferred from registers sstdr to sstrsr 1 : data is transferred from registers sstdr to sstrsr rw b3 b2 b1 b7 b6 b5 b4 ? (b1) nothing is assigned. if necessary, set to 0. when read, the content is 0. 0 : no data in ssrdr register 1 : data in ssrdr r egis ter orer ? (b4-b3) ce rw rw ? conflict error flag (1) 0 : no conflict errors generated 1 : conflict errors generated (2) ? overrun error flag (1) 0 : no overrun errors generated 1 : overrun errors generated (3) rw rw indicates w hen overrun errors occur and receive completes by error reception. if the next serial data receive operation is completed w hile the rdrf bit is set to 1 (data in the ssrdr register), the orer bit is set to 1. after the orer bit is set to 1 (overrun error), transmit and receive operations are disabled w hile the bit remains 1. when the serial communication is started w hile the ssums bit in the ssmr2 register is set to 1 (four-w ire bus communication mode) and the mss bit in the sscrh register is set to 1 (operates as master device), the ce bit is set rdrf receive data register full (1,4) tend transmit end (1, 5) 0 : the tdre bit is set to 0 w hen transmitting the last bit of transmit data 1 : the tdre bit is set to 1 w hen transmitting the last bit of transmit data the tdre bit is set to 1 w hen the te bit in the sser register is set to 1 (transmit enabled). transfer, the ce bit is set to 1. to 1 if ?l? is applied to the scs _ ____ pin input. refer to 16.2.7 scs _ ____ pin control and arbitration for more information. bits tend and tdre are set to 0 w hen w riting data to the sstdr register. when the ssums bit in the ssmr2 register is set to 1 (four-w ire bus communication mode), the mss bit in the sscrh register is set to 0 (operates as slave device) and the scs _ ____ pin input changes the level from ?l? to ?h? during free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 313 of 485 rej09b0244-0300 figure 16.7 ssmr2 register ss mode register 2 symbol address after reset ssmr2 00bdh 00h bit symbol bit name function rw scs _ ____ pin open drain output 0 : cmos output select bit 1 : n-channel open drain output scs _ ____ pin select bits (2) b5 b4 0 0 : functions as port 0 1 : functions as scs _ ____ input pin 1 0 : functions as scs _ ____ output pin (3) 1 1 : functions as scs _ ____ output pin (3) notes: 1. 2. 3. 4. 5. the ssi pin and sso pin corresponding port direction bits are set to 0 (input mode) w hen the soos bit is set to 0 (cmos output). the bide bit is disabled w hen the ssums bit is set to 0 (clock synchronous communication mode). rw bide bidirectional mode enable bit (1, 4) 0 : standard mode (communication using 2 pins of data input and data output) 1 : bidirectional mode (communication using 1 pin of data input and data output) thi s bi t f unct i ons as t h e scs i nput p i n b e f ore start i ng trans f er. (clock synchronous communication mode). rw rw rw rw rw rw 0 : clock synchronous communication mode 1 : four-w ire bus communication mode ssck pin open drain output select bit 0 : cmos output 1 : n-channel open drain output css1 clock synchronous serial i/o w ith chip select mode select bit (1) serial data pin open output drain select bit (1) 0 : cmos output (5) 1 : n-channel open drain output css0 soos sckos ssums csos b2 b1 b7 b6 b5 b4 b0 ref er to 16.2.2.1 association betw een data i/o pins and ss shift register for information on combinations of data i/o pins. the scs _ ____ pin functions as a port, regardless of the values of bits css0 and css1 w hen the ssums bit is set to 0 scks ssck pin select bit 0 : functions as port 1 : functions as serial clock pin rw b3 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 314 of 485 rej09b0244-0300 figure 16.8 registers sstdr and ssrdr figure 16.9 pmr register ss receive data register symbol address after reset ssrdr 00bfh ffh rw note: 1. the ssrdr register retains the data received before an overrun error occurs (orer bit in the sssr register set to 1 (overrun error)). w hen an overrun error occurs, the receive data may contain errors and therefore should be discarded. store the receive data. (1) the receive data is transferred to the ssrdr register and the receive operation is completed w hen 1 byte of data has been received by the sstrsr register. at this time, the next receive operation is possible. continuous reception is possible using registers sstrsr and ssrdr. ro function b3 b2 b1 b0 b7 b6 b5 b4 ss transmit data register symbol address after reset sstdr 00beh ffh rw b2 rw b1 function store the transmit data. the stored transmit data is transferred to the sstrsr register and transmission is started w hen it is detected that the sstrsr register is empty. when the next transmit data is w ritten to the sstdr register during the data transmission from the sstrsr register, the data can be transmitted continuously. when the mls bit in the ssmr register is set to 1 (transfer data w ith lsb-first), the data in w hich msb and lsb are reversed is read, after w riting to the sstdr register. b0 b3 b7 b6 b5 b4 port mode registe r symbol address after reset pmr 00f8h 00h bit symbol bit name function rw iicsel rw 0 : selects ssu function 1 : selects i 2 c bus function set to 0. 0 : i/o ports p6_5, p6_6, p6_7 1 : clk1, txd1, rxd1 set to 0. ? reserved bits ssu / i 2 c bus sw itch bit rw b0 0 ? reserved bits u1pinsel port clk1/txd1/rxd1 sw itch bit ? (b3-b0) ? (b6-b5) b3 b2 0 b1 0 0 b7 b6 b5 b4 00 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 315 of 485 rej09b0244-0300 16.2.1 transfer clock the transfer clock can be selected fro m among seven internal clocks (f1/256, f1/128, f1/64, f1/ 32, f1/16, f1/8, and f1/4) and an external clock. when using clock synchronous serial i/o with chip sele ct, set the scks bit in the ssmr2 register to 1 and select the ssck pin as the serial clock pin. when the mss bit in the sscrh register is set to 1 (operates as master device), an internal clock can be selected and the ssck pin functions as output. when tran sfer is started, the ssck pin outputs clocks of the transfer rate selected by bits cks0 to cks2 in the sscrh register. when the mss bit in the sscrh register is set to 0 (ope rates as slave device), an external clock can be selected and the ssck pin functions as input. 16.2.1.1 association between transf er clock polarity, phase, and data the association between the transfer clock polarity, phase and data change s according to the combination of the ssums bit in the ssmr2 register and bits cphs and cpos in the ssmr register. figure 16.10 shows the association between transf er clock polarity, phase, and transfer data. also, the msb-first transfer or lsb-first transfer can be selected by setting the mls bit in the ssmr register. when the mls bit is set to 1, transfer is started fr om the lsb and proceeds to th e msb. when the mls bit is set to 0, transfer is started fr om the msb and proceeds to the lsb. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 316 of 485 rej09b0244-0300 figure 16.10 association between transfer clock polarity, phase, and transfer data ssck b0 sso, ssi ? ssums = 0 (clock synchronous communication mode), cphs bit = 0 (data change at odd edge), and cpos bit = 0 (?h? when clock stops) b1 b2 b3 b4 b5 b6 b7 ssck cpos = 0 (?h? when clock stops) b0 sso, ssi ? ssums = 1 (4-wire bus communication mode) and cphs = 0 (data change at odd edge) b1 b2 b3 b4 b5 b6 b7 ssck cpos = 1 (?l? when clock stops) scs ssck cpos = 0 (?h? when clock stops) sso, ssi ? ssums = 1 (4-wire bus communication mode) and cphs = 1 (data download at odd edge) ssck cpos = 1 (?l? when clock stops) scs b0 b1 b2 b3 b4 b5 b6 b7 cphs and cpos: bits in ssmr register, ssums: bits in ssmr2 register free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 317 of 485 rej09b0244-0300 16.2.2 ss shift register (sstrsr) the sstrsr register is a sh ift register for transmittin g and receiving serial data. when transmit data is transferred from the sstdr regi ster to the sstrsr register and the mls bit in the ssmr register is set to 0 (msb-first), the bit 0 in the sstdr register is transferred to bit 0 in the sstrsr register. when the mls bit is set to 1 (lsb-first), bit 7 in the sstdr register is transferred to bit 0 in the sstrsr register. 16.2.2.1 association between data i/o pins and ss shift register the connection between the data i/o pins and sstrsr re gister (ss shift register ) changes according to a combination of the mss bit in the sscrh register an d the ssums bit in the ssmr2 register. the connection also changes according to the bi de bit in the ssmr2 register. figure 16.11 shows the association between data i/o pins and sstrsr register. figure 16.11 association between da ta i/o pins and sstrsr register sstrsr register sso ssi ? ssums = 0 (clock synchronous communication mode) sstrsr register sso ssi ? ssums = 1 (4-wire bus communication mode), bide = 0 (standard mode), and mss = 0 (operates as slave device) sstrsr register sso ssi ? ssums = 1 (4-wire bus communication mode), bide = 0 (standard mode), and mss = 1 (operates as master device) sstrsr register sso ssi ? ssums = 1 (4-wire bus communication mode) and bide = 1 (bidirectional mode) free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 318 of 485 rej09b0244-0300 16.2.3 interrupt requests clock synchronous serial i/o with chip select has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. si nce these interrupt requests are assigned to the clock synchronous serial i/o with chip select interrupt vector table, determining interrupt sources by flags is required. table 16.3 shows the clock synchronous serial i/o with chip select interrupt requests. ceie, rie, teie and tie: bits in sser register orer, rdrf, tend and tdre: bits in sssr register if the generation conditions in table 16.3 are met, a clock synchronous serial i/o with chip select interrupt request is generated. set each interrupt source to 0 by a clock sy nchronous serial i/ o with chip select interrupt routine. however, the tdre and tend bits are automatically set to 0 by writing transmit data to the sstdr register and the rdrf bit is automatically set to 0 by reading the ssrdr register. in particular, the tdre bit is set to 1 (data transmitted from registers sstdr to sst rsr) at the same time transmit data is written to the sstdr register. setting the tdre bit to 0 (data not transmitted from re gisters sstdr to sstrsr) can cause an additional byte of data to be transmitted. table 16.3 clock synchronous serial i/o with chip select interrupt requests interrupt request abbreviation generation condition transmit data empty txi tie = 1, tdre = 1 transmit end tei teie = 1, tend = 1 receive data full rxi rie = 1, rdrf = 1 overrun error oei rie = 1, orer = 1 conflict error cei ceie = 1, ce = 1 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 319 of 485 rej09b0244-0300 16.2.4 communication mo des and pin functions clock synchronous serial i/o with chip select switches the functions of the i/o pins in each communication mode according to the se tting of the mss bit in the sscrh register and bits re and te in the sser register. table 16.4 shows the association between communication modes and i/o pins. notes: 1. this pin can be used as a programmable i/o port. 2. do not set both bits te and re to 1 in 4-wire bus (bidirectional) communication mode. ssums and bide: bits in ssmr2 register mss: bit in sscrh register te and re: bits in sser register table 16.4 association between communication modes and i/o pins communication mode bit setting pin state ssums bide mss te re ssi sso ssck clock synchronous communication mode 0disabled001input ? (1) input 10 ? (1) output input 1 input output input 101input ? (1) output 10 ? (1) output output 1 input output output 4-wire bus communication mode 10 001 ? (1) input input 1 0 output ? (1) input 1 output input input 101input ? (1) output 10 ? (1) output output 1 input output output 4-wire bus (bidirectional) communication mode (2) 11 001 ? (1) input input 10 ? (1) output input 101 ? (1) input output 10 ? (1) output output free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 320 of 485 rej09b0244-0300 16.2.5 clock synchronous communication mode 16.2.5.1 initialization in cl ock synchronous communication mode figure 16.12 shows initialization in clock synchronous communication mode. to initialize, set the te bit in the sser register to 0 (transmit disabled) and the re bit to 0 (receive disabled) before data transmission or reception. set the te bit to 0 and the re bit to 0 before changing the communication mode or format. setting the re bit to 0 does not change the contents of flags rdrf and orer or the contents of the ssrdr register. figure 16.12 initialization in cl ock synchronous communication mode start ssmr2 register ssums bit 0 sscrh register set bits cks0 to cks2 set rsstp bit sssr register orer bit 0 (1) sser register re bit 1 (receive) te bit 1 (transmit) set bits rie, teie, and tie end note: 1. write 0 after reading 1 to set the orer bit to 0. sser register re bit 0 te bit 0 ssmr2 register scks bit 1 set soos bit sscrh register set mss bit ssmr register cphs bit 0 cpos bit 0 set mls bit free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 321 of 485 rej09b0244-0300 16.2.5.2 data transmission figure 16.13 shows an example of clock synchronous serial i/o with chip select operation for data transmission (clock synchronous communication mode). during data transmission, the clock synchronous serial i/o with chip select operates as described below. when clock synchronous serial i/o with chip select is set as a master devi ce, it outputs a synchronous clock and data. when clock synchronous serial i/o with chip sele ct is set as a slave device, it outputs data synchronized with the input clock. when the te bit is set to 1 (transmit enabled) before writing the transmit data to the sstdr register, the tdre bit is automatically set to 0 (data not transferred from registers sstdr to sstrsr) and the data is transferred from registers sstdr to sstrsr. after the tdre bit is set to 1 (data transferred from registers sstdr to sstrsr), transmission starts. when the tie bit in the sser register is set to 1, the txi in terrupt request is generated. when one frame of data is transferred while the tdre bit is set to 0, data is transferred from registers sstdr to sstrsr and transmission of the next frame is star ted. if the 8th bit is transmitted while the tdre bit is set to 1, the tend bit in the sssr register is set to 1 (the tdre bit is set to 1 when the last bit of the transmit data is transmitted) and the state is retained. the tei interrupt request is ge nerated when the teie bit in the sser register is set to 1 (transmit-end interrupt request enabled). th e ssck pin is fixed ?h? after transmit-end. transmission cannot be performed while the orer bit in th e sssr register is set to 1 (overrun er ror). confirm that the orer bit is set to 0 before transmission. figure 16.14 shows a sample flowchart of data tr ansmission (clock synchronous communication mode). figure 16.13 example of clock synchronous serial i/o with chip select operation for data transmission (clock synchronous communication mode) ssck b0 sso ? ssums = 0 (clock synchronous communication mode), cphs = 0 (data change at odd numbers), and cpos = 0 (?h? when clock stops) b1 b7 b0 b1 b7 1 frame tdre bit in sssr register 0 1 tend bit in sssr register 0 1 tei interrupt request generation write data to sstdr register processing by program 1 frame txi interrupt request generation free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 322 of 485 rej09b0244-0300 figure 16.14 sample flowchart of data transmis sion (clock synchronous communication mode) start initialization read tdre bit in sssr register sssr register tend bit 0 (1) end tdre = 1 ? write transmit data to sstdr register data transmission continues? read tend bit in sssr register tend = 1 ? no yes yes no no yes sser register te bit 0 (1) (2) (3) (1) after reading the sssr register and confirming that the tdre bit is set to 1, write the transmit data to the sstdr register. when the transmit data is written to the sstdr register, the tdre bit is automatically set to 0. (2) determine whether data transmission continues. (3) when data transmission is completed, the tend bit is set to 1. set the tend bit to 0 and the te bit to 0 and complete transmit mode. note: 1. write 0 after reading 1 to set the tend bit to 0. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 323 of 485 rej09b0244-0300 16.2.5.3 data reception figure 16.15 shows an example of clock synchronous serial i/o with chip select operation for data reception (clock synchronous communication mode). during data reception, clock synchronous serial i/o with chip select operates as described below. when the clock synchronous serial i/o with chip select is set as the master device, it outputs a synchronous clock and inputs data. when clock synchronous serial i/o with ch ip select is set as a slave device, it inputs data synchronized with the input clock. when clock synchronous serial i/o with chip select is set as a master devi ce, it outputs a receive clock and starts receiving by performing dummy read of the ssrdr register. after 8 bits of data are received, the rdrf bit in the sssr register is set to 1 (data in the ssrdr register) and receive data is stored in the ssrdr register. when the rie bit in the sser register is set to 1 (rxi and oei interrupt requests enabled), the rxi interrupt request is ge nerated. if the ssdr regist er is read, the rdrf bit is automatically set to 0 (no data in the ssrdr register). read the receive data after setting the rsstp bit in the sscrh register to 1 (after receiving 1 byte of data, the receive operation is completed). clock synchronous serial i/o with chip select outputs a clock for receiving 8 bits of data and stops. after that, set the re bit in th e sser register to 0 (receive disabled) and the rsstp bit to 0 (receive operation is continued afte r receiving the 1 byte of data) and read the receive data. if the ssrdr register is read while the re bit is set to 1 (r eceive enabled), a receive clock is output again. when the 8th clock rises while the rdrf bit is set to 1, the orer bit in the sssr register is set to 1 (overrun error: oei) and the op eration is stopped. when the orer bit is se t to 1, receive cannot be performed. confirm that the orer bit is set to 0 before restarting receive. figure 16.16 shows a sample flowchart of data re ception (mss = 1) (clock synchronous communication mode). figure 16.15 example of clock synchronous serial i/o with chip select operation for data reception (clock synchronous communication mode) ssck b0 ssi ? ssums = 0 (clock synchronous communic ation mode), cphs = 0 (data download at even edges), and cpos bit = 0 (?h? when clock stops) b0 b7 1 frame rdrf bit in sssr register 0 1 rsstp bit in sscrh register 0 1 dummy read in ssrdr register processing by program rxi interrupt request generation b0 b7 b7 1 frame rxi interrupt request generation read data in ssrdr register read data in ssrdr register set rsstp bit to 1 rxi interrupt request generation free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 324 of 485 rej09b0244-0300 figure 16.16 sample flowchart of data recepti on (mss = 1) (clock synchronous communication mode) start initialization dummy read of ssrdr register read receive data in ssrdr register read orer bit in sssr register last data received? read rdrf bit in sssr register rdrf = 1 ? no yes yes no no yes (1) (2) (3) (1) after setting each register in the clock synchronous serial i/o with chip select register, a dummy read of the ssrdr register is performed and the receive operation is started. (2) determine whether it is the last 1 byte of data to be received. if so, set to stop after the data is received. (3) if a receive error occurs, perform error (6) processing after reading the orer bit. then set the orer bit to 0. transmission/reception cannot be restarted while the orer bit is set to 1. (4) confirm that the rdrf bit is set to 1. if the rdrf bit is set to 1, read the receive data in the ssrdr register. when the ssrdr register is read, the rdrf bit is automatically set to 0. orer = 1 ? end read receive data in ssrdr register read orer bit in sssr register read rdrf in sssr register rdrf = 1 ? no yes orer = 1 ? sser register re bit 0 sscrh register rsstp bit 0 sscrh register rsstp bit 1 overrun error processing no yes (4) (5) (6) (7) (7) confirm that the rdrf bit is set to 1. when the receive operation is completed, set the rsstp bit to 0 and the re bit to 0 before reading the last 1 byte of data. if the ssrdr register is read before setting the re bit to 0, the receive operation is restarted again. (5) before the last 1 byte of data is received, set the rsstp bit to 1 and stop after the data is received. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 325 of 485 rej09b0244-0300 16.2.5.4 data transmission/reception data transmission/reception is an operation combining data transmission and reception which were described earlier. transmission/reception is started by writing data to the sstdr register. when the 8th clock rises or the orer bit is set to 1 (overrun error) while the tdre bit is set to 1 (data is transferred from registers sstd r to sstrsr), the transmit/r eceive operation is stopped. when switching from transmit mode (te = 1) or receiv e mode (re = 1) to transmit/receive mode (te = re = 1), set the te bit to 0 and re bit to 0 before switching. after confirming that the tend bit is set to 0 (the tdre bit is set to 0 when the last bit of the transmit data is transmitted), the rdrf bit is set to 0 (no data in the ssrdr register), and the orer bit is set to 0 (no overrun error), set bits te and re to 1. figure 16.17 shows a sample flowch art of data transmission/reception (clock synchronous communication mode). free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 326 of 485 rej09b0244-0300 figure 16.17 sample flowchart of data transmission/reception (clock synchronous communication mode) start initialization read tdre bit in sssr register sssr register tend bit 0 (1) end tdre = 1 ? write transmit data to sstdr register data transmission (2) continues? no yes yes no sser register re bit 0 te bit 0 (1) (2) (3) (1) after reading the sssr register and confirming that the tdre bit is set to 1, write the transmit data to the sstdr register. when the transmit data is written to the sstdr register, the tdre bit is automatically set to 0. (5) set the tend bit to 0 and bits re and te in (6) the sser register to 0 before ending transmit/ receive mode. read receive data in ssrdr register read rdrf bit in sssr register rdrf = 1 ? no yes (4) (2) confirm that the rdrf bit is set to 1. if the rdrf bit is set to 1, read the receive data in the ssrdr register. when the ssrdr register is read, the rdrf bit is automatically set to 0. (3) determine whether the data transmission continues (5) note: 1. write 0 after reading 1 to set the tend bit to 0. read tend bit in sssr register tend = 1 ? yes no (6) (4) when the data transmission is completed, the tend bit in the sssr register is set to 1. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 327 of 485 rej09b0244-0300 16.2.6 operation in 4-wire bus communication mode in 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and a chip select line is used for communication. this mode includes bidirectional mode in which the data input line and data output line function as a single pin. the data input line and output line change according to the settings of the mss bit in the sscrh register and the bide bit in the ssmr2 register. for details, refer to 16.2.2.1 association between data i/o pins and ss shift register . in this mode, clock polarity, phase, and data settings are pe rformed by bits cpos and cphs in the ssmr register. for details, refer to 16.2.1.1 association between tran sfer clock polarity, phase, and data . when this mcu is set as the master device, the chip select line controls output. when clock synchronous serial i/o with chip select is set as a slav e device, the chip select line controls input. when it is set as the master device, the chip select line controls output of the scs pin or controls ou tput of a general port according to the setting of the css1 bit in the ssmr2 register. when the mcu is set as a slave device, the chip select line sets the scs pin as an input pin by setting bits css1 and css0 in the ssmr2 register to 01b. in 4-wire bus communication mode, the mls bit in th e ssmr register is set to 0 and communication is performed msb-first. 16.2.6.1 initialization in 4-wire bus communication mode figure 16.18 shows initialization in 4-wire bus communication mode. before the data transit/receive operation, set the te bit in the sser register to 0 (tra nsmit disabled), the re bit in the sser register to 0 (receive disabled), and initialize the clock synchronous serial i/o with chip select. to change the communication mode or format, set the te bit to 0 and the re bit to 0 before making the change. setting the re bit to 0 does not change the settings of flags rdrf and orer or the contents of the ssrdr register. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 328 of 485 rej09b0244-0300 figure 16.18 initialization in 4-wire bus communication mode start ssmr2 register ssums bit 1 sssr register orer bit 0 (1) sser register re bit 1 (receive) te bit 1 (transmit) set bits rie, teie, and tie end sser register re bit 0 te bit 0 (2) set the bide bit to 1 in bidirectional mode and set the i/o of the scs pin by bits css0 and css1. (1) (1) the mls bit is set to 0 for msb-first transfer. the clock polarity and phase are set by bits cphs and cpos. (2) note: 1. write 0 after reading 1 to set the orer bit to 0. ssmr2 register scks bit 1 set bits soos, css0 to css1, and bide sscrh register set mss bit ssmr register set bits cphs and cpos mls bits 0 sscrh register set bits cks0 to cks2 set rsstp bit free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 329 of 485 rej09b0244-0300 16.2.6.2 data transmission figure 16.19 shows an example of clock synchronous se rial i/o with chip select operation during data transmission (4-wire bus communication mode). during the data transmit operation, clock synchronous serial i/o with chip select operates as described below. when the mcu is set as the master device, it outputs a synchronous clock and data. when the mcu is set as a slave device, it outputs data in synchronization with the input clock while the scs pin is ?l?. when the transmit data is written to the sstdr register after setting the te bit to 1 (transmit enabled), the tdre bit is automatically set to 0 (data has not been transferred from registers sstdr to sstrsr) and the data is transferred from registers sstdr to sstrsr. afte r the tdre bit is set to 1 (data is transferred from registers sstdr to sstrsr), transmissi on starts. when the tie bit in the sser register is set to 1, a txi interrupt request is generated. after 1 frame of data is transferred while the tdre bit is set to 0, the data is tran sferred from registers sstdr to sstrsr and transmission of the next frame is started. if the 8th bit is transmitted while tdre is set to 1, tend in the sssr register is set to 1 (when the last bit of the transmit data is transmitted, the tdre bit is set to 1) and the state is retained. if the teie bit in the sser register is set to 1 (transmit-end interrupt requests enabled), a tei interrupt request is generated. the ssck pin remains ?h? after transmit-end and the scs pin is held ?h?. when transmitting continuously while the scs pin is held ?l?, write the next transmit data to the sstdr register before transmitting the 8th bit. transmission cannot be performed while the orer bit in th e sssr register is set to 1 (overrun er ror). confirm that the orer bit is set to 0 before transmission. in contrast to the clock synchronous communication mode, the sso pin is placed in high-impedance state while the scs pin is placed in high-impedance state when opera ting as a master device and the ssi pin is placed in high-impedance state while the scs pin is placed in ?h? input state when operat ing as a slave device. the sample flowchart is the same as that for the clock synchronous communication mode (refer to figure 16.14 sample flowchart of data transmission (clock synchronous communication mode) ). free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 330 of 485 rej09b0244-0300 figure 16.19 example of clock synchronous serial i/o with chip select operation during data transmission (4-wire bus communication mode) tdre bit in sssr register 0 1 tend bit in sssr register 0 1 data write to sstdr register processing by program ssck b0 sso ? cphs bit = 0 (data change at odd edges) and cpos bit = 0 (?h? when clock stops) b7 scs (output) ssck ? cphs bit = 1 (data change at even edges) and cpos bit = 0 (?h? when clock stops) cphs, cpos: bits in ssmr register 1 frame tdre bit in sssr register 0 1 tend bit in sssr register 0 1 data write to sstdr register processing by program 1 frame high-impedance b0 b7 high-impedance scs (output) txi interrupt request is generated b7 b0 sso 1 frame 1 frame b6 b6 txi interrupt request is generated tei interrupt request is generated b6 b7 b0 b6 tei interrupt request is generated txi interrupt request is generated txi interrupt request is generated free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 331 of 485 rej09b0244-0300 16.2.6.3 data reception figure 16.20 shows an example of clock synchronous se rial i/o with chip select operation during data reception (4-wire bus communication mode). during data reception, clock synchron ous serial i/o with chip select operates as described below. when the mcu is set as the master device, it outputs a synchronous clock and inputs data. when the mcu is set as a slave device, it outputs data synchr onized with the inpu t clock while the scs pin receives ?l? input. when the mcu is set as the master device, it outputs a receive clock and starts receiving by performing a dummy read of the ssrdr register. after 8 bits of data are received, the rdrf bit in the sssr register is set to 1 (data in the ssrdr register) and receive data is stored in the ssrdr register. when the rie bit in the sser register is set to 1 (rxi and oei interrupt requests enabled), an rxi in terrupt request is generated. when the ssrdr register is read, the rdrf bit is automatically set to 0 (no data in the ssrdr register). read the receive data after setting the rsstp bit in th e sscrh register to 1 (after receiving 1-byte data, the receive operation is completed). clock synchronous serial i/o with chip select outputs a clock for receiving 8 bits of data and stops. after that, set the re bit in th e sser register to 0 (receive disabled) and the rsstp bit to 0 (receive operation is continued af ter receiving 1-byte data) and read the receive data. when the ssrdr register is read while the re bit is set to 1 (r eceive enabled), a receive clock is output again. when the 8th clock rises while the rdrf bit is set to 1, the orer bit in the sssr register is set to 1 (overrun error: oei) and the operation is st opped. when the orer bit is set to 1, reception can not be performed. confirm that the orer bit is set to 0 before restarting reception. the timing with which bits rdrf and orer are set to 1 varies depending on the setting of the cphs bit in the ssmr register. figure 16.20 shows when bits rdrf and orer are set to 1. when the cphs bit is set to 1 (dat a download at the odd edges), bits rd rf and orer are set to 1 at some point during the frame. the sample flowchart is the same as that for the clock synchronous communication mode (refer to figure 16.16 sample flowchart of data reception (mss = 1) (clock synchronou s communication mode) ). free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 332 of 485 rej09b0244-0300 figure 16.20 example of clock synchronous serial i/o with chip select operation during data reception (4-wire bus communication mode) ssck b0 ssi ? cphs bit = 0 (data download at even edges) and cpos bit = 0 (?h? when clock stops) b7 scs (output) ssck ? cphs bit = 1 (data download at odd edges) and cpos bit = 0 (?h? when clock stops) cphs and cpos: bit in ssmr register 1 frame rdrf bit in sssr register 0 1 rsstp bit in sscrh register 0 1 dummy read in ssrdr register processing by program 1 frame high-impedance b0 b7 high-impedance scs (output) b7 b0 data read in ssrdr register rxi interrupt request is generated rxi interrupt request is generated data read in ssrdr register rxi interrupt request is generated b0 b7 b0 b7 b7 b0 ssi 1 frame rdrf bit in sssr register 0 1 rsstp bit in sscrh register 0 1 dummy read in ssrdr register processing by program 1 frame data read in ssrdr register rxi interrupt request is generated rxi interrupt request is generated rxi interrupt request is generated set rsstp bit to 1 data read in ssrdr register set rsstp bit to 1 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 333 of 485 rej09b0244-0300 16.2.7 scs pin control an d arbitration when setting the ssums bit in the ssmr2 register to 1 (4-wire bus communication mode) and the css1 bit in the ssmr2 register to 1 (functions as scs output pin), set the mss bit in the sscrh register to 1 (operates as the master device) and check the arbitration of the scs pin before starting serial transfer. if clock synchronous serial i/o with chip select detect s that the synchronized internal scs signal is held ?l? in this period, the ce bit in the sssr register is set to 1 (c onflict error) and the mss bit is automa tically set to 0 (operates as a slave device). figure 16.21 shows the arbitration check timing. future transmit operations are not performed while the ce bi t is set to 1. set the ce bit to 0 (no conflict error) before starting transmission. figure 16.21 arbitration check timing data write to sstdr register maximum time of scs internal synchronization during arbitration detection high-impedance scs input internal scs (synchronization) mss bit in sscrh register transfer start ce scs output 0 1 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 334 of 485 rej09b0244-0300 16.2.8 notes on clock synchronous serial i/o with chip select set the iicsel bit in the pmr register to 0 (select clock synchronous serial i/o with chip select function) to use the clock synchronous serial i/o with chip select function. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 335 of 485 rej09b0244-0300 16.3 i 2 c bus interface the i 2 c bus interface is the circuit that performs serial comm unication based on the data transfer format of the philips i 2 c bus. table 16.5 lists the i 2 c bus interface specifications, figure 16.22 shows a block diagram of i 2 c bus interface, and figure 16.23 shows the external circuit connection example of pins scl and sda. figures 16.24 to 16.31 show the registers associated with the i 2 c bus interface. * i 2 c bus is a trademark of koninklijke philips electronics n. v. note: 1. all sources use one interrupt vector for i 2 c bus interface. table 16.5 i 2 c bus interface specifications item specification communication formats ?i 2 c bus format - selectable as master/slave device - continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent) - start/stop conditions are automatically generated in master mode - automatic loading of acknowledge bit during transmission - bit synchronization/wait function (in master mode, the state of the scl signal is monitored per bit and the timing is synchronized automatically. if the transfer is not possible yet, the scl signal goes ?l? and the interface stands by.) - support for direct drive of pins sc l and sda (n-channel open drain output) ? clock synchronous serial format - continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent) i/o pins scl (i/o): serial clock i/o pin sda (i/o): serial data i/o pin transfer clocks ? when the mst bit in the iccr1 register is set to 0 the external clock (input from the scl pin) ? when the mst bit in the iccr1 register is set to 1 the internal clock selected by bits cks0 to cks3 in the iccr1 register (output from the scl pin) receive error detection ? overrun error detection (clock synchronous serial format) indicates an overrun error during reception. when the last bit of the next data item is received while the rdrf bit in the icsr register is set to 1 (data in the icdrr register), the al bit is set to 1. interrupt sources ?i 2 c bus format .................................. 6 sources (1) transmit data empty (including when sl ave address matches), transmit ends, receive data full (including when slav e address matches), arbitration lost, nack detection, and stop condition detection. ? clock synchronous serial format ...... 4 sources (1) transmit data empty, transmit ends, receive data full and overrun error select functions ?i 2 c bus format - selectable output level for acknowledge signal during reception ? clock synchronous serial format - msb-first or lsb-first selectable as data transfer direction free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 336 of 485 rej09b0244-0300 figure 16.22 block diagram of i 2 c bus interface iccr1 register data bus iccr2 register icmr register icdrt register sar register icsr register address comparison circuit output control scl interrupt request (txi, tei, rxi, stpi, naki) transfer clock generation circuit icdrs register icdrr register bus state judgment circuit arbitration judgment circuit icier register interrupt generation circuit transmit/receive control circuit noise canceller sda output control f1 noise canceller free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 337 of 485 rej09b0244-0300 figure 16.23 external circuit connect ion example of pins scl and sda scl sda scl input scl output sda input sda output (master) vcc vcc scl sda scl input scl output sda input sda output (slave 1) scl sda scl input scl output sda input sda output scl sda (slave 2) free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 338 of 485 rej09b0244-0300 figure 16.24 iccr1 register iic bus control register 1 symbol address after reset iccr1 00b8h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. master/slave select bit (5, 6) in master mode w ith the i 2 c bus format, w hen arbitration is lost, bits mst and trs are set to 0 and the iic enters slave receive mode. when an overrun error occurs in master receive mode of the clock synchronous serial format, the mst bit is set to 0 and the iic enters slave receive mode. b0 rew rite the trs bit betw een transfer frames. rcv d receive disable bit after reading the icdrr register w hile the trs bit is set to 0 0 : maintains the next receive operation 1 : disables the next receive operation rw b3 b2 rw rw b1 b7 b6 b5 b4 cks2 cks3 cks0 cks1 rw trs transmit clock select bits 3 to 0 (1) b3 b2 b1 b0 0 0 0 0 : f1/28 0 0 0 1 : f1/40 0 0 1 0 : f1/48 0 0 1 1 : f1/64 0 1 0 0 : f1/80 0 1 0 1 : f1/100 0 1 1 0 : f1/112 0 1 1 1 : f1/128 1 0 0 0 : f1/56 1 0 0 1 : f1/80 1 0 1 0 : f1/96 1 0 1 1 : f1/128 1 1 0 0 : f1/160 1 1 0 1 : f1/200 1 1 1 0 : f1/224 1 1 1 1 : f1/256 b5 b4 0 0 : slave receive mode (4) 0 1 : slave transmit mode 1 0 : master receive mode 1 1 : master transmit mode rw mst rw rw transfer/receive select bit (2, 3, 6) in multimaster operation use the mov instruction to set bits trs and mst. when the first 7 bit after the start condition in slave receive mode match w ith the slave address set in the sar register and the 8th bit is set to 1, the trs bit is set to 1. rw ice iic bus interface enable bit 0 : this module is halted (pins scl and sda are set to port function) 1 : this module is enabled for transfer operations (pins scl and sda are bus drive state) set according to the necessary transfer rate in master mode. refer to table 16.6 transfer rate exam ples for the transfer rate. this bit is used for maintaining of the setup time in transmit mode of slave mode. the time is 10tcyc w hen the cks3 bit is set to 0 and 20tcyc w hen the cks3 bit is set to 1. (1tcyc = 1/f1(s)) free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 339 of 485 rej09b0244-0300 figure 16.25 iccr2 register iic bus control register 2 symbol address after reset iccr2 00b9h 01111101b bit symbol bit name function rw notes: 1. 2. 3. 4. ro rw ? iic control part reset bit ? (b0) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? iicrst rw when hang-up occurs due to communication failure during i 2 c bus interface operation, w rite 1, to reset the control block of the i 2 c bus interface w ithout setting ports or initializing registers. b0 b3 b2 b1 b7 b6 b5 b4 ? (b2) nothing is assigned. if necessary, set to 0. when read, the content is 1. sclo scl monitor flag 0 : scl pin is set to ?l? 1 : scl pin is set to ?h? sdaop sdao rw when read 0 : sda pin output is held ?l? 1 : sda pin output is held ?h? when w ritten (1,2) 0 : sda pin output is changed to ?l? 1 : sda pin output is changed to high-impedance (?h? output via external pull-up resistor) sda output value control bit sdao w rite protect bit when rew rite to sdao bit, w rite 0 simultaneously. (1) when read, the content is 1. when read 0 : bus is in released state (sda signal changes from ?l? to ?h? w hile scl signal is in ?h? state) 1 : bus is in occupied state (sda signal changes from ?h? to ?l? w hile scl signal is in ?h? state) when w ritten (3) 0 : generates stop condition 1 : generates start condition rw this bit is disabled w hen the clock synchronous serial format is used. this bit is enabled in master mode. when w riting to the bbsy bit, w rite 0 to the scp bit using the mov instruction simultaneously. execute the same w ay w hen the start condition is regenerating. when w riting to the sdao bit, w rite 0 to the sdaop bit using the mov instruction simultaneously. do not w rite during a transfer operation. bbsy bus busy bit (4) scp start/stop condition generation disable bit when w riting to the to bbsy bit, w rite 0 simultaneously. (3) when read, the content is 1. writing 1 is invalid. rw free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 340 of 485 rej09b0244-0300 figure 16.26 icmr register iic bus mode register symbol address after reset icmr 00bah 00011000b bit symbol bit name function rw msb-f irst/lsb-f irst select bit notes: 1. 2. 3. 4. 5. 6. set to 0 w hen the i 2 c bus format is used. when w ritin g to bits bc0 to bc2, w rite 0 to the bcwp bit usin g the mov instruction. ? (b4) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? rew rite betw een transfer frames. when w ritin g values other than 000b, w rite w hen the scl si g nal is ?l?. after data including the acknow ledge bit is transferred, these bits are automatically set to 000b. when the start condition is detected, these bits are automatically set to 000b. do not rew rite w hen the clock s y nchronous serial format is used. reserved bit wait insertion bit (5) when rew riting bits bc0 to bc2, w rite 0 simultaneously. (2,4) when read, the content is 1. rw the setting value is enabled in master mode of the i 2 c bus format. it is disabled in slave mode of the i 2 c bus format or w hen the clock synchronous serial format is used. 0 : no w ait (transfer data and acknow ledge bit consecutively) 1 : wait (after the clock falls for the final data bit, ?l? period is extended for tw o transfer clocks cycles) set to 0. rw rw 0 : data transfer w ith msb-first (6) 1 : data transfer w ith lsb-first ? (b5) wait b3 b2 b1 b0 b7 b6 b5 b4 bcwp bc w rite protect bit 0 mls rw rw bc1 bc2 bits counter 2 to 0 i 2 c bus format (remaining transfer bit count w hen read out and data bit count of next transfer w hen w ritten). (1,2) b2 b1 b0 0 0 0 : 9 bits (3) 0 0 1 : 2 bits 0 1 0 : 3 bits 0 1 1 : 4 bits 1 0 0 : 5 bits 1 0 1 : 6 bits 1 1 0 : 7 bits 1 1 1 : 8 bits clock synchronous serial format (w hen read, the remaining transfer bit count and w hen w ritten 000b). b2 b1 b0 0 0 0 : 8 bits 0 0 1 : 1 bit 0 1 0 : 2 bits 0 1 1 : 3 bits 1 0 0 : 4 bits 1 0 1 : 5 bits 1 1 0 : 6 bits 1 1 1 : 7 bits bc0 rw rw free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 341 of 485 rej09b0244-0300 figure 16.27 icier register iic bus interrupt enable register symbol address after reset icier 00bbh 00h bit symbol bit name function rw notes: 1. 2. 0 : 0 is transmitted as acknow ledge bit in receive mode. 1 : 1 is transmitted as acknow ledge bit in receive mode. b0 b3 b2 b1 na kie b7 b6 b5 b4 acke stie ackbt rw rw ro ackbr rw receive acknow ledge bit 0 : acknow ledge bit received from receive device in transmit mode is set to 0. 1 : acknow ledge bit received from receive device in transmit mode is set to 1. transmit acknow ledge select bit rie receive interrupt enable bit 0 : disables receive data full and overrun error interrupt request 1 : enables receive data full and overrun error interrupt request (1) rw acknow ledge bit judgment select bit 0 : value of receive acknow ledge bit is ignored and continuous transfer is performed. 1 : when receive acknow ledge bit is set to 1, continuous transfer is halted. rw stop condition detection interrupt enable bit 0 : disables stop condition detection interrupt request 1 : enables stop condition detection interrupt request (2) 0 : disables nack receive interrupt request and arbitration lost/overrun error interrupt request 1 : enables nack receive interrupt request and arbitration lost/overrun error interrupt request (1) nack receive interrupt enable bit set the stie bit to 1 (enable stop condition detection interrupt request) w hen the stop bit in the icsr register is set to 0. 0 : disables transmit end interrupt request 1 : enables transmit end interrupt request rw rw an overrun error interrupt request is generated w hen the clock synchronous format is used. tie transmit interrupt enable bit 0 : disables transmit data empty interrupt request 1 : enables transmit data empty interrupt request teie transmit end interrupt enable bit free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 342 of 485 rej09b0244-0300 figure 16.28 icsr register iic bus status register (7) symbol address after reset icsr 00bch 0000x000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. b0 the nackf bit is enabled w hen the acke bit in the icier register is set to 1 (w hen the receive acknow ledge bit is set to 1, transfer is halted). tdre transmit data empty (1,6) in the follow ing cases, this flag is set to 1. ? data is transferred from registers icdrt to icdrs and the icdrt register is empty ? when setting the trs bit in the iccr1 register to 1 (transmit mode) ? when generating the start condition (including retransmit) ? when changing from slave receive mode to slave transmit mode rw b3 b2 b1 b7 b6 b5 b4 rw aas al adz tend transmit end (1,6) rw rw general call address recognition flag (1,2) when the general call address is detected, this flag is set to 1. arbitration lost flag/overrun error flag (1) when the i 2 c bus format is used, this flag indicates that arbitration has been lost in master mode. in the follow ing cases, this flag is set to 1 (3) . ? when the internal sda signal and sda pin level do not match at the rise of the scl signal in master transmit mode ? when the start condition is detected and the sda pin is held ?h? in master transmit/receive mode this flag indicates an overrun error w hen the clock synchronous format is used. in the follow ing case, this flag is set to 1. ? when the last bit of the next data item is received w hile the rdrf bit is set to 1 slave address recognition flag (1) this flag is set to 1 w hen the first frame follow ing start condition matches bits sva0 to sva6 in the sar register in slave receive mode. (detect the slave address and generate call address) receive data register full (1,5) when the 9th clock cycle of the scl signal in the i 2 c bus format occurs w hile the tdre bit is set to 1, this flag is set to 1. this flag is set to 1 w hen the final bit of the transmit frame is transmitted in the clock synchronous format. no acknow ledge detection flag (1,4) this flag is enabled in slave receive mode of the i 2 c bus f or mat. each bit is set to 0 by reading 1 before w riting 0. na ckf when no acknow ledge is detected from the receive device after transmission, this flag is set to 1. rw rw when receive data is transferred from in registers icdrs to icdrr , this flag is set to 1. when accessing the icsr register continuously, insert one or more nop instructions betw een the instructions to access it. stop stop condition detection flag (1) when the stop condition is detected after the frame is transferred, this flag is set to 1. rw the rdrf bit is set to 0 w hen reading data from the icdrr register. bits tend and tdre are set to 0 w hen w riting data to the icdrt register. when tw o or more master devices attempt to occupy the bus at nearly the same time, if the i 2 c bus interface monitors the sda pin and the data w hich the i 2 c bus interface transmits is different, the al flag is set to 1 and the bus is occupied by another master. rw rdrf free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 343 of 485 rej09b0244-0300 figure 16.29 registers sar and icdrt iic bus transmit data registe r symbol address after reset icdrt 00beh ffh rw b3 b2 b7 b6 b5 b4 b1 rw function store transmit data when it is detected that the icdrs register is empty, the stored transmit data item is transferred to the icdrs register and data transmission starts. when the next transmit data item is w ritten to the icdrt register during transmission of the data in the icdrs register, continuous transmit is enabled. when the mls bit in the icmr register is set to 1 (data transferred lsb-first) and after the data is w ritten to the icdrt register, the msb-lsb inverted data is read. b0 slave address register symbol address after reset sar 00bdh 00h bit symbol bit name function rw b7 b6 b0 b1 b5 b3 b2 b4 fs 0 : i 2 c bus format 1 : clock synchronous serial format rw sva2 sva0 format select bit rw rw rw rw rw sva3 sva1 sva6 sva5 sva4 rw rw slave address 6 to 0 set an address different from that of the other slave devices w hich are connected to the i 2 c bus. when the 7 high-order bits of the first frame transmitted after the starting condition match bits sva0 to sva6 in slave mode of the i 2 c bus format, the mcu operates as a slave device. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 344 of 485 rej09b0244-0300 figure 16.30 registers icdrr and icdrs figure 16.31 pmr register iic bus receive data register symbol address after reset icdrr 00bfh ffh rw b3 b2 b1 b0 b7 b6 b5 b4 store receive data when the icdrs register receives 1 byte of data, the receive data is transferred to the icdrr register and the next receive operation is enabled. ro function iic bus shift register symbol icdrs rw this register is used to transmit and receive data. the transmit data is transferred from registers icrdt to the icdrs and data is transmitted from the sda pin w hen transmitting. after 1 byte of data received, data is transferred from registers icdrs to icdrr w hile receiving. ? function b3 b2 b1 b0 b7 b6 b5 b4 port mode registe r symbol address after reset pmr 00f8h 00h bit symbol bit name function rw iicsel rw 0 : selects ssu function 1 : selects i 2 c bus function set to 0. 0 : i/o ports p6_5, p6_6, p6_7 1 : clk1, txd1, rxd1 set to 0. ? reserved bits ssu / i 2 c bus sw itch bit rw b0 0 ? reserved bits u1pinsel port clk1/txd1/rxd1 sw itch bit ? (b3-b0) ? (b6-b5) b3 b2 0 b1 0 0 b7 b6 b5 b4 00 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 345 of 485 rej09b0244-0300 16.3.1 transfer clock when the mst bit in the iccr1 register is set to 0, the transfer clock is the external clock input from the scl pin. when the mst bit in the iccr1 register is set to 1, the transfer clock is the internal clock selected by bits cks0 to cks3 in the iccr1 register and the transfer clock is outp ut from the scl pin. table 16.6 lists the transfer rate examples. table 16.6 transfer rate examples iccr1 register transfer clock transfer rate cks3 cks2 cks1 cks0 f1 = 5 mhz f1 = 8 mhz f1 = 10 mhz f1 = 16 mhz f1 = 20 mhz 0 0 0 0 f1/28 179 khz 286 khz 357 khz 571 khz 714 khz 1 f1/40 125 khz 200 khz 250 khz 400 khz 500 khz 1 0 f1/48 104 khz 167 khz 208 khz 333 khz 417 khz 1 f1/64 78.1 khz 125 khz 156 khz 250 khz 313 khz 1 0 0 f1/80 62.5 khz 100 khz 125 khz 200 khz 250 khz 1 f1/100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 1 0 f1/112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 1 f1/128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1 0 0 0 f1/56 89.3 khz 143 khz 179 khz 286 khz 357 khz 1 f1/80 62.5 khz 100 khz 125 khz 200 khz 250 khz 1 0 f1/96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 1 f1/128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1 0 0 f1/160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 1 f1/200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 1 0 f1/224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 f1/256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 346 of 485 rej09b0244-0300 16.3.2 interrupt requests the i 2 c bus interface has six interr upt requests when the i 2 c bus format is used and four interrupt requests when the clock synchronous serial format is used. table 16.7 lists the interrupt requests of i 2 c bus interface. since these interrupt requests are allocated at the i 2 c bus interface interrupt vector table, determining the source bit by bit is necessary. stie, nakie, rie, teie, tie: bits in icier register al, stop, nackf, rdrf, tend, tdre: bits in icsr register when the generation conditions list ed in table 16.7 are met, an i 2 c bus interface interrupt request is generated. set the interrupt generation conditions to 0 by the i 2 c bus interface interrupt routin e. however, bits tdre and tend are automatically set to 0 by writing transmit data to the icdrt register and the rdrf bit is automatically set to 0 by reading the icdrr register. wh en writing transmit data to the icdrt register, the tdre bit is set to 0. when data is transferred from re gisters icdrt to icdrs, the tdre bit is set to 1 and by further setting the tdre bit to 0, 1 additional byte may be transmitted. set the stie bit to 1 (enable stop condition detecti on interrupt request) when the stop bit is set to 0. table 16.7 interrupt requests of i 2 c bus interface interrupt request generation condition format i 2 c bus clock synchronous serial transmit data empty txi tie = 1 and tdre = 1 enabled enabled transmit ends tei teie = 1 and tend = 1 enabled enabled receive data full rxi rie = 1 and rdrf = 1 enabled enabled stop condition detection stpi stie = 1 and stop = 1 enabled disabled nack detection naki nakie = 1 and al = 1 (or nakie = 1 and nackf = 1) enabled disabled arbitration lost/overrun error enabled enabled free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 347 of 485 rej09b0244-0300 16.3.3 i 2 c bus interface mode 16.3.3.1 i 2 c bus format setting the fs bit in the sar regist er to 0 enables communication in i 2 c bus format. figure 16.32 shows the i 2 c bus format and bus timing. the 1st frame following the start condition consists of 8 bits. figure 16.32 i 2 c bus format and bus timing s r/w a data a a/a p 1 7 1 1 n 1 1 1 1 m (a) i 2 c bus format (fs = 0) transfer bit count (n = 1 to 8) transfer frame count (m = from 1) s r/w a data a/a p 1 7 1 1 n1 1 1 1 m1 (b) i 2 c bus format (when start condition is retransmitted, fs = 0) upper: transfer bit count (n1, n2 = 1 to 8) lower: transfer frame count (m1, m2 = 1 or more) sla sla a/a 1 s 1 r/w a data 7 1 1 n2 sla 1 m2 sda scl s sla r/w a data a data a p 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 (1) i 2 c bus format (2) i 2 c bus timing explanation of symbols s : start condition the master device changes the sda signal from ?h? to ?l? while the scl signal is held ?h?. sla : slave address r/w : indicates the direction of data transmit/receive data is transmitted from the slave device to the master device when r/w value is 1 and from the master device to the slave devi ce when r/w value is 0. a : acknowledge the receive device sets the sda signal to ?l?. data : transmit / receive data p : stop condition the master device changes the sda signal from ?l? to ?h? while the scl signal is held ?h?. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 348 of 485 rej09b0244-0300 16.3.3.2 master transmit operation in master transmit mode, the master device outputs th e transmit clock and data, and the slave device returns an acknowledge signal. figures 16.33 and 16.34 show the operatin g timing in master transmit mode (i 2 c bus interface mode). the transmit procedure and operation in ma ster transmit mode are as follows. (1) set the stop bit in the icsr register to 0 to rese t it. then set the ice bit in the iccr1 register to 1 (transfer operation enabled). then set bits wait a nd mls in the icmr register and set bits cks0 to cks3 in the iccr1 register (initial setting). (2) read the bbsy bit in the iccr2 regi ster to confirm that the bus is free. set bits trs and mst in the iccr1 register to master transmit mode. the start conditi on is generated by writing 1 to the bbsy bit and 0 to the scp bit by the mov instruction. (3) after confirming that the tdre bit in the icsr regi ster is set to 1 (data is transferred from registers icdrt to icdrs), write transmit data to the icdr t register (data in which a slave address and r/w are indicated in the 1st byte). at this time, the tdre bit is automatically set to 0, data is transferred from registers icdrt to icdrs, an d the tdre bit is set to 1 again. (4) when transmission of 1 byte of data is completed while the tdre bit is set to 1, the tend bit in the icsr register is set to 1 at the rise of the 9th transmit clock pulse. read the ackbr bit in the icier register, and confirm that the slave is selected. write the 2nd byte of data to the icdrt register. since the slave device is not acknowledged when the ackbr bit is set to 1, generate the stop condition. the stop condition is generated by the writing 0 to the bbsy bit and 0 to the scp bit by the mov instruction. the scl signal is held ?l? until data is available and the stop condition is generated. (5) write the transmit data after the 2nd byte to the icdrt register every time the tdre bit is set to 1. (6) when writing the number of bytes to be transmitte d to the icdrt register, wait until the tend bit is set to 1 while the tdre bit is set to 1. or wait for nack (the nackf bit in the icsr register is set to 1) from the receive device while the acke bit in the icier register is set to 1 (when the receive acknowledge bit is set to 1, transf er is halted). then generate the stop condition before setting bits tend and nackf to 0. (7) when the stop bit in the icsr register is set to 1, return to slave receive mode. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 349 of 485 rej09b0244-0300 figure 16.33 operating timing in master transmit mode (i 2 c bus interface mode) (1) figure 16.34 operating timing in master transmit mode (i 2 c bus interface mode) (2) sda (master output) scl (master output) 12 89 67 45 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 12 sda (slave output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrt register icdrs register r/w slave address address + r/w processing by program (2) instruction of start condition generation (3) data write to icdrt register (1st byte) a (4) data write to icdrt register (2nd byte) (5) data write to icdrt register (3rd byte) data 2 address + r/w data 1 data 1 sda (master output) scl (master output) 12 89 67 45 3 b7 b6 b5 b4 b3 b2 b1 b0 sda (slave output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrt register icdrs register data n processing by program (6) generate stop condition and set tend bit to 0 (3) data write to icdrt register a/a (7) set to slave receive mode 9 a data n free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 350 of 485 rej09b0244-0300 16.3.3.3 master receive operation in master receive mode, the master device outputs the r eceive clock, receives data from the slave device, and returns an acknowledge signal. figures 16.35 an d 16.36 show the operating timi ng in master receive mode (i 2 c bus interface mode). the receive procedure and operation in master receive mode are shown below. (1) after setting the tend bit in th e icsr register to 0, switch fr om master transmit mode to master receive mode by setting the trs bit in the iccr1 register to 0. also, set the tdre bit in the icsr register to 0. (2) when performing the dummy read of the icdrr regi ster and starting the recei ve operation, the receive clock is output in synchronization with the internal clock and data is received. the master device outputs the level set by the ackbt bit in the icier register to the sda pin at the rising edge of the 9th clock cycle of the receive clock. (3) the 1-frame data receive is completed and the rdrf bit in the icsr register is set to 1 at the rise of the 9th clock cycle. at this time, when reading the ic drr register, the received data can be read and the rdrf bit is set to 0 simultaneously. (4) continuous receive operation is enabled by reading the icdrr register every time the rdrf bit is set to 1. if the 8th clock cycle falls after the icdrr regi ster is read by another process while the rdrf bit is set to 1, the scl signal is fixed ?l? until the icdrr register is read. (5) if the next frame is the last receive frame and the rcvd bit in the iccr1 regist er is set to 1 (disables the next receive operation) before reading the ic drr register, stop condition generation is enabled after the next receive operation. (6) when the rdrf bit is set to 1 at the rise of the 9th clock cycle of the receive clock, generate the stop condition. (7) when the stop bit in the icsr register is set to 1, read the icdrr register and set the rcvd bit to 0 (maintain the following receive operation). (8) return to slave receive mode. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 351 of 485 rej09b0244-0300 figure 16.35 operating timing in master receive mode (i 2 c bus interface mode) (1) sda (master output) scl (master output) 1 8 967 45 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 12 sda (slave output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrr register icdrs register data 1 processing by program (1) set tend and trs bits to 0 before setting tdre bits to 0 a (2) read icdrr register data 1 9 trs bit in iccr1 register 1 0 rdrf bit in icsr register 1 0 a (3) read icdrr register master transmit mode master receive mode free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 352 of 485 rej09b0244-0300 figure 16.36 operating timing in master receive mode (i 2 c bus interface mode) (2) sda (master output) scl (master output) 12 89 67 45 3 b7 b6 b5 b4 b3 b2 b1 b0 sda (slave output) 1 0 rcvd bit in iccr1 register 1 0 icdrr register icdrs register data n-1 processing by program (6) stop condition generation a/a (8) set to slave receive mode 9 a data n rdrf bit in icsr register data n data n-1 (5) set rcvd bit to 1 before reading icdrr register (7) read icdrr register before setting rcvd bit to 0 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 353 of 485 rej09b0244-0300 16.3.3.4 slave transmit operation in slave transmit mode, the slave device outputs the tran smit data while the master device outputs the receive clock and returns an acknowledge signal. figures 16.37 and 16.38 show the operating timing in slave transmit mode (i 2 c bus interface mode). the transmit procedure and operation in slave transmit mode are as follows. (1) set the ice bit in the iccr1 register to 1 (trans fer operation enabled). set bits wait and mls in the icmr register and bits cks0 to cks3 in the iccr1 register (initial setting). set bits trs and mst in the iccr1 register to 0 and wait until the slave address matches in slave receive mode. (2) when the slave address matches at the 1st frame after detecting the start condition, the slave device outputs the level set by the ackbt bit in the icier register to the sda pin at the rise of the 9th clock cycle. at this time, if the 8th bit of data (r/w ) is 1, bits trs and tdre in the icsr register are set to 1, and the mode is switched to slave transmit mode automatically. continuous transmission is enabled by writing transmit data to the icdrt register every time the tdre bit is set to 1. (3) when the tdre bit in the icdrt register is set to 1 after writing the last transmit data to the icdrt register, wait until the tend bit in the icsr register is set to 1 while the tdre bit is set to 1. when the tend bit is set to 1, set the tend bit to 0. (4) the scl signal is released by setting the trs bit to 0 and performing a dummy read of the icdrr register to end the process. (5) set the tdre bit to 0. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 354 of 485 rej09b0244-0300 figure 16.37 operating timing in slave transmit mode (i 2 c bus interface mode) (1) sda (master output) scl (master output) 1 8 967 45 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 12 sda (slave output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrr register icdrs register data 1 processing by program a data 2 9 trs bit in iccr1 register 1 0 a slave transmit mode slave receive mode scl (slave output) icdrt register data 1 (1) data write to icdrt register (data 1) (2) data write to icdrt register (data 2) data 2 (2) data write to icdrt register (data 3) data 3 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 355 of 485 rej09b0244-0300 figure 16.38 operating timing in slave transmit mode (i 2 c bus interface mode) (2) sda (slave output) scl (master output) 12 89 67 45 3 b7 b6 b5 b4 b3 b2 b1 b0 sda (master output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrt register icdrs register data n processing by program (3) set the tend bit to 0 a 9 a data n slave receive mode slave transmit mode trs bit in iccr1 register 1 0 icdrr register (4) dummy read of icdrr register after setting trs bit to 0 (5) set tdre bit to 0 scl (slave output) free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 356 of 485 rej09b0244-0300 16.3.3.5 slave receive operation in slave receive mode, the master de vice outputs the transmit clock and data, and the slave device returns an acknowledge signal. figures 16.39 an d 16.40 show the operating timing in slave receive mode (i 2 c bus interface mode). the receive procedure and operation in slave receive mode are as follows. (1) set the ice bit in the iccr1 register to 1 (trans fer operation enabled). set bits wait and mls in the icmr register and bits cks0 to cks3 in the iccr1 register (initial setting). set bits trs and mst in the iccr1 register to 0 and wait until the slave address matches in slave receive mode. (2) when the slave address matches at the 1st frame after detecting the start condition, the slave device outputs the level set in the ackbt bit in the icier re gister to the sda pin at the rise of the 9th clock cycle. since the rdrf bit in the icsr register is set to 1 simultaneously, perform the dummy read (the read data is unnecessary because it indicates the slave address and r/w ). (3) read the icdrr register every time the rdrf bit is set to 1. if the 8th cl ock cycle falls while the rdrf bit is set to 1, the scl signal is fixed ?l? until the icdrr register is read. the setting change of the acknowledge signal returned to the master devi ce before reading the icdrr register takes affect from the following transfer frame. (4) reading the last byte is performed by r eading the icdrr register in like manner. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 357 of 485 rej09b0244-0300 figure 16.39 operating timing in slave receive mode (i 2 c bus interface mode) (1) figure 16.40 operating timing in slave receive mode (i 2 c bus interface mode) (2) sda (master output) scl (master output) 1 8 967 45 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 12 sda (slave output) icdrr register icdrs register data 1 processing by program a (2) dummy read of icdrr register data 1 9 rdrf bit in icsr register 1 0 a (2) read icdrr register scl (slave output) data 2 sda (master output) scl (master output) 8 967 45 3 b7 b6 b5 b4 b3 b2 b1 b0 12 sda (slave output) icdrr register icdrs register data 1 processing by program a (3) read icdrr register data 1 9 rdrf bit in icsr register 1 0 a (4) read icdrr register scl (slave output) data 2 (3) set ackbt bit to 1 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 358 of 485 rej09b0244-0300 16.3.4 clock synchronous serial mode 16.3.4.1 clock synchronous serial format set the fs bit in the sar register to 1 to use the clock synchronous serial format for communication. figure 16.41 shows the transfer format of clock synchronous serial format. when the mst bit in the iccr1 register is set to 1, the transfer clock is output from the scl pin, and when the mst bit is set to 0, the external clock is input. the transfer data is output between su ccessive falling edges of the scl clock, and data is determined at the rising edge of the scl clock. msb-first or lsb-first can be selected as the order of the data transfer by setting the mls bit in the icmr register. the sda output leve l can be changed by the sdao bit in the iccr2 register during transfer standby. figure 16.41 transfer format of clock synchronous serial format scl b0 sda b1 b2 b3 b4 b5 b6 b7 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 359 of 485 rej09b0244-0300 16.3.4.2 transmit operation in transmit mode, transmit data is output from the sda pin in synchronization with the falling edge of the transfer clock. the transfer clock is output when the mst bit in the iccr1 register is set to 1 and input when the mst bit is set to 0. figure 16.42 shows the operating timing in tr ansmit mode (clock synchronous serial mode). the transmit procedure and operation in transmit mode are as follows. (1) set the ice bit in the iccr1 register to 1 (transfe r operation enabled). set bits cks0 to cks3 in the iccr1 register and set the mst bit (initial setting). (2) the tdre bit in the icsr register is set to 1 by selecting transmit mode after setting the trs bit in the iccr1 register to 1. (3) data is transferred from registers icdrt to ic drs and the tdre bit is automatically set to 1 by writing transmit data to the icdrt register after c onfirming that the tdre bit is set to 1. continuous transmission is enabled by writing data to the icdrt register every time the tdre bit is set to 1. when switching from transmit to receive mode, set the trs bit to 0 while the tdre bit is set to 1. figure 16.42 operating timing in transmit mode (clock synchronous serial mode) sda (output) scl 8 7 b7 b1 b0 12 icdrt register icdrs register processing by program 17 81 b6 b7 b0 b6 b0 tdre bit in icsr register 1 0 trs bit in iccr1 register 1 0 data 1 data 2 data 3 data 1 data 2 data 3 (2) set trs bit to 1 (3) data write to icdrt register (3) data write to icdrt register (3) data write to icdrt register (3) data write to icdrt register free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 360 of 485 rej09b0244-0300 16.3.4.3 receive operation in receive mode, data is latched at the rising edge of the transfer clock. the transf er clock is output when the mst bit in the iccr1 register is set to 1 and input when the mst bit is set to 0. figure 16.43 shows the operating timing in re ceive mode (clock synchronous serial mode). the receive procedure and operation in receive mode are as follows. (1) set the ice bit in the iccr1 register to 1 (transfe r operation enabled). set bits cks0 to cks3 in the iccr1 register and set the mst bit (initial setting). (2) the output of the receive clock starts when the mst bit is set to 1 while the transfer clock is being output. (3) data is transferred from register s icdrs to icdrr and the rdrf bit in the icsr register is set to 1, when the receive operation is completed. since the next byte of data is enabled when the mst bit is set to 1, the clock is output continuously. continuous reception is enabled by reading the icdrr register every time the rdrf bit is set to 1. an overrun is de tected at the rise of the 8th clock cycle while the rdrf bit is set to 1, and th e al bit in the icsr register is set to 1. at this time, the last receive data is retained in the icdrr register. (4) when the mst bit is set to 1, set the rcvd bit in the iccr1 register to 1 (disables the next receive operation) and read the icdrr regi ster. the scl signal is fixed ?h ? after reception of the following byte of data is completed. figure 16.43 operating timing in receive mode (clock synchronous serial mode) sda (input) scl 8 7 b7 b1 b0 12 icdrr register icdrs register processing by program 17 81 b6 b7 b0 b6 b0 rdrf bit in icsr register 1 0 mst bit in iccr1 register 1 0 data 1 data 2 (2) set mst bit to 1 (when transfer clock is output) (3) read icdrr register 2 trs bit in iccr1 register 1 0 data 2 data 3 data 1 (3) read icdrr register free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 361 of 485 rej09b0244-0300 16.3.5 noise canceller the states of pins scl and sda ar e routed through the noise canceller before being latched internally. figure 16.44 shows a block diagram of noise canceller. the noise canceller consists of two cascaded latch and ma tch detector circuits. when the scl pin input signal (or sda pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next circuit. when they do not match, the former value is retained. figure 16.44 block diagram of noise canceller c dq latch c dq latch match detection circuit scl or sda input signal internal scl or sda signal f1 (sampling clock) period of f1 f1 (sampling clock) free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 362 of 485 rej09b0244-0300 16.3.6 bit synchronization circuit when setting the i 2 c bus interface to master mode , the high-level period may b ecome shorter in the following two cases: ? if the scl signal is driven l level by a slave device ? if the rise speed of the scl signal is reduced by a load (load capacity or pull-up resistor) on the scl line. therefore, the scl signal is monitored and communication is synchronized bit by bit. figure 16.45 shows the timing of bit synchronization ci rcuit, and table 16.8 lists the time between changing scl signal from ?l? output to high-impedance and monitoring of scl signal. figure 16.45 timing of bit synchronization circuit 1tcyc = 1/f1(s) table 16.8 time between changing scl signal from ?l? output to high-impedance and monitoring of scl signal iccr1 register time for monitoring scl cks3 cks2 0 0 7.5tcyc 1 19.5tcyc 1017.5tcyc 1 41.5tcyc vih reference clock of scl monitor timing scl internal scl free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 363 of 485 rej09b0244-0300 16.3.7 examples of register setting figures 16.46 to 16.49 show examples of register setting when using i 2 c bus interface. figure 16.46 example of register setting in master transmit mode (i 2 c bus interface mode) start initial setting read bbsy bit in iccr2 register end bbsy = 0 ? write transmit data to icdrt register transmit mode ? master receive mode tend = 1 ? no yes yes no (1) judge the state of the scl and sda lines (2) set to master transmit mode (3) generate the start condition (4) set the transmit data of the 1st byte (slave address + r/w) (5) wait for 1 byte to be transmitted (6) judge the ackbr bit from the specified slave device (7) set the transmit data after 2nd byte (except the last byte) (8) wait until the icrdt register is empty (9) set the transmit data of the last byte (10) wait for end of transmission of the last byte (11) set the tend bit to 0 (12) set the stop bit to 0 (13) generate the stop condition (14) wait until the stop condition is generated (15) set to slave receive mode set the tdre bit to 0 iccr1 register trs bit 1 mst bit 1 iccr2 register scp bit 0 bbsy bit 1 read tend bit in icsr register no read ackbr bit in icier register yes ackbr = 0 ? write transmit data to icdrt register tdre = 1 ? read tdre bit in icsr register last byte ? write transmit data to icdrt register tend = 1 ? read tend bit in icsr register icsr register tend bit 0 icsr register stop bit 0 iccr2 register scp bit 0 bbsy bit 0 read stop bit in icsr register stop = 1 ? iccr1 register trs bit 0 mst bit 0 icsr register tdre bit 0 no yes no yes no yes no yes no yes (1) (2) (3) (4) (5) (6) (7) (8) (12) (10) (13) (14) (11) (9) (15) ? set the stop bit in the icsr register to 0 ? set the iicsel bit in the pmr register to 1 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 364 of 485 rej09b0244-0300 figure 16.47 example of register setting in master receive mode (i 2 c bus interface mode) end rdrf = 1 ? master receive mode no yes (1) set the tend bit to 0 and set to master receive mode. set the tdre bit to 0 (1,2) (2) set the ackbt bit to the transmit device (1) (3) dummy read the icdrr register (1) (4) wait for 1 byte to be received (5) judge (last receive - 1) (6) read the receive data (7) set the ackbt bit of the last byte and set to disable continuous receive operation (rcvd = 1) (2) (8) read the receive data of (last byte - 1) (9) wait until the last byte is received (10) set the stop bit to 0 (11) generate the stop condition (12) wait until the stop condition is generated (13) read the receive data of the last byte (14) set the rcvd bit to 0 (15) set to slave receive mode iccr1 register trs bit 0 dummy read in icdrr register read rdrf bit in icsr register last receive - 1 ? icsr register tend bit 0 icsr register stop bit 0 iccr2 register scp bit 0 bbsy bit 0 read stop bit in icsr register stop = 1 ? icsr register tdre bit 0 no (1) (2) (3) (4) (5) (6) (7) (8) (12) (10) (13) (14) (11) (9) (15) icier register ackbt bit 0 no yes read icdrr register icier register ackbt bit 1 iccr1 register rcvd bit 1 read icdrr register read rdrf bit in icsr register rdrf = 1 ? read icdrr register iccr1 register rcvd bit 0 iccr1 register mst bit 0 no yes yes notes: 1. do not generate the interrupt while processing steps (1) to (3). 2. when receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7). processing step (8) is dummy read of the icdrr register. free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 365 of 485 rej09b0244-0300 figure 16.48 example of register setting in slave transmit mode (i 2 c bus interface mode) end write transmit data to icdrt register slave transmit mode no yes (1) set the aas bit to 0 (2) set the transmit data (except the last byte) (3) wait until the icrdt register is empty (4) set the transmit data of the last byte (5) wait until the last byte is transmitted (6) set the tend bit to 0 (7) set to slave receive mode (8) dummy read the icdrr register to release the scl signal (9) set the tdre bit to 0 tdre = 1 ? read tdre bit in icsr register last byte ? write transmit data to icdrt register tend = 1 ? read tend bit in icsr register icsr register tend bit 0 icsr register aas bit 0 iccr1 register trs bit 0 icsr register tdre bit 0 no yes no yes (1) (2) (3) (4) (5) (6) (7) (8) (9) dummy read in icdrr register free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 366 of 485 rej09b0244-0300 figure 16.49 example of register se tting in slave receive mode (i 2 c bus interface mode) end rdrf = 1 ? slave receive mode no yes (1) set the aas bit to 0 (1) (2) set the ackbt bit to the transmit device (3) dummy read the icdrr register (4) wait until 1 byte is received (5) judge (last receive - 1) (6) read the receive data (7) set the ackbt bit of the last byte (1) (8) read the receive data of (last byte - 1) (9) wait until the last byte is received (10) read the receive data of the last byte dummy read icdrr register read rdrf bit in icsr register last receive - 1 ? (1) (2) (3) (4) (5) (6) (7) (8) (10) (9) icier register ackbt bit 0 no yes read icdrr register icier register ackbt bit 1 read icdrr register read rdrf bit in icsr register rdrf = 1 ? read icdrr register no yes note: 1. when receiving 1 byte, skip steps (2) to (6) after (1) and jump to processing step (7). processing step (8) is dummy read of the icdrr register. icsr register aas bit 0 free datasheet http:///
r8c/24 group, r8c/25 group 16. cl ock synchronous serial interface rev.3.00 feb 29, 2008 page 367 of 485 rej09b0244-0300 16.3.8 notes on i 2 c bus interface set the iicsel bit in the pmr register to 1 (select i 2 c bus interface function) to use the i 2 c bus interface. 16.3.8.1 multimaster operation the following actions must be performed to use the i 2 c bus interface in multimaster operation. ? transfer rate set the transfer rate by 1/1.8 or faster than the fastes t rate of the other masters. for example, if the fastest transfer rate of the other masters is set to 400 kbps, the i 2 c-bus transfer rate in this mcu should be set to 223 kbps (= 400/1.18) or more. ? bits mst and trs in the iccr1 register setting (a) use the mov instruction to set bits mst and trs. (b) when arbitration is lost, confirm the contents of b its mst and trs. if the contents are other than the mst bit set to 0 and the trs bit set to 0 (slave recei ve mode), set the mst bit to 0 and the trs bit to 0 again. 16.3.8.2 master receive mode either of the following actions must be performed to use the i 2 c bus interface in ma ster receive mode. (a) in master receive mode while the rdrf bit in the icsr register is set to 1, read the icdrr register before the rising edge of the 8th clock. (b) in master receive mode, set the rcvd bit in th e iccr1 register to 1 (disables the next receive operation) to perform 1-byte communications. free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 368 of 485 rej09b0244-0300 17. hardware lin the hardware lin performs lin communication in cooperation with timer ra and uart0. 17.1 features the hardware lin has the features listed below. figure 17.1 shows a block diagram of hardware lin. master mode ? generates synch break ? detects bus collision slave mode ? detects synch break ? measures synch field ? controls synch break and synch field signal inputs to uart0 ? detects bus collision note: 1. the wakeup function is detected by int1. figure 17.1 block diagram of hardware lin timer ra uart0 interrupt control circuit bus collision detection circuit synch field control circuit rxd0 input control circuit rxd0 pin txd0 pin lstart bit sbe bit line bit timer ra interrupt tiosel = 0 hardware lin tiosel = 1 rxd data timer ra underflow signal bcie, sbie, and sfie bits uart0 transfer clock uart0 te bit timer ra output pulse uart0 txd data mst bit line, mst, sbe, lstart, bcie, sbie, sfie: bits in lincr register tiosel: bit in traioc register te: bit in u0c1 register free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 369 of 485 rej09b0244-0300 17.2 input/output pins the pin configuration of the hardware lin is listed in table 17.1. table 17.1 pin configuration name abbreviation input/output function receive data input rxd0 input receive data input pin of the hardware lin transmit data output txd0 output transmit data output pin of the hardware lin free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 370 of 485 rej09b0244-0300 17.3 register configuration the hardware lin contains the registers listed below. these registers are detailed in figures 17.2 and 17.3. ? lin control register (lincr) ? lin status register (linst) figure 17.2 lincr register lin control register symbol address after reset lincr 0106h 00h bit symbol bit name function rw notes: 1. 2. 3. lin operation start bit 0 : causes lin to stop 1 : causes lin to start operating (3) rw lin operation mode setting bit (2) 0 : slave mode (synch break detection circuit actuated) 1 : master mode (timer ra output or?ed w ith txd0) 0 : disables synch field measurement- completed interrupt 1 : enables synch field measurement- completed interrupt sfie synch field measurement- completed interrupt enable bit b7 b6 b5 b4 b3 b2 b1 b0 0 : rxd0 input enabled 1 : rxd0 input disabled when this bit is set to 1, timer ra input is enabled and rxd0 input is disabled. when read, the content is 0. rw rw ro rw rw rxd0 input status flag synch break detection start bit(1) synch break detection interrupt enable bit bus collision detection interrupt enable bit 0 : disables synch break detection interrupt 1 : enables synch break detection interrupt 0 : disables bus collision detection interrupt 1 : enables bus co llision detection interrupt sbie bcie rxdsf lstart inputs to timer ra and uart0 are prohibited immediately after this bit is set to 1. (refer to figure 17.5 example of header field transm ission flow chart (1) and figure 17.9 exam ple of header field reception flow chart (2) .) before changing lin operation modes, temporarily stop the lin operation (line bit = 0). sbe after setting the lstart bit, confirm that the rxdsf flag is set to 1 before synch break input starts. 0 : unmasked after synch break is detected 1 : unmasked after synch field measurement is completed rw rxd0 input unmasking timing select bit (effective only in slave mode) mst rw line free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 371 of 485 rej09b0244-0300 figure 17.3 linst register lin status register symbol address after reset linst 0107h 00h bit symbol bit name function rw ? (b7-b6) ? 1 show s synch field measurement completed. sfdct synch field measurement- completed flag ro rw rw rw ro b3 b2 b1 b0 b7 b6 b5 b4 ro sbdct bit clear bit bcdct bit clear bit 1 show s synch break detected or synch break generation completed. 1 show s bus collision detected when this bit is set to 1, the sfdct bit is set to 0. when read, the content is 0. when this bit is set to 1, the sbdct bit is set to 0. when read, the content is 0. nothing is assigned. if necessary, set to 0. when read, the content is 0. b2clr sbdct bcdct b0clr b1clr when this bit is set to 1, the bcdct bit is set to 0. when read, the content is 0. synch break detection flag bus collision detection f lag sfdct bit clear bit free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 372 of 485 rej09b0244-0300 17.4 functional description 17.4.1 master mode figure 17.4 shows typical operation of the hardware lin when transmitting a header field in master mode. figures 17.5 and 17.6 show a flowchart of the procedure fo r transmitting a header field. when transmitting a header field, the ha rdware lin operates as described below. (1) when the tstart bit in the tracr register for timer ra is set by writing 1 in software, the hardware lin outputs ?l? level from the txd0 pin for the peri od that is set in registers trapre and tra for timer ra. (2) when timer ra underflo ws upon reaching the terminal count, th e hardware lin reverses the output of the txd0 pin and sets the sbdct flag in the linst re gister to 1. furthermore, if the sbie bit in the lincr register is set to 1, it generates a timer ra interrupt. (3) the hardware lin transmits 55h via uart0. (4) the hardware lin transmits an id field via uart0 after it finishes sending 55h. (5) the hardware lin performs communication for a re sponse field after it finish es sending the id field. figure 17.4 typical operation when sending a header field txd0 pin synch break 1 0 sbdct flag in the linst register 1 0 ir bit in the traic register 1 0 synch field identifier (1) (2) (3) (4) (5) set by writing 1 to the b1clr bit in the linst register cleared to 0 upon acceptance of interrupt request or by a program the above applies under the following conditions: line = 1, mst = 1, sbie = 1 free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 373 of 485 rej09b0244-0300 figure 17.5 example of header fi eld transmission flowchart (1) timer ra set to timer mode bits tmod0 to tmod2 in tramr register 000b timer ra set the pulse output level from low to start tedgsel bit in traioc register 1 timer ra set the int1/traio pin to p1_5 tiosel bit in traioc register 1 timer ra set the count source (f1, f2, f8, foco) bits tck0 to tck2 in tramr register timer ra set the synch break width trapre register tra register hardware lin set to master mode mst bit in lincr register 1 hardware lin set the lin operation to start line bit in lincr register 1 hardware lin set the register to enable interrupts (bus collision detection , synch break detection, synch field measurement) bits bcie, sbie, sfie in lincr register hardware lin clear the status flags (bus collision detection , synch break detection, synch field measurement) bits b2clr, b1clr, b0clr in linst register 1 set the count source and registers tra and trapre as suitable for the synch break period. during master mode, the synch field measurement- completed interrupt cannot be used. a for the hardware lin function, set the tiosel bit in the traioc register to 1. uart0 set to transmit/receive mode (transfer data length : 8 bits, internal clock, 1 stop bit, parity disabled) u0mr register uart0 set the brg count source (f1, f8, f32) u0c0clk0 to 1 bit uart0 set the bit rate u0brg register hardware lin set the lin operation to stop lincr register line bit 0 set the brg count source and u0brg register as appropriate for the bit rate. free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 374 of 485 rej09b0244-0300 figure 17.6 example of header fi eld transmission flowchart (2) timer ra set the timer to start counting tstart bit in tracr register 1 timer ra read the count status flag tcstf flag in tracr register hardware lin read the synch break detection flag sbdct flag in linst register timer ra set the timer to stop counting tstart bit in tracr register 0 timer ra read the count status flag tcstf flag in tracr register uart0 communication via uart0 te bit in u0c1 register 1 u0tb register 0055h the timer ra interrupt may be used to terminate generation of synch break. one to two cycles of the cpu clock are required after synch break generation completes before the sbdct flag is set to 1. transmit the id field. a tcstf = 1 ? sbdct = 1 ? yes tcstf = 0 ? yes uart0 communication via uart0 u0tb register id field no yes no no if registers trapre and tra for timer ra do not need to be read or the register settings do not need to be changed after writing 0 to the tstart bit, the procedure for reading tcstf flag = 0 can be omitted. zero to one cycle of the timer ra count source is required after timer ra stops counting before the tcstf flag is set to 0. transmit the synch field. after timer ra synch break is generated, the timer should be made to stop counting. if registers trapre and tra for timer ra do not need to be read or the register settings do not need to be changed after writing 1 to the tstart bit, the procedure for reading tcstf flag = 1 can be omitted. zero to one cycle of the timer ra count source is required after timer ra starts counting before the tcstf flag is set to 1. timer ra generates synch break. free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 375 of 485 rej09b0244-0300 17.4.2 slave mode figure 17.7 shows typical operation of the hardware lin when receiving a header field in slave mode. figure 17.8 through figure 17.10 show a flowchart for the pro cedure for receiving a header field. when receiving a header field, the hard ware lin operates as described below. (1) synch break detection is enabled by writing 1 to th e lstart bit in the lincr register of the hardware lin. (2) when ?l? level is input for a duration equal to or greater than the period set in timer ra, the hardware lin detects it as synch break. at this time, the sbdct flag in the linst register is set to 1. furthermore, if the sbie bit in the lincr register is set to 1, the hardware lin generates a timer ra interrupt. then it goes to synch field measurement. (3) the hardware lin receives a synch fi eld (55h). at this time, it measur es the period of the start bit and bits 0 to 6 by using timer ra. in this case, it is poss ible to select whether to input the synch field signal to rxd0 of uart0 by setting the sbe bit in the lincr register accordingly. (4) the hardware lin sets the sfdct flag in the linst register to 1 when it fi nishes measuring the synch field. furthermore, if the sfie bit in the lincr regi ster is set to 1, it generates a timer ra interrupt. (5) after it finishes measuring the synch field, calcula te a transfer rate from the count value of timer ra and set to uart0 and registers tr apre and tra of timer ra again. (6) the hardware lin performs comm unication for a response field after it finishes receiving the id field. figure 17.7 typical operation when receiving a header field rxd0 pin synch break 1 0 rxd0 input for uart0 1 0 rxdsf flag in the lincr register 1 0 synch field identifier (2) (3) (5) (6) the above applies under the following conditions: line = 1, mst = 0, sbe = 1, sbie = 1, sfie = 1 (4) (1) sbdct flag in the linst register 1 0 sfdct flag in the linst register 1 0 ir bit in the traic register 1 0 set by writing 1 to the b0clr bit in the linst register cleared to 0 when synch field measurement finishes measure this period set by writing 1 to the b1clr bit in the linst register cleared to 0 upon acceptance of interrupt request or by a program set by writing 1 to the lstart bit in the lincr register free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 376 of 485 rej09b0244-0300 figure 17.8 example of header field reception flowchart (1) set the count source and registers tra and trapre as appropriate for the synch break period. select the timing at which to unmask the rxd0 input for uart0. if the rxd0 input is chosen to be unmasked after detection of synch break, the synch field signal is also input to uart0. a for the hardware lin function, set the tiosel bit in the traioc register to 1. timer ra set to pulse width measurement mode bits tmod0 to tmod2 in the tramr register 011b timer ra set the pulse width measurement level low tedgsel bit in the traioc register 0 timer ra set the int1/traio pin to p1_5 tiosel bit in the traioc register 1 timer ra set the count source (f1, f2, f8, foco) bits tck0 to tck2 in the tramr register timer ra set the synch break width trapre register tra register hardware lin set the lin operation to stop line bit in the lincr register 0 hardware lin set to slave mode mst bit in the lincr register 0 hardware lin set the rxd0 input unmasking timing (after synch break detection, or after synch field measurement) sbe bit in the lincr register hardware lin set the register to enable interrupts (bus collision detection, synch break detection, synch field measurement) bits bcie, sbie, sfie in the lincr register hardware lin set the lin operation to start line bit in the lincr register 1 free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 377 of 485 rej09b0244-0300 figure 17.9 example of header field reception flowchart (2) timer ra set to start a pulse width measurement tstart bit in the tracr register 1 timer ra read the count status flag tcstf flag in the tracr register hardware lin set to start synch break detection lstart bit in the lincr register 1 hardware lin read the rxd0 input status flag rxdsf flag in the lincr register a tcstf = 1 ? yes rxdsf = 1 ? yes no no timer ra waits until the timer starts counting. hardware lin clear the status flags (bus collision detection, synch break detection, synch field measurement) bits b2clr, b1clr, b0clr in the linst register 1 hardware lin read the synch break detection flag sbdct flag in the linst register sbdct = 1 ? yes no b do not apply ?l? level to the rxd pin until the rxdsf flag reads 1 after writing 1 to the lstart bit. this is because the signal applied during this time is input directly to uart0. one to two cycles of the cpu clock and zero to one cycle of the timer ra count source are required after the lstart bit is set to 1 before the rxdsf flag is set to 1. after this, input to timer ra and uart0 is enabled. hardware lin detects a synch break. the interrupt of the timer ra may be used. hardware lin waits until the rxd0 input for uart0 is masked. when synch break is detected, timer ra is reloaded with the initially set count value. even if the duration of the input ?l? level is shorter than the set period, timer ra is reloaded with the initially set count value and waits until the next ?l? level is input. one to two cycles of the cpu clock are required after synch break detection before the sbdct flag is set to 1. when the sbe bit in the lincr register is set to 0 (unmasked after synch break is detected), timer ra can be used in timer mode after the sbdct flag in the linst register is set to 1 and the rxdsf flag is set to 0. zero to one cycle of the timer ra count source is required after timer ra starts counting before the tcstf flag is set to 1. free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 378 of 485 rej09b0244-0300 figure 17.10 example of header field reception flowchart (3) hardware lin read the synch field measurement- completed flag sfdct flag in the linst register uart0 set the uart0 communication rate u0brg register communication via uart0 (the sbdct flag is set when the timer ra counter underflows upon reaching the terminal count.) b sfdct = 1 ? yes uart0 communication via uart0 clock asynchronous serial interface (uart) mode transmit id field no hardware lin measures the synch field. the interrupt of timer ra may be used (the sbdct flag is set when the timer ra counter underflows upon reaching the terminal count). when the sbe bit in the lincr register is set to 1 (unmasked after synch field measurement is completed), timer ra may be used in timer mode after the sfdct bit in the linst register is set to 1. set a communication rate based on the synch field measurement result. yes timer ra set the synch break width again trapre register tra register free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 379 of 485 rej09b0244-0300 17.4.3 bus collision detection function the bus collision detection function can be used when uart0 is enabled for transmission (te bit in the u0c1 register = 1). figure 17.11 shows the typical operatio n when a bus collision is detected. figure 17.11 typical operation when a bus collision is detected txd0 pin 1 0 rxd0 pin 1 0 transfer clock 1 0 line bit in the lincr register 1 0 te bit in the u0c1 register 1 0 bcdct flag in the linst register 1 0 ir bit in the traic register 1 0 cleared to 0 upon acceptance of interrupt request or by a program set by writing 1 to the b2clr bit in the linst register set to 1 by a program set to 1 by a program free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 380 of 485 rej09b0244-0300 17.4.4 hardware li n end processing figure 17.12 shows an example of hardware lin communication completion flowchart. use the following timing for hardware lin end processing: ? if the hardware bus collision detection function is used perform hardware lin end processing af ter checksum transmission completes. ? if the bus collision detection function is not used perform hardware lin end processing after head er field transmission and reception complete. figure 17.12 example of hardware lin communication completion flowchart hardware lin clear the status flags (bus collision detection, synch break detection, synch field measurement) bits b2clr, b1clr, b0clr in the linst register 1 timer ra read the count status flag tcstf flag in tracr register uart0 complete transmission via uart0 when the bus collision detection function is not used, end processing for the uart0 transmission is not required. tcstf = 0 ? yes no set the timer to stop counting. zero to one cycle of the timer ra count source is required after timer ra starts counting before the tcstf flag is set to 1. after clearing hardware lin status flag, stop the hardware lin operation. timer ra set the timer to stop counting tstart bit in tracr register 0 hardware lin set the lin operation to stop line bit in the lincr register 0 free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 381 of 485 rej09b0244-0300 17.5 interrupt requests there are four interrupt requests th at are generated by the hardware li n: synch break detection, synch break generation completed, synch field measurement, and bus collision detection. these interrupts are shared with timer ra. table 17.2 lists the interrupt requests of hardware lin. table 17.2 interrupt requests of hardware lin interrupt request status flag cause of interrupt synch break detection sbdct generated when timer ra has underflowed after measuring the ?l? level duration of rxd0 input, or when a ?l? level is input for a duration longer than the synch break period during communication. synch break generation completed generated when ?l? level output to txd0 for the duration set by timer ra completes. synch field measurement sfdct generated when measurement for 6 bits of the synch field by timer ra is completed. bus collision detection bcdct ge nerated when the rxd0 input and txd0 output values differed at data latch timing while uart0 is enabled for transmission. free datasheet http:///
r8c/24 group, r8c/25 group 17. hardware lin rev.3.00 feb 29, 2008 page 382 of 485 rej09b0244-0300 17.6 notes on hardware lin for the time-out processing of the head er and response fields, use another timer to measure the duration of time with a synch break detection interrupt as the starting point. free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 383 of 485 rej09b0244-0300 18. a/d converter the a/d converter consists of one 10- bit successive approximation a/d converter circuit with a capacitive coupling amplifier. the analog input shares pins p0_0 to p0_7, and p1_0 to p1_3. therefore, when us ing these pins, ensure that the corresponding port direction bits are set to 0 (input mode). when not using the a/d converter, set the vcut bit in the adcon1 register to 0 (vref unconnected) so that no current will flow from the vref pin into the resistor ladder. this helps to reduce the power consumption of the chip. the result of a/d conversion is stored in the ad register. table 18.1 lists the performance of a/d converter. figure 18.1 shows a block diagram of a/d converter. figures 18.2 and 18.3 show the a/d converter-related registers. notes: 1. the analog input voltage does not depend on use of a sample and hold function. when the analog input voltage is over the reference voltage, the a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. 2. when 2.7 v avcc 5.5 v, the frequency of ad must be 10 mhz or below. when 2.2 v avcc < 2.7 v, the frequency of ad must be 5 mhz or below. without a sample and hold function, the ad frequency should be 250 khz or above. with a sample and hold function, the ad frequency should be 1 mhz or above. 3. in repeat mode, only 8-bit mode can be used. table 18.1 performance of a/d converter item performance a/d conversion method successive approximat ion (with capacitive coupling amplifier) analog input voltage (1) 0 v to avcc operating clock ad (2) 4.2 v avcc 5.5 v f1, f2, f4, foco-f 2.2 v avcc < 4.2 v f2, f4, foco-f resolution 8 bits or 10 bits selectable absolute accuracy avcc = vref = 5 v, ad = 10 mhz ? 8-bit resolution 2 lsb ? 10-bit resolution 3 lsb avcc = vref = 3.3 v, ad = 10 mhz ? 8-bit resolution 2 lsb ? 10-bit resolution 5 lsb avcc = vref = 2.2 v, ad = 5 mhz ? 8-bit resolution 2 lsb ? 10-bit resolution 5 lsb operating mode one-shot and repeat (3) analog input pin 12 pins (an0 to an11) a/d conversion start condition ? software trigger set the adst bit in the adcon0 regi ster to 1 (a/d conversion starts) ?capture timer rd interrupt request is generated while the adst bit is set to 1 conversion rate per pin ? without sample and hold function 8-bit resolution: 49 ad cycles, 10-bit resolution: 59 ad cycles ? with sample and hold function 8-bit resolution: 28 ad cycles, 10-bit resolution: 33 ad cycles free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 384 of 485 rej09b0244-0300 figure 18.1 block diagram of a/d converter comparator avss data bus resistor ladder vcut = 0 vcut = 1 vref successive conversion register ad register adcon0 vcom vin p1_0/an8 p1_1/an9 p1_2/an10 p1_3/an11 adgsel0 = 1 ch0 to ch2, adgsel0, cks0: bits in adcon0 register cks1, vcut: bits in adcon1 register adgsel0 = 0 adcap = 1 software trigger timer rd interrupt request adcap = 0 trigger p0_7/an0 ch2 to ch0 = 000b p0_6/an1 p0_5/an2 p0_4/an3 p0_3/an4 p0_2/an5 p0_1/an6 p0_0/an7 decoder cks0 = 1 cks1 = 1 cks1 = 0 ad a/d conversion rate selection cks0 = 0 f2 f4 foco-f f1 cks0 = 1 cks0 = 0 ch2 to ch0 = 001b ch2 to ch0 = 010b ch2 to ch0 = 011b ch2 to ch0 = 100b ch2 to ch0 = 101b ch2 to ch0 = 110b ch2 to ch0 = 111b ch2 to ch0 = 100b ch2 to ch0 = 101b ch2 to ch0 = 110b ch2 to ch0 = 111b free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 385 of 485 rej09b0244-0300 figure 18.2 adcon0 register a/d control register 0 (1) symbol address after reset adcon0 00d6h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. adgsel0 = 0 adgsel0 = 1 an0 an1 an2 an3 an4 an8 an5 an9 an6 an10 an7 an11 100b 101b 110b 111b ch2 to ch0 000b do not set. 001b 010b 011b set ?ad frequency to 10 mhz or below . the analog input pin can be selected according to a combination of bits ch0 to ch2 and the adgsel0 bit. cks0 frequency select bit 0 [when cks1 in adcon1 register = 0] 0 : selects f4 1 : selects f2 [when cks1 in adcon1 register = 1] 0 : selects f1 (3) 1 : selects foco-f rw if the adcon0 register is rew ritten during a/d conversion, the conversion result is undefined. when changing a/d operating mode, set the analog input pin again. adst a/d conversion start flag 0 : stops a/d conversion 1 : starts a/d conversion rw adcap a/d conversion automatic start bit 0 : starts at softw are trigger (adst bit) 1 : starts at timer rd (complementary pwm mode) rw 0 : one-shot mode 1 : repeat mode rw rw adgsel0 rw a/d input group select bit (4) 0 : selects port p0 group (an0 to an7) 1 : selects port p1 group (an8 to an11) ch1 rw ch0 ch2 rw analog input pin select bits (note 4) md a/d operating mode select bit (2) b7 b6 b5 b4 b3 b2 b1 b0 free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 386 of 485 rej09b0244-0300 figure 18.3 registers adcon1, adcon2, and ad a/d control register 1 (1) symbol address after reset adcon1 00d7h 00h bit symbol bit name function rw notes: 1. 2. 3. when the vcut bit is set to 1 (connected) from 0 (not connected), w ait for 1 s or more before starting a/d conversion. b3 b2 vcut b1 b0 00 refer to the description of the cks0 bit in the adcon0 register function b7 b6 b5 b4 ? (b2-b0) 00 0 if the adcon1 register is rew ritten during a/d conversion, the conversion result is undefined. cks1 rw rw rw ? (b6-b7) reserved bits vref connect bit (3) 0 : vref not connected 1 : vref connected set the bits bit to 0 (8-bit mode) in repeat mode. reserved bits set to 0. 8/10-bit mode select bit (2) 0 : 8-bit mode 1 : 10-bit mode rw set to 0. frequency select bit 1 bits rw a/d control register 2 (1) symbol address after reset adcon2 00d4h 00h bit symbol bit name function rw note: 1. b0 00 0 b3 b2 b1 reserved bits set to 0. b7 b6 b5 b4 0 : without sample and hold 1 : with sample and hold rw if the adcon2 register is rew ritten during a/d conversion, the conversion result is undefined. smp a/d conversion method select bit nothing is assigned. if necessary, set to 0. when read, the content is 0. ? (b7-b4) ? ? (b3-b1) rw a /d registe r symbol address after reset ad 00c1h-00c0h undefined rw ( b15) b7 ( b8) b0 b0 b7 ro nothing is assigned. if necessary, set to 0. when read, the content is 0. ? 2 high-order bits in a/d conversion result when read, the content is undefined. function ro when bits bit in adcon1 register is set to 1 (10-bit mode). when bits bit in adcon1 register is set to 0 (8-bit mode). 8 low -order bits in a/d conversion result a/d conversion result rw free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 387 of 485 rej09b0244-0300 18.1 one-shot mode in one-shot mode, the input voltage of one selected pin is a/d converted once. table 18.2 lists the one-shot mode specifications. fi gures 18.4 and 18.5 show registers adcon0 and adcon1 in one-shot mode. table 18.2 one-shot mode specifications item specification function the input voltage of one pin select ed by bits ch2 to ch0 and adgsel0 is a/d converted once start condition ? when the adcap bit is set to 0 (software trigger): set the adst bit to 1 (a/d conversion starts) ? when the adcap bit is set to 1 (starts in timer rd (complementary pwm mode): a compare match between registers trd0 and trdgra0 or a trd1 underflow is generated while the adst bit is set to 1 stop condition ? a/d conversion completes (when the adcap bit is set to 0 (software trigger) adst bit is set to 0) ? set the adst bit to 0 interrupt request generation timing a/d conversion completes input pin select one of an0 to an11 reading of a/d conversion result read ad register free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 388 of 485 rej09b0244-0300 figure 18.4 adcon0 register in one-shot mode a/d control register 0 (1) symbol address after reset adcon0 00d6h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. adgsel0 = 0 adgsel0 = 1 an0 an1 an2 an3 an4 an8 an5 an9 an6 an10 an7 an11 set ?ad frequency to 10 mhz or below . the analog input pin can be selected according to a combination of bits ch0 to ch2 and the adgsel0 bit. cks0 frequency select bit 0 [when cks1 in adcon1 register = 0] 0 : selects f4 1 : selects f2 [when cks1 in adcon1 register = 1] 0 : selects f1 (3) 1 : selects foco-f rw if the adcon0 register is rew ritten during a/d conversion, the conversion result is undefined. after changing the a/d operating mode, select the analog input pin again. adst a/d conversion start flag 0 : stops a/d conversion 1 : starts a/d conversion rw adcap a/d conversion automatic start bit 0 : starts at softw are trigger (adst bit) 1 : starts at timer rd (complementary pwm mode) rw 0 : one-shot mode rw rw adgsel0 rw a/d input group select bit (4) 0 : selects port p0 group (an0 to an7) 1 : selects port p1 group (an8 to an11) ch1 rw ch0 ch2 rw analog input pin select bits (note 4) md a/d operating mode select bit (2) b7 b6 b5 b4 0 b3 b2 b1 b0 ch2 to ch0 000b do not set. 001b 010b 011b 100b 101b 110b 111b free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 389 of 485 rej09b0244-0300 figure 18.5 adcon1 register in one-shot mode a/d control register 1 (1) symbol address after reset adcon1 00d7h 00h bit symbol bit name function rw notes: 1. 2. when the vcut bit is set to 1 (connected) from 0 (not connected), w ait for 1 s or more before starting a/d conversion. b3 b2 vcut b1 b0 00 refer to the description of the cks0 bit in the adcon0 register function b7 b6 b5 b4 ? (b2-b0) 001 0 bits rw if the adcon1 register is rew ritten during a/d conversion, the conversion result is undefined. cks1 rw rw rw ? (b6-b7) reserved bits vref connect bit (2) rw set to 0. frequency select bit 1 1 : vref connected reserved bits set to 0. 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 390 of 485 rej09b0244-0300 18.2 repeat mode in repeat mode, the input voltage of one selected pin is a/d converted repeatedly. table 18.3 lists the repeat mode specifications. figures 18.6 and 18.7 show registers adcon0 and adcon1 in repeat mode. table 18.3 repeat mode specifications item specification function the input voltage of one pin select ed by bits ch2 to ch0 and adgsel0 is a/d converted repeatedly start conditions ? when the adcap bit is set to 0 (software trigger): set the adst bit to 1 (a/d conversion starts) ? when the adcap bit is set to 1 (starts in timer rd (complementary pwm mode)): a compare match between registers trd0 and trdgra0 or a trd1 underflow is generated while the adst bit is set to 1 stop condition set the adst bit to 0 interrupt request generation timing not generated input pin select one of an0 to an11 reading of result of a/d converter read ad register free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 391 of 485 rej09b0244-0300 figure 18.6 adcon0 register in repeat mode a/d control register 0 (1) symbol address after reset adcon0 00d6h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. adgsel0 = 0 adgsel0 = 1 an0 an1 an2 an3 an4 an8 an5 an9 an6 an10 an7 an11 b0 1 b3 b2 b1 md a/d operating mode select bit (2) b7 b6 b5 b4 ch2 rw analog input pin select bits (note 4) 1 : repeat mode rw rw adgsel0 rw a/d input group select bit (4) 0 : selects port p0 group (an0 to an7) 1 : selects port p1 group (an8 to an11) ch1 rw ch0 adcap a/d conversion automatic start bit 0 : starts at softw are trigger (adst bit) 1 : starts at timer rd (complementary pwm mode) rw adst a/d conversion start flag 0 : stops a/d conversion 1 : starts a/d conversion rw set ?ad frequency to 10 mhz or below . the analog input pin can be selected according to a combination of bits ch0 to ch2 and the adgsel0 bit. cks0 frequency select bit 0 [when cks1 in adcon1 register = 0] 0 : selects f4 1 : selects f2 [when cks1 in adcon1 register = 1] 0 : selects f1 (3) 1 : do not set. rw if the adcon0 register is rew ritten during a/d conversion, the conversion result is undefined. after changing a/d operation mode, select the analog input pin again. ch2 to ch0 000b do not set. 001b 010b 011b 100b 101b 110b 111b free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 392 of 485 rej09b0244-0300 figure 18.7 adcon1 register in repeat mode a/d control register 1 (1) symbol address after reset adcon1 00d7h 00h bit symbol bit name function rw notes: 1. 2. 3. when the vcut bit is set to 1 (connected) from 0 (not connected), w ait for 1 s or more before starting a/d conversion. b3 b2 vcut b1 b0 0 00 refer to the description of the cks0 bit in the adcon0 register function b7 b6 b5 b4 ? (b2-b0) 001 0 bits rw if the adcon1 register is rew ritten during a/d conversion, the conversion result is undefined. cks1 rw rw rw ? (b6-b7) reserved bits set the bits bit to 0 (8-bit mode) in repeat mode. vref connect bit (3) 1 : vref connected reserved bits set to 0. 8/10-bit mode select bit (2) 0 : 8-bit mode rw set to 0. frequency select bit 1 free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 393 of 485 rej09b0244-0300 18.3 sample and hold when the smp bit in the adcon2 register is set to 1 (sample and hold function enabled), the a/d conversion rate per pin increases. the sample and hold function is available in all operating modes. start a/d conversion after selecting whether the samp le and hold circuit is to be used or not. figure 18.8 shows a timing diagram of a/d conversion. figure 18.8 timing diagram of a/d conversion 18.4 a/d conversion cycles figure 18.9 shows the a/d conversion cycles. figure 18.9 a/d conversion cycles sampling time 4? ad cycles sample and hold disabled conversion time of 1st bit 2nd bit comparison time sampling time 2.5? ad cycles comparison time sampling time 2.5? ad cycles comparison time * repeat until conversion ends sampling time 4? ad cycles sample and hold enabled conversion time of 1st bit 2nd bit comparison time comparison time comparison time * repeat until conversion ends comparison time a/d conversion mode without sample & hold without sample & hold with sample & hold with sample & hold 8 bits 10 bits 8 bits 10 bits conversion time comparison time comparison time end process sampling time end process conversion time at the 1st bit sampling time conversion time at the 2nd bit and the follows 49 ad 4 ad 2.0 ad 2.5 ad 2.5 ad 8.0 ad 59 ad 4 ad 2.0 ad 2.5 ad 2.5 ad 8.0 ad 28 ad 4 ad 2.5 ad 0.0 ad 2.5 ad 4.0 ad 33 ad 4 ad 2.5 ad 0.0 ad 2.5 ad 4.0 ad free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 394 of 485 rej09b0244-0300 18.5 internal equivalent circuit of analog input figure 18.10 shows the internal equivalent circuit of analog input. figure 18.10 internal equivalent circuit of analog input vcc parasitic diode chopper-type amplifier a/d successive conversion register comparison voltage b1 b2 b0 vcc vss an0 vss i = 12 an11 vref avss vref comparison reference voltage (vref) generator sw1 sw2 avcc amp sw3 avss vin sw4 sw5 sw1 parasitic diode on resistor approx. 2k ? wiring resistor approx. 0.2k ? on resistor approx. 0.6k ? on resistor approx. 2k ? wiring resistor approx. 0.2k ? i ladder-type switches a/d control register 0 on resistor approx. 0.6k f analog input voltage sampling control signal on resistor approx. 5k ? c = approx.1.5pf a/d conversion interrupt request sw1 conducts only on the ports selected for analog input. sw2 and sw3 are open when a/d conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. sw4 conducts only when a/d conversion is not in progress. sw5 conducts when compare operation is in progress. control signal for sw2 control signal for sw3 sampling compari son connect to connect to connect to connect to note: 1. use only as a standard for designing this data. mass production may cause some changes in device characteristics. i ladder-type wiring resistors resistor ladder reference control signal b4 free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 395 of 485 rej09b0244-0300 18.6 output impedance of sensor under a/d conversion to carry out a/d conversion properly, charging the internal capacitor c shown in figure 18.11 has to be completed within a specified period of time. t (sampling time) as the specified time. let ou tput impedance of sensor equivalent circuit be r0, internal resistance of microcom puter be r, precision (error) of the a/d converter be x, and the resolution of a/d converter be y (y is 1 024 in the 10-bit mode, and 256 in the 8-bit mode). vc is generally and when t = t, hence, figure 18.11 shows the analog input pin and external sens or equivalent circuit. when the difference between vin and vc becomes 0.1lsb, we find impedance r0 wh en voltage between pins vc changes from 0 to vin- (0.1/1024) vin in time t. (0.1/1024) means that a/d precisi on drop due to insufficient capacitor charge is held to 0.1lsb at time of a/d conversion in the 10-bit mode. actu al error however is the value of absolute precision added to 0.1lsb. when f(xin) = 10 mhz, t = 0.25 s in the a/d conversion mode without sample & hold. output impedance r0 for sufficiently charging capacitor c within time t is determined as follows. t = 0.25 s, r = 2.8 k ? , c = 6.0 pf, x = 0.1, and y = 1024. hence, thus, the allowable output impedance of the sensor equivale nt circuit, making the precision (error) 0.1lsb or less, is approximately 1.7 k ? . maximum. figure 18.11 analog input pin and exte rnal sensor equivalent circuit r0 r (2.8 k ? ) c (6.0 pf) vin vc mcu sensor equivalent circuit note: 1. the capacity of the terminal is assumed to be 4.5 pf. r0 t c x y --- - ln ? ------------------- ?r ? = 1 cr0 r + () -------------------------- ?t x y --- - ln = e 1 cr0 r + () -------------------------- t ? x y --- - = vc vin x y --- - vin vin 1 x y --- - ? ?? ?? = ? = vc vin 1 e 1 cr0 r + () -------------------------- ? t ? ?? ?? ?? = r0 0.25 10 6 ? 6.0 10 12 ? 0.1 1024 ----------- - ln ? -------------------------------------------------- - ? =2.8 3 10 ? 1.7 3 10 free datasheet http:///
r8c/24 group, r8c/25 group 18. a/d converter rev.3.00 feb 29, 2008 page 396 of 485 rej09b0244-0300 18.7 notes on a/d converter ? write to each bit (other th an bit 6) in the adcon0 register, each b it in the adcon1 register, or the smp bit in the adcon2 register when a/d conversi on is stopped (before a trigger occurs). ? when the vcut bit in the adcon1 register is changed from 0 (vref no t connected) to 1 (vref connected), wait for at least 1 s before starting the a/d conversion. ? after changing the a/d operating mode, select an analog input pin again. ? when using the one-shot mode, ensure that a/d conversion is completed before reading the ad register. the ir bit in the adic register or the adst bit in the ad con0 register can be used to determine whether a/d conversion is completed. ? when using the repeat mode, select the fr equency of the a/d converter operating clock ad or more for the cpu clock during a/d conversion. do not select th e foco-f for the ad. ? if the adst bit in the adcon0 register is set to 0 (a /d conversion stops) by a program and a/d conversion is forcibly terminated duri ng an a/d conversion operatio n, the conversion result of the a/d converter will be undefined. if the adst bit is set to 0 by a program, do not use the value of the ad register. ? connect 0.1 f capacitor between the p4_2 /vref pin and avss pin. ? do not enter stop mode during a/d conversion. ? do not enter wait mode when the cm02 bit in the cm0 re gister is set to 1 (peripheral function clock stops in wait mode) during a/d conversion. free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 397 of 485 rej09b0244-0300 19. flash memory 19.1 overview in the flash memory, rewrite operations to the flash memory can be pe rformed in three modes : cpu rewrite, standard serial i/o, and parallel i/o. table 19.1 lists the flash memo ry performance (refer to table 1.1 functions and specifications for r8c/24 group and table 1.2 functions and specifications for r8c/25 group for items not listed in table 19.1 ). notes: 1. definition of programming and erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be eras ed n times. for example, if 1,024 1-byte writes are performed to block a, a 1-kbyte block, and then the block is erased, the erase count stands at one. when performing 100 or more rewrites, th e actual erase count can be reduced by executing programming operations in such a way that all blank areas are used before perform ing an erase operation. avoid rewriting only particular blocks and try to average ou t the programming and erasure endurance of the blocks. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 2. blocks a and b are implemented only in the r8c/25 group. 3. to perform programming and erasure, use vcc = 2.7 v to 5.5 v as the supply voltage. do not perform programming and erasure at less than 2.7 v. table 19.1 flash me mory performance item specification flash memory operating mode 3 modes (cpu rewrite, standard serial i/o, and parallel i/o) division of erase block refer to figure 19.1 and figure 19.2 programming method byte unit erase method block erase programming and erasure control method (3) program and erase control by software command rewrite control method rewrite control for blocks 0 and 1 by fmr02 bit in fmr0 register rewrite control for block 0 by fmr15 bit and block 1 by fmr16 bit in fmr1 register number of commands 5 commands programming and erasure endurance (1) blocks 0 and 1 (program rom) r8c/24 group: 100 times; r8c/25 group: 1,000 times blocks a and b (data flash) (2) 10,000 times id code check function standard serial i/o mode supported rom code protect parallel i/o mode supported table 19.2 flash memory rewrite modes flash memory rewrite mode cpu rewrite mode standard serial i/o mode parallel i/o mode function user rom area is rewritten by executing software commands from the cpu. ew0 mode: rewritable in the ram ew1 mode: rewritable in flash memory user rom area is rewritten by a dedicated serial programmer. user rom area is rewritten by a dedicated parallel programmer. areas which can be rewritten user rom area user ro m area user rom area operating mode single chip mode boot mode parallel i/o mode rom programmer none serial programmer parallel programmer free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 398 of 485 rej09b0244-0300 19.2 memory map the flash memory contains a user rom area and a boot rom area (reserved area). figure 19.1 shows the flash memory block diagram for r8c/24 group. figure 19.2 shows a flash memory block diagram for r8c/25 group. the user rom area of the r8c/25 group contains an area (program rom) which stores mcu operating programs and blocks a and b (data fl ash) each 1 kbyte in size. the user rom area is divided into several blocks. the us er rom area can be rewritten in cpu rewrite mode and standard serial i/o and parallel i/o modes. when rewriting blocks 0 and 1 in cpu rewrite mode, se t the fmr02 bit in the fmr0 register to 1 (rewrite enabled). when the fmr15 bit in the fm r1 register is set to 0 (rewrite enabled), block 0 is rewritable. when the fmr16 bit is set to 0 (rewrite enabled), block 1 is rewritable. the rewrite control program for standard serial i/o mode is stored in the boot rom area before shipment. the boot rom area and the user rom area share the same address, but have separate memory areas. figure 19.1 flash memory block diagram for r8c/24 group boot rom area (reserved area) (2) 8 kbytes 0e000h 08000h block 0: 16 kbytes (1) 0c000h 0ffffh 16 kbytes rom product block 1: 16 kbytes (1) block 0: 16 kbytes (1) 0bfffh 0c000h 0ffffh 32 kbytes rom product program rom 04000h block 0: 32 kbytes (1) 0c000h 13fffh 64 kbytes rom product block 1: 32 kbytes (1) block 0: 16 kbytes (1) 0bfffh 0c000h 0ffffh 48 kbytes rom product block 1: 32 kbytes (1) 04000h 0bfffh 0ffffh 10000h notes: 1. when the fmr02 bit in the fmr0 register is set to 1 (rewrite enabled) and the fmr15 bit in the fmr1 register is set to 0 (r ewrite enabled), block 0 is rewritable. when the fmr16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for cpu rewrite mode). 2. this area is for storing the boot program provided by renesas technology. user rom area user rom area user rom area user rom area program rom 0ffffh user rom area block 0: 16 kbytes (1) 0c000h 0ffffh 24 kbytes rom product block 1: 8 kbytes (1) 0a000h 0bfffh free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 399 of 485 rej09b0244-0300 figure 19.2 flash memory block diagram for r8c/25 group boot rom area (reserved area) (2) 8 kbytes 0e000h 0ffffh user rom area block 0: 16 kbytes (1) 0c000h 0ffffh block b: 1 kbyte block a: 1 kbyte 02400h 02bffh 16 kbytes rom product 08000h block 1: 16 kbytes (1) user rom area block 0: 16 kbytes (1) 0bfffh 0c000h 0ffffh block b: 1 kbyte block a: 1 kbyte 02400h 02bffh 32 kbytes rom product program rom data flash user rom area block 0: 32 kbytes (1) 0c000h 13fffh block b: 1 kbyte block a: 1 kbyte 02400h 02bffh 64 kbytes rom product 04000h block 1: 32 kbytes (1) user rom area block 0: 16 kbytes (1) 0bfffh 0c000h 0ffffh block b: 1 kbyte block a: 1 kbyte 02400h 02bffh 48 kbytes rom product 0ffffh 10000h 0bfffh 04000h block 1: 32 kbytes (1) program rom data flash user rom area block 0: 16 kbytes (1) 0c000h 0ffffh block b: 1 kbyte block a: 1 kbyte 02400h 02bffh 24 kbytes rom product block 1: 8 kbytes (1) 0a000h 0bfffh notes: 1. when the fmr02 bit in the fmr0 register is set to 1 (rewrite enabled) and the fmr15 bit in the fmr1 register is set to 0 (r ewrite enabled), block 0 is rewritable. when the fmr16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for cpu rewrite mode). 2. this area is for storing the boot program provided by renesas technology. free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 400 of 485 rej09b0244-0300 19.3 functions to prevent re writing of flash memory standard serial i/o mode ha s an id code check function, and parallel i/o mode has a rom code protect function to prevent the flash memory from being read or rewritten easily. 19.3.1 id code check function this function is used in standard serial i/o mode. unless the flash memory is blank, the id codes sent from the programmer and the id codes written in the flash memory are checked to see if they match. if the id codes do not match, the commands sent from the programmer ar e not acknowledged. the id codes consist of 8 bits of data each, the areas of which, beginning with the first byte, are 00ffdfh, 00ffe3h, 00ffebh, 00ffefh, 00fff3h, 00fff7h, and 00fffbh. write pr ograms in which the id codes are set at these addresses and write them to the flash memory. figure 19.3 address for stored id code 4 bytes address note: 1. the ofs register is assigned to 00ffffh. refer to figure 19.4 ofs register for ofs register details. id1 id2 id3 id4 id5 id6 id7 (note 1) undefined instruction vector overflow vector brk instruction vector address match vector oscillation stop detection/watchdog timer/voltage monitor 1 and voltage monitor 2 vector address break reset vector (reserved) single step vector 00ffdfh to 00ffdch 00ffe3h to 00ffe0h 00ffe7h to 00ffe4h 00ffebh to 00ffe8h 00ffefh to 00ffech 00fff3h to 00fff0h 00fff7h to 00fff4h 00fffbh to 00fff8h 00ffffh to 00fffch free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 401 of 485 rej09b0244-0300 19.3.2 rom code protect function the rom code protect function disables reading or changing the contents of the on-chip flash memory by the ofs register in parallel i/o mode. figure 19.4 shows the ofs register. the rom code protect function is enabled by writing 0 to the romcp1 bit and 1 to the romcr bit. it disables reading or changing the contents of the on-chip flash memory. once rom code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel i/o mode. to disable rom code protect, erase the block including the ofs register with cpu rewrite mode or standard serial i/o mode. figure 19.4 ofs register option function select register (1) symbol address when shipping ofs 0ffffh ffh (3) bit symbol bit name function rw notes: 1. 2. 3. if the block including the ofs register is erased, ffh is set to the ofs register. ? (b6) reserved bit set to 1. rw csproini count source protect mode after reset select bit 0 : count source protect mode enabled after reset 1 : count source protect mode disabled after reset rw to use the pow er-on reset, set the lvd0on bit to 0 (voltage monitor 0 reset enabled after reset). romcp1 rom code protect bit 0 : rom code protect enabled 1 : rom code protect disabled rw romcr rom code protect disabled bit 0 : rom code protect disabled 1 : romcp1 enabled rw ? (b1) rw reserved bit set to 1. wdton rw watchdog timer start select bit 0 : starts w atchdog timer automatically after reset 1 : watchdog timer is inactive after reset 1 11 b7 b6 b5 b4 b3 b2 b1 b0 ? (b4) reserved bit set to 1. rw the ofs register is on the flash memory. write to the ofs register w ith a program. after w riting is completed, do not w rite additions to the ofs register. lvd0on voltage detection 0 circuit start bit (2) 0 : voltage monitor 0 reset enabled after hardw are reset 1 : voltage monitor 0 reset disabled after hardw are reset rw free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 402 of 485 rej09b0244-0300 19.4 cpu rewrite mode in cpu rewrite mode, the user rom area can be rewr itten by executing software commands from the cpu. therefore, the user rom area can be rewritten directly while the mcu is mounted on a board without using a rom programmer. execute the progra m and block erase commands only to blocks in the user rom area. the flash module has an erase-suspend function when an in terrupt request is generated during an erase operation in cpu rewrite mode. it performs an interrupt process afte r the erase operation is halted temporarily. during erase- suspend, the user rom area can be read by a program. in case an interrupt request is generated during an auto -program operation in cpu rewrite mode, the flash module has a program-suspend function which performs the inte rrupt process after the au to-program operation is suspended. during program-suspend, the user rom area can be read by a program. cpu rewrite mode has an erase write 0 mode (ew0 mode) and an erase write 1 mode (e w1 mode). table 19.3 lists the differences between ew0 mode and ew1 mode. note: 1. when the fmr02 bit in the fmr0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled by setting the fmr15 bit in the fmr1 register to 0 (rewrite e nabled), and rewriting block 1 is enabled by setting the fmr16 bit to 0 (rewrite enabled). table 19.3 differences between ew0 mode and ew1 mode item ew0 mode ew1 mode operating mode single-chip mode single-chip mode areas in which a rewrite control program can be located user rom area user rom area areas in which a rewrite control program can be executed necessary to transfer to any area other than the flash memory (e.g., ram) before executing executing directly in user rom or ram area possible areas which can be rewritten user rom area user rom area however, blocks which contain a rewrite control program are excluded (1) software command restrictions none ? program and block erase commands cannot be run on any block which contains a rewrite control program ? read status register command cannot be executed modes after program or erase read status register mode read array mode modes after read status register read status register mode do not execute this command cpu status during auto- write and auto-erase operating hold state (i/o ports hold state before the command is executed) flash memory status detection ? read bits fmr00, fmr06, and fmr07 in the fmr0 register by a program ? execute the read status register command and read bits sr7, sr5, and sr4 in the status register. read bits fmr00, fmr06, and fmr07 in the fmr0 register by a program conditions for transition to erase-suspend set bits fmr40 and fmr41 in the fmr4 register to 1 by a program. the fmr40 bit in the fmr4 register is set to 1 and the interrupt request of the enabled maskable interrupt is generated conditions for transitions to program-suspend set bits fmr40 and fmr42 in the fmr4 register to 1 by a program. the fmr40 bit in the fmr4 register is set to 1 and the interrupt request of the enabled maskable interrupt is generated cpu clock 5 mhz or below no restriction (on clock frequency to be used) free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 403 of 485 rej09b0244-0300 19.4.1 ew0 mode the mcu enters cpu rewrite mode and software commands can be acknowledged by setting the fmr01 bit in the fmr0 register to 1 (cpu rewrite mode enabled). in this case, since th e fmr11 bit in the fmr1 register is set to 0, ew0 mode is selected. use software commands to control pr ogram and erase operations. the fmr0 register or the status register can be used to determine when program and erase operations complete. during auto-erasure, set the fmr40 bi t to 1 (erase-suspend enabled) and the fmr41 bit to 1 (request erase- suspend). wait for td(sr-sus) and ensure that the fmr46 bit is set to 1 (read enabled) before accessing the user rom area. the auto-erase operat ion can be restarted by setting the fmr41 bit to 0 (erase restarts). to enter program-suspend during the auto-program operati on, set the fmr40 bit to 1 (suspend enabled) and the fmr42 bit to 1 (request program-suspend). wait for td(s r-sus) and ensure that the fmr46 bit is set to 1 (read enabled) before accessing the user rom area. the auto-program operation can be restarted by setting the fmr42 bit to 0 (program restarts). 19.4.2 ew1 mode the mcu is switched to ew1 mode by setting the fmr11 bit to 1 (ew1 mode) after setting the fmr01 bit to 1 (cpu rewrite mode enabled). the fmr0 register can be used to determine when progra m and erase operations complete. do not execute commands that use the read st atus register in ew1 mode. to enable the erase-suspend function during auto-erasure, ex ecute the block erase co mmand after setting the fmr40 bit to 1 (erase-suspend enabled) . the interrupt to enter erase-suspend should be in interrupt enabled status. after waiting for td(sr-sus) after the bloc k erase command is executed, the interrupt request is acknowledged. when an interrupt request is generated, the fmr41 bit is automatically set to 1 (re quests erase-suspend) and the auto-erase operation suspends. if an auto-erase operati on does not complete (fmr00 bit is 0) after an interrupt process completes, the auto-erase operation restar ts by setting the fmr41 bit to 0 (erasure restarts) to enable the program-suspend function during auto-p rogramming, execute the pr ogram command after setting the fmr40 bit to 1 (suspend enabled). the interrupt to enter program-suspend should be in interrupt enabled status. after waiting for td(sr-sus) after the program command is executed, an interrupt request is acknowledged. when an interrupt request is generated, the fmr42 bit is automatically set to 1 (request program-suspend) and the auto-program oper ation suspends. when the auto-program operation does not complete (fmr00 bit is 0) after the interrupt process completes, the auto-program op eration can be restarted by setting the fmr42 bit to 0 (programming restarts). free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 404 of 485 rej09b0244-0300 figure 19.5 shows the fmr0 regist er. figure 19.6 shows the fmr1 re gister. figure 19.7 shows the fmr4 register. 19.4.2.1 fmr00 bit this bit indicates the operating status of the flash me mory. the bits value is 0 during programming, erasure (including suspend periods), or erase-suspend mode; otherwise, it is 1. 19.4.2.2 fmr01 bit the mcu is made ready to accept commands by setting the fmr01 bit to 1 (cpu rewrite mode). 19.4.2.3 fmr02 bit rewriting of blocks 0 and 1 does not accept program or block erase comma nds if the fmr02 bit is set to 0 (rewrite disabled). rewriting of blocks 0 and 1 is controlled by bits fmr15 and fmr16 if the fmr02 bit is set to 1 (rewrite enabled). 19.4.2.4 fmstp bit this bit is used to initialize the flash memory contro l circuits, and also to reduce the amount of current consumed by the flash memory. access to the flash memory is disabled by setting the fmstp bit to 1. therefore, the fmstp bit must be written to by a program tran sferred to the ram. in the following cases, set the fmstp bit to 1: ? when flash memory access resulted in an error whil e erasing or programming in ew0 mode (fmr00 bit not reset to 1 (ready)) ? to provide lower consumption in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode (xin clock stops), and low-speed clock mode (xin clock stops). figure 19.11 shows the handling to provide lower cons umption in high-speed on-chip oscillator mode, low- speed on-chip oscillator mode (xin clock stops), a nd low-speed clock mode (xin clock stops). handle according to this flowchart. note that when going to stop or wait mode while the cpu re write mode is disabled, the fmr0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode. 19.4.2.5 fmr06 bit this is a read-only bit indicating the status of an auto-program operation. the bit is set to 1 when a program error occurs; otherwise, it is set to 0. for details, refer to the description in 19.4.5 full status check . 19.4.2.6 fmr07 bit this is a read-only bit indicating the st atus of an auto-erase operation. the bit is set to 1 when an erase error occurs; otherwise, it is set to 0. refer to 19.4.5 full status check for details. 19.4.2.7 fmr11 bit setting this bit to 1 (ew1 mo de) places the mcu in ew1 mode. 19.4.2.8 fmr15 bit when the fmr02 bit is set to 1 (rewrite enabled) and the fmr15 bit is set to 0 (rewrite enabled), block 0 accepts program and block erase commands. 19.4.2.9 fmr16 bit when the fmr02 bit is set to 1 (rewrite enabled) and the fmr16 bit is set to 0 (rewrite enabled), block 1 accepts program and block erase commands. free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 405 of 485 rej09b0244-0300 19.4.2.10 fmr40 bit the suspend function is enabled by setting the fmr40 bit to 1 (enable). 19.4.2.11 fmr41 bit in ew0 mode, the mcu enters erase-suspend mode when the fmr41 bit is set to 1 by a program. the fmr41 bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is generated in ew1 mode, and then the mcu enters erase-suspend mode. set the fmr41 bit to 0 (erase restarts) when the auto-erase operation restarts. 19.4.2.12 fmr42 bit in ew0 mode, the mcu enters program-suspend mode when the fmr42 bit is set to 1 by a program. the fmr42 bit is automatically set to 1 (request program- suspend) when an interrupt request of an enabled interrupt is generated in ew1 mode, and th en the mcu enters program-suspend mode. set the fmr42 bit to 0 (program restart) when the auto-program operation restarts. 19.4.2.13 fmr43 bit when the auto-erase operation starts, the fmr43 bit is set to 1 (erase execution in progress). the fmr43 bit remains set to 1 (erase execution in progress) during erase-suspend operation. when the auto-erase operation ends, the fm r43 bit is set to 0 (erase not executed). 19.4.2.14 fmr44 bit when the auto-program operation star ts, the fmr44 bit is set to 1 (program execution in progress). the fmr44 bit remains set to 1 (program execution in progress) during program-suspend operation. when the auto-program operatio n ends, the fmr44 bit is set to 0 (program not executed). 19.4.2.15 fmr46 bit the fmr46 bit is set to 0 (reading disabled) during auto -program or auto-erase ex ecution and set to 1 (reading enabled) in suspend mode. do not access the flash memory while this bit is set to 0. 19.4.2.16 fmr47 bit power consumption when reading the flash memory can be reduced by set ting the fmr47 bit to 1 (enabled) in low-speed clock mode (xin clock stops) and low- speed on-chip oscillator mode (xin clock stops). free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 406 of 485 rej09b0244-0300 figure 19.5 fmr0 register flash memory control register 0 symbol address after reset fmr0 01b7h 00000001b bit symbol bit name function rw ry /by _ __ status flag notes: 1. 2. 3. 4. 5. 6. this bit is set to 0 by executing the clear status command. this bit is enabled w hen the fmr01 bit is set to 1 (cpu rew rite mode enabled). when the fmr01 bit is set to 0, w riting 1 to the fmstp bit causes the fmstp bit to be set to 1. the flash memory does not enter low -pow er consumption state nor is it reset. fmr06 to set this bit to 1, set it to 1 immediately after setting it first to 0. do not generate an interrupt betw een setting the bit to 0 and setting it to 1. enter read array mode and set this bit to 0. set this bit to 1 immediately after setting it first to 0 w hile the fmr01 bit is set to 1. do not generate an interrupt betw een setting the bit to 0 and setting it to 1. set this bit by a program transferred to the ram. program status flag (4) 0 : completed successfully 1 : terminated by error erase status flag (4) 0 : completed successfully 1 : terminated by error rw ro ro ro reserved bits set to 0. rw fmr02 rw rw ? (b5-b4) fmr00 fmstp b7 b6 b5 b4 00 0 : enables flash memory operation 1 : stops flash memory (enters low -pow er consumption state and flash memory is reset) fmr01 block 0, 1 rew rite enable bit (2, 6) 0 : busy (w riting or erasing in progress) 1 : ready cpu rew rite mode select bit (1) 0 : cpu rew rite mode disabled 1 : cpu rew rite mode enabled when setting the fmr01 bit to 0 (cpu rew rite mode disabled), the fmr02 bit is set to 0 (disables rew rite). fmr07 b3 b2 b1 b0 0 : disables rew rite 1 : enables rew rite flash memory stop bit (3, 5) free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 407 of 485 rej09b0244-0300 figure 19.6 fmr1 register flash memory control register 1 symbol address after reset fmr1 01b5h 1000000xb bit symbol bit name function rw notes: 1. 2. 3. fmr16 block 1 rew rite disable bit (2,3) to set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the fmr01 bit is set to 1 (cpu rew rite mode enable). do not generate an interrupt betw een setting the bit to 0 and setting it to 1. this bit is set to 0 by setting the fmr01 bit to 0 (cpu rew rite mode disabled). reserved bit set to 1. when the fmr01 bit is set to 1 (cpu rew rite mode enabled), bits fmr15 and fmr16 can be w ritten to. to set this bit to 0, set it to 0 immediately after setting it first to 1. to set this bit to 1, set it to 1. ? (b7) 0 rw rw rw ro rw res er v ed bit 0 : enables rew rite 1 : disables rew rite rw fmr15 ? (b0) res er v ed bits when read, the content is undefined. ew1 mode select bit (1, 2) 0 : ew0 mode 1 : ew1 mode block 0 rew rite disable bit (2,3) 0 : enables rew rite 1 : disables rew rite b7 b6 b5 b4 10 b3 b2 set to 0. 0 b1 b0 fmr11 ? (b4-b2) free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 408 of 485 rej09b0244-0300 figure 19.7 fmr4 register flash memory control register 4 symbol address after reset fmr4 01b3h 01000000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. to set this bit to 1, set it to 1 immediately after setting it first to 0. do not generate an interrupt betw een setting the bit to 0 and setting it to 1. this bit is enabled w hen the fmr40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing an erase command and completing the erase. (this bit is set to 0 during periods other than above.) in ew0 mode, it can be set to 0 or 1 by a program. in ew1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase operation w hile the fmr40 bit is set to 1. do not set this bit to 1 by a program (0 can be w ritten). b3 b2 set to 0. b1 b0 fmr41 ? (b5) 0 fmr40 fmr42 fmr44 b7 b6 b5 b4 rw rw erase-suspend function enable bit (1) 0 : disables reading 1 : enables reading res er v ed bit 0 : disable 1 : enable erase-suspend request bit (2) 0 : erase restart 1 : erase-suspend request ro ro rw fmr43 erase command flag 0 : erase not executed 1 : erase execution in progress ro 0 : disable 1 : enable fmr46 program-suspend request bit (3) 0 : program restart 1 : program-suspend request set the fmr01 bit in the fmr0 register to 0 (cpu rew rite mode disabled) in low -pow er consumption read mode. in high-speed clock mode and high-speed on-chip osc illator m ode, set the fmr47 bit to 0 (disabled). program command flag 0 : program not executed 1 : program execution in progress ro the fmr42 bit is enabled only w hen the fmr40 bit is set to 1 (enable) and programming to the fmr42 bit is enabled until auto-programming ends after a program command is generated. (this bit is set to 0 during periods other than the above.) in ew0 mode, 0 or 1 can be programmed to the fmr42 bit by a program. in ew1 mode, the fmr42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming w hen the fmr40 bit is set to 1. 1 cannot be w ritten to the fmr42 bit by a program. fmr47 read status flag rw low -pow er consumption read mode enable bit (1, 4, 5) free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 409 of 485 rej09b0244-0300 figure 19.8 shows the timing of suspend operation. figure 19.8 timing of suspend operation fmr00 bit in fmr0 register fmr46 bit in fmr4 register fmr44 bit in fmr4 register fmr43 bit in fmr4 register 1 0 1 0 1 0 1 0 erasure starts erasure suspends programming starts programming suspends programming restarts programming ends during erasure during programming during programming erasure restarts erasure ends during erasure check that the fmr43 bit is set to 1 (during erase execution), and that the erase-operation has not ended. check that the fmr44 bit is set to 1 (during program execution), and that the program has not ended. check the status, and that the programming ends normally. check the status, and that the erasure ends normally. remains 0 during suspend remains 1 during suspend note: 1. if program-suspend is entered during erase-suspend, always restart programming. the above figure shows an example of the use of program-suspend during programming following erase-suspend. free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 410 of 485 rej09b0244-0300 figure 19.9 shows the how to set and exit ew0 mode. figure 19.10 shows the how to set and exit ew1 mode. figure 19.9 how to set and exit ew0 mode figure 19.10 how to set and exit ew1 mode set registers (1) cm0 and cm1 transfer a rewrite control program which uses cpu rewrite mode to the ram. jump to the rewrite control program which has been transferred to the ram. (the subsequent process is executed by the rewrite control program in the ram.) write 0 to the fmr01 bit before writing 1 (cpu rewrite mode enabled) (2) execute the read array command (3) execute software commands write 0 to the fmr01 bit (cpu rewrite mode disabled) jump to a specified address in the flash memory rewrite control program notes: 1. select 5 mhz or below for the cpu clock by the cm06 bit in the cm0 register and bits cm16 to cm17 in the cm1 register. 2. to set the fmr01 bit to 1, write 0 to the fmr01 bit before writing 1. do not generate an interrupt between writing 0 and 1. write to the fmr01 bit in the ram. 3. disable the cpu rewrite mode after executing the read array command. ew0 mode operating procedure write 0 to the fmr01 bit before writing 1 (cpu rewrite mode enabled) (1) write 0 to the fmr11 bit before writing 1 (ew1 mode) execute software commands write 0 to the fmr01 bit (cpu rewrite mode disabled) note: 1. to set the fmr01 bit to 1, write 0 to the fmr01 bit before writing 1. do not generate an interrupt between writing 0 and 1. ew1 mode operating procedure program in rom free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 411 of 485 rej09b0244-0300 figure 19.11 process to reduce power consumpt ion in high-speed on-c hip oscillator mode, low-speed on-chip oscillator mode (xin clock stops) and low-speed clock mode (xin clock stops) transfer a high-speed on-chip oscillator mode, low- speed on-chip oscillator mo de (xin clock stops), and low-speed clock mode (xin clock stops) program to the ram. jump to the high-speed on-c hip oscillator mode, low- speed on-chip oscillator mo de (xin clock stops), and low-speed clock mode (xin clock stops) program which has been transferred to the ram. (the subsequent processing is executed by the program in the ram.) write 0 to the fmr01 bit before writing 1 (cpu rewrite mode enabled) switch the clock source for the cpu clock. turn xin off process in high-speed on-chip oscillator mode, low-speed on-ch ip oscillator mode (xin clock stops), and low-speed clock mode (xin clock stops) write 0 to the fmr01 bit (cpu rewrite mode disabled) jump to a specified address in the flash memory high-speed on-chip oscillator mode, low-speed on-chip oscillator mode (xin clock stops), and low-speed clock mode (xin clock stops) program notes: 1. set the fmr01 bit to 1 (cpu rewrite mode enabled) before setting the fmstp bit to 1. 2. before switching to a different clock source for the cpu, make sure the designated clock is stable. 3. insert a 30 s wait time in a program. do not access to the flash memory during this wait time. write 1 to the fmstp bit (flash memory stops. low power consumption mode) (1) wait until the flash memory circuit stabilizes (30 s) (3) write 0 to the fmstp bit (flash memory operation) turn xin clock on wait until oscillation stabilizes switch the clock source for cpu clock (2) free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 412 of 485 rej09b0244-0300 19.4.3 software commands the software commands are described below. read or write commands and data in 8-bit units. srd: status register data (d7 to d0) wa: write address (ensure the address specified in th e first bus cycle is the same address as the write address specified in the second bus cycle.) wd: write data (8 bits) ba: given block address : any specified address in the user rom area 19.4.3.1 read array command the read array command reads the flash memory. the mcu enters read array mode when ffh is written in the first bus cycle. when the read address is entered in the following bus cycles , the content of the specified addr ess can be read in 8-bit units. since the mcu remains in read array mode until another command is written, the contents of multiple addresses can be read continuously. in addition, the mcu enters r ead array mode after a reset. 19.4.3.2 read status register command the read status register command is used to read the status register. when 70h is written in the first bus cy cle, the status register can be read in the second bus cycle (refer to 19.4.4 status registers ). when reading the status register, specify an addr ess in the user rom area. do not execute this command in ew1 mode. the mcu remains in read status register mode until the next read array command is written. 19.4.3.3 clear status register command the clear status register command sets the status register to 0. when 50h is written in the first bus cycle, bits fmr06 to fmr07 in the fmr0 register and sr4 to sr5 in the status register are set to 0. table 19.4 software commands command first bus cycle second bus cycle mode address data (d7 to d0) mode address data ( d7 to d0) read array write ffh read status register write 70h read srd clear status register write 50h program write wa 40h write wa wd block erase write 20h write ba d0h free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 413 of 485 rej09b0244-0300 19.4.3.4 program command the program command writes data to the flash memory in 1-byte units. by writing 40h in the first bus cycle and data in the s econd bus cycle to the writ e address, an auto-program operation (data program and verify) will start. make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. the fmr00 bit in the fmr0 register can be used to determine whether auto-programming has completed. when suspend function disabled, the fmr00 bit is set to 0 during auto-programming and set to 1 when auto- programming completes. when suspen d function enabled, the fmr44 bit is set to 1 during auto-programming and set to 0 when auto-programming completes. the fmr06 bit in the fmr0 register can be used to de termine the result of auto -programming after it has been finished (refer to 19.4.5 full status check ). do not write additions to the already programmed addresses. when the fmr02 bit in the fmr0 register is set to 0 (rew riting disabled), or the fmr02 bit is set to 1 (rewrite enabled) and the fmr15 bit in the fmr1 register is set to 1 (rewriting disabled), program commands targeting block 0 are not acknowledged. when the fmr16 bit is set to 1 (rewriting disabled), program commands targeting block 1 are not acknowledged. figure 19.12 shows the program command (when su spend function disabled). figure 19.13 shows the program command (when suspend function enabled). in ew1 mode, do not execute this command for any a ddress which a rewrite cont rol program is allocated. in ew0 mode, the mcu enters read status register mode at the same time auto-p rogramming starts and the status register can be read. the status register bit 7 (sr7) is set to 0 at the same time auto-programming starts and set back to 1 when auto-programming completes. in this case, the mcu remains in read status register mode until the next read array command is written. the status register ca n be read to determine the result of auto-programming after auto-programming has completed. figure 19.12 program command (when suspend function disabled) start write the command code 40h to the write address write data to the write address fmr00 = 1? full status check program completed no yes free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 414 of 485 rej09b0244-0300 figure 19.13 program command (when suspend function enabled) start write the command code 40h to the write address write data to the write address fmr44 = 0 ? full status check program completed no yes ew0 mode fmr40 = 1 start write the command code 40h write data to the write address fmr44 = 0 ? full status check program completed no yes ew1 mode fmr40 = 1 maskable interrupt (2) reit access flash memory fmr42 = 0 notes: 1. in ew0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the ram area. 2. td(sr-sus) is needed until the interrupt request is acknowledged after it is generated. the interrupt to enter suspend should be in interrupt enabled status. 3. when no interrupt is used, the instruction to enable interrupts is not needed. 4. td(sr-sus) is needed until program is suspended after the fmr42 bit in the fmr4 register is set to 1. maskable interrupt (1) fmr46 = 1 ? reit yes fmr42 = 1 (4) fmr42 = 0 access flash memory fmr44 = 1 ? yes no access flash memory no i = 1 (enable interrupt) i = 1 (enable interrupt) (3) free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 415 of 485 rej09b0244-0300 19.4.3.5 block erase when 20h is written in the first bus cycle and d0h is wr itten to a given address of a block in the second bus cycle, an auto-erase operation (erase an d verify) of the specified block starts. the fmr00 bit in the fmr0 regist er can be used to de termine whether auto-erasure has completed. the fmr00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes. the fmr07 bit in the fmr0 register can be used to dete rmine the result of auto-erasure after auto-erasure has completed (refer to 19.4.5 full status check ). when the fmr02 bit in the fmr0 register is set to 0 (r ewriting disabled) or the fmr02 bit is set to 1 (rewriting enabled) and the fmr15 bit in the fmr1 register is set to 1 (rewriting disabled), the block erase commands targeting block 0 are not acknowledge d. when the fmr16 bit is set to 1 (rewriting disabled), block erase commands targeting block 1 are not acknowledged. do not use the block erase command during program-suspend. figure 19.14 shows the block erase command (when er ase-suspend function disabled). figure 19.15 shows the block erase command (when er ase-suspend function enabled). in ew1 mode, do not execute this command for any addr ess to which a rewrite control program is allocated. in ew0 mode, the mcu enters read stat us register mode at the same time auto-erasure starts and the status register can be read. the status register bit 7 (sr7) is set to 0 at the same time auto-erasure starts and set back to 1 when auto-erasure completes. in th is case, the mcu remains in read stat us register mode until the next read array command is written. figure 19.14 block erase command (when erase-suspend function disabled) start write the command code 20h write d0h to a given block address fmr00 = 1? full status check block erase completed no yes free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 416 of 485 rej09b0244-0300 figure 19.15 block erase command (when erase-suspend function enabled) start write the command code 20h write d0h to any block address fmr00 = 1 ? full status check block erase completed no yes ew0 mode fmr40 = 1 start write the command code 20h write d0h to any block address fmr00 = 1 ? full status check block erase completed no yes ew1 mode i = 1 (enable interrupt) maskable interrupt (2) reit access flash memory fmr41 = 0 notes: 1. in ew0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the ram area. 2. td(sr-sus) is needed until the interrupt request is acknowledged after it is generated. the interrupt to enter suspend should be in interrupt enabled status. 3. when no interrupt is used, the instruction to enable interrupts is not needed. 4. td(sr-sus) is needed until erase is suspended after the fmr41 bit in the fmr4 register is set to 1. maskable interrupt (1) fmr46 = 1 ? reit yes fmr41 = 1 (4) fmr41 = 0 access flash memory fmr43 = 1 ? yes no access flash memory no i = 1 (enable interrupt) (3) fmr40 = 1 free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 417 of 485 rej09b0244-0300 19.4.4 status registers the status register indicates the oper ating status of the flash memory and whether an erase or program operation has completed normally or in error. status of the stat us register can be read by bits fmr00, fmr06, and fmr07 in the fmr0 register. table 19.5 lists the status register bits. in ew0 mode, the status register can be read in the following cases: ? when a given address in the user rom area is read after writing the read status register command ? when a given address in the user rom area is read after executing program or block erase command but before executing the read array command. 19.4.4.1 sequencer status (bits sr7 and fmr00) the sequencer status bits indicate the operating status of the flash memory. sr7 is set to 0 (busy) during auto- programming and auto-erasure, and is set to 1 (rea dy) at the same time the operation completes. 19.4.4.2 erase status (bits sr5 and fmr07) refer to 19.4.5 full status check . 19.4.4.3 program status (bits sr4 and fmr06) refer to 19.4.5 full status check . d0 to d7: indicate the data bus which is read when the read status register command is executed. bits fmr07 (sr5) to fmr06 (sr4) are set to 0 by executing the clear status register command. when the fmr07 bit (sr5) or fmr06 bit (sr4) is set to 1, the program and block erase commands cannot be accepted. table 19.5 status register bits status register bit fmr0 register bit status name description value after reset 01 sr0 (d0) ? reserved ??? sr1 (d1) ? reserved ??? sr2 (d2) ? reserved ??? sr3 (d3) ? reserved ??? sr4 (d4) fmr06 program status completed normally error 0 sr5 (d5) fmr07 erase status completed normally error 0 sr6 (d6) ? reserved ??? sr7 (d7) fmr00 sequencer status busy ready 1 free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 418 of 485 rej09b0244-0300 19.4.5 full status check when an error occurs, bits fmr06 to fmr07 in the fmr0 register are set to 1, indicating the occurrence of an error. therefore, checking th ese status bits (full status check) can be used to determine the execution result. table 19.6 lists the errors and fmr0 register status. figure 19.16 shows the full status check and handling procedure for indi vidual errors. note: 1. the mcu enters read array mode when ffh is writ ten in the second bus cycle of these commands. at the same time, the comma nd code written in the first bus cycle is disabled. table 19.6 errors and fmr0 register status fmr0 register (status register) status error error occurrence condition fmr07(sr5) fmr06(sr4) 1 1 command sequence error ? when a command is not written correctly ? when invalid data other than that which can be written in the second bus cycle of the block erase command is written (i.e., other than d0h or ffh) (1) ? when the program command or block erase command is executed while rewriting is disabled by the fmr02 bit in the fmr0 register, or the fmr15 or fmr16 bit in the fmr1 register. ? when an address not allocated in flash memory is input during erase command input ? when attempting to erase the block for which rewriting is disabled during erase command input. ? when an address not allocated in flash memory is input during write command input. ? when attempting to write to a block for which rewriting is disabled during write command input. 1 0 erase error ? when the block erase command is executed but auto- erasure does not complete correctly 0 1 program error ? when the program command is executed but not auto- programming does not complete. free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 419 of 485 rej09b0244-0300 figure 19.16 full status check and ha ndling procedure for individual errors note: 1. to rewrite to the address where the program error occurs, check if the full status check is complete normally and write to the address after the block erase command is executed. full status check fmr06 = 1 and fmr07 = 1? fmr07 = 1? fmr06 = 1? full status check completed no yes yes no yes no command sequence error erase error program error command sequence error execute the clear status register command (set these status flags to 0) check if command is properly input re-execute the command erase error execute the clear status register command (set these status flags to 0) erase command re-execution times 3 times? re-execute block erase command program error execute the clear status register command (set these status flags to 0) specify the other a ddress besides the write address where the error occurs for the program address (1) re-execute program command block targeting for erasure cannot be used no yes free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 420 of 485 rej09b0244-0300 19.5 standard serial i/o mode in standard serial i/o mode, the user rom area can be rewritten while the mcu is mounted on-board by using a serial programmer which is suitable for the mcu. there are three types of standard serial i/o modes: ? standard serial i/o mode 1 ........... .clock synchronous serial i/o used to connect with a serial programmer ? standard serial i/o mode 2 ........... .clock asynchronous serial i/o used to connect with a serial programmer ? standard serial i/o mode 3 ........... .special clock asynchronous serial i/o used to connect with a serial programmer this mcu uses standard serial i/o mode 2 and standard serial i/o mode 3. refer to appendix 2. connection examples between seri al writer and on-chip debugging emulator. contact the manufacturer of your serial programmer fo r details. refer to the user?s manual of your serial programmer for instructions on how to use it. table 19.7 lists the pin functions (flash memory standard serial i/o mode 2), table 19.8 lists the pin functions (flash memory standard serial i/o mode 3), and figure 19.17 shows pin connections for standard serial i/o mode 3. after processing the pins shown in table 19.8 and rewriting the flash memory using the programmer, apply ?h? to the mode pin and reset the hardware to run a pr ogram in the flash memory in single-chip mode. 19.5.1 id code check function the id code check function determines whether the id codes sent from the serial programmer and those written in the flash memory match (refer to 19.3 functions to prevent rewriting of flash memory ). table 19.7 pin functions (flash memory standard serial i/o mode 2) pin name i/o description vcc,vss power input apply the voltage guaranteed for programming and erasure to the vcc pin and 0 v to the vss pin. reset reset input i reset input pin. p4_6/xin p4_6 input/cl ock input i connect a ceramic re sonator or crystal oscillator between the xin and xout pins. p4_7/xout p4_7 input/clock output i/o p4_3/xcin p4_3 inpu t/clock input i connect crystal o scillator between pins xcin and xcout. p4_4/xcout p4_4 input/clock output i/o p0_0 to p0_7 input port p0 i input ?h? or ?l? level signal or leave the pin open. p1_0 to p1_7 input port p1 i input ?h? or ?l? level signal or leave the pin open. p2_0 to p2_7 input port p2 i input ?h? or ?l? level signal or leave the pin open. p3_0, p3_1, p3_3 to p3_5, p3_7 input port p3 i input ?h? or ?l? level signal or leave the pin open. p4_2/vref, p4_5 input port p4 i input ?h? or ?l? level signal or leave the pin open. p6_0 to p6_5 input port p6 i input ?h? or ?l? level signal or leave the pin open. mode mode i input ?l? level signal. p6_6 txd output o serial data output pin. p6_7 rxd input i serial data input pin. free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 421 of 485 rej09b0244-0300 table 19.8 pin functions (flash memory standard serial i/o mode 3) pin name i/o description vcc,vss power input apply the voltage guaranteed for programming and erasure to the vcc pin and 0 v to the vss pin. reset reset input i re set input pin. p4_6/xin p4_6 input/clock input i connect a ceramic resonator or crystal oscillator between the xin and xout pins when connecting external oscillator. apply ?h? and ?l? or leave the pin open when using as input port. p4_7/xout p4_7 input/clock output i/o p4_3/xcin p4_3 input/clock input i connect cr ystal oscillator between pins xcin and xcout when connect ing external oscillator. apply ?h? and ?l? or leave the pin open when using as a port. p4_4/xcout p4_4 input/clock output i/o p0_0 to p0_7 input port p0 i input ?h? or ?l? level signal or leave the pin open. p1_0 to p1_7 input port p1 i input ?h? or ?l? level signal or leave the pin open. p2_0 to p2_7 input port p2 i input ?h? or ?l? level signal or leave the pin open. p3_0, p3_1, p3_3 to p3_5, p3_7 input port p3 i input ?h? or ?l? level signal or leave the pin open. p4_2/vref, p4_5 input port p4 i input ?h? or ?l? level signal or leave the pin open. p6_0 to p6_7 input port p6 i input ?h? or ?l? level signal or leave the pin open. mode mode i/o serial data i/o pin. connect to the flash programmer. free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 422 of 485 rej09b0244-0300 figure 19.17 pin connections for standard serial i/o mode 3 note: 1. it is not necessary to connect an oscillating circuit when operating with the on-chip oscillator clock. vcc mode connect oscillator circuit (1) package: plqp0052ja-a mode setting signal value mode reset voltage from programmer vss vcc 52 r8c/24 group r8c/25 group 51 50 49 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 32 33 34 35 36 37 38 39 27 40 vss free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 423 of 485 rej09b0244-0300 19.5.1.1 example of circuit applicat ion in standard serial i/o mode figure 19.18 shows an example of pin processing in st andard serial i/o mode 2, and figure 19.19 shows an example of pin processing in standard serial i/o mode 3. since the controlled pins vary depending on the programmer, refer to the manual of your serial programmer for details. figure 19.18 example of pin processing in standard serial i/o mode 2 figure 19.19 example of pin processing in standard serial i/o mode 3 notes: 1. in this example, modes are switched between single-chip mode and standard serial i/o mode by controllin g the mode input with a switch. 2. connecting the oscillation is necessary. set the main clock frequency 1 mhz to 20 mhz. refer to appendix figure 2.1 connection example with m16c flash starter (m3a-0806) . mcu txd rxd data output data input mode notes: 1. controlled pins and external circuits vary depending on the programmer. refer to the programmer manual for details. 2. in this example, modes are switched between single-chip mode and standard serial i/o mode by connecting a programmer. 3. when operating with the on-chip osci llator clock, it is not necessary to connect an oscillating circuit. mcu mode reset user reset signal mode i/o reset input free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 424 of 485 rej09b0244-0300 19.6 parallel i/o mode parallel i/o mode is used to input a nd output software commands, addresses and data necessary to control (read, program, and erase) the on-chip flash memory. use a pa rallel programmer which suppor ts this mcu. contact the manufacturer of the parallel programmer for more inform ation, and refer to the user?s manual of the parallel programmer for details on how to use it. rom areas shown in figures 19.1 and 19.2 can be rewritten in parallel i/o mode. 19.6.1 rom code protect function the rom code protect function disables the reading and rewriting of the flash memory. (refer to 19.3 functions to prevent rewriting of flash memory .) free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 425 of 485 rej09b0244-0300 19.7 notes on flash memory 19.7.1 cpu rewrite mode 19.7.1.1 operating speed before entering cpu rewrite mode (ew0 mode), select 5 mhz or below for the cpu clock using the cm06 bit in the cm0 register and bits cm16 to cm17 in the cm1 register. this does not apply to ew1 mode. 19.7.1.2 prohibited instructions the following instructions cannot be used in ew0 mode because they reference da ta in the flash memory: und, into, and brk. 19.7.1.3 interrupts table 19.9 lists the ew0 mode interrupts, and table 19.10 lists the ew1 mode interrupts. notes: 1. do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in rom. 2. do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is alloca ted in block 0. table 19.9 ew0 mode interrupts mode status when maskable interrupt request is acknowledged when watchdog timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2 interrupt request is acknowledged ew0 during auto-erasure any interrupt can be used by allocating a vector in ram once an interrupt request is acknowledged, auto-programming or auto-erasure is forcibly stopped immediately and the flash memory is reset. interrupt handling starts after the fixed period and the flash memory restarts. since the block during auto- erasure or the address during auto- programming is forcibly stopped, the normal value may not be read. execute auto-erasure again and ensure it completes normally. since the watchdog timer does not stop during the command operation, interrupt requests may be generated. reset the watchdog timer regularly. auto-programming free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 426 of 485 rej09b0244-0300 notes: 1. do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in rom. 2. do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is alloca ted in block 0. table 19.10 ew1 mode interrupts mode status when maskable interrupt request is acknowledged when watchdog timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2 interrupt request is acknowledged ew1 during auto-erasure (erase-suspend function enabled) auto-erasure is suspended after td(sr-sus) and interrupt handling is executed. auto- erasure can be restarted by setting the fmr41 bit in the fmr4 register to 0 (erase restart) after interrupt handling completes. once an interrupt request is acknowledged, auto-programming or auto-erasure is forcibly stopped immediately and the flash memory is reset. interrupt handling starts after the fixed period and the flash memory restarts. since the block during auto- erasure or the address during auto- programming is forcibly stopped, the normal value may not be read. execute auto-erasure again and ensure it completes normally. since the watchdog timer does not stop during the command operation, interrupt requests may be generated. reset the watchdog timer regularly using the erase-suspend function. during auto-erasure (erase-suspend function disabled) auto-erasure has priority and the interrupt request acknowledgement is put on standby. interrupt handling is executed after auto-erasure completes. during auto- programming (program suspend function enabled) auto-programming is suspended after td(sr-sus) and interrupt handling is executed. auto-programming can be restarted by setting the fmr42 bit in the fmr4 register to 0 (program restart) after interrupt handling completes. during auto- programming (program suspend function disabled) auto-programming has priority and the interrupt request acknowledgement is put on standby. interrupt handling is executed after auto-programming completes. free datasheet http:///
r8c/24 group, r8c/25 group 19. flash memory rev.3.00 feb 29, 2008 page 427 of 485 rej09b0244-0300 19.7.1.4 how to access write 0 before writing 1 when setting the fmr01, fmr02, or fmr11 bit to 1. do not generate an interrupt between writing 0 and 1. 19.7.1.5 rewriting user rom area in ew0 mode, if the supply voltage drops while rewr iting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. in this case, use standard serial i/o mode. 19.7.1.6 program do not write additions to th e already programmed address. 19.7.1.7 entering stop mode or wait mode do not enter stop mode or wait mode during erase-suspend. 19.7.1.8 program and erase voltage for flash memory to perform programming and erasure, use vcc = 2.7 to 5.5 v as the supply voltage. do not perform programming and erasure at less than 2.7 v. free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 428 of 485 rej09b0244-0300 20. electrical characteristics note: 1. 300 mw for the ptlg0064ja-a package. table 20.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage -0.3 to 6.5 v v i input voltage -0.3 to v cc + 0.3 v v o output voltage -0.3 to v cc + 0.3 v p d power dissipation t opr = 25 c 500 (1) mw t opr operating ambient temperature -20 to 85 (n version) / -40 to 85 (d version) c t stg storage temperature -65 to 150 c the electrical characteristics of n version (topr = -20 to 85 c) and d version (topr = -40 to 85 c) are listed below. please contact renesas technology sales offices for the electrical characteristics in the y version (topr = -20 to 105 c). free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 429 of 485 rej09b0244-0300 notes: 1. v cc = 2.2 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. the average output current indicates the av erage value of current measured during 100 ms. table 20.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 2.2 ? 5.5 v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage 0.8 v cc ? v cc v v il input ?l? voltage 0 ? 0.2 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? -160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? -80 ma i oh(peak) peak output ?h? current except p2_0 to p2_7 ?? -10 ma p2_0 to p2_7 ?? -40 ma i oh(avg) average output ?h? current except p2_0 to p2_7 ?? -5 ma p2_0 to p2_7 ?? -20 ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ?? 160 ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ?? 80 ma i ol(peak) peak output ?l? current except p2_0 to p2_7 ?? 10 ma p2_0 to p2_7 ?? 40 ma i ol(avg) average output ?l? current except p2_0 to p2_7 ?? 5ma p2_0 to p2_7 ?? 20 ma f (xin) xin clock input oscillation frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz f (xcin) xcin clock input oscillation frequency 2.2 v v cc 5.5 v 0 ? 70 khz ? system clock ocd2 = 0 xln clock selected 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz ocd2 = 1 on-chip oscillator clock selected fra01 = 0 low-speed on-chip oscillator clock selected ? 125 ? khz fra01 = 1 high-speed on-chip oscillator clock selected 3.0 v v cc 5.5 v ?? 20 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.7 v v cc 5.5 v ?? 10 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.2 v v cc 5.5 v ?? 5mhz free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 430 of 485 rej09b0244-0300 notes: 1. av cc = 2.2 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. when the analog input voltage is over the reference voltage, the a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. figure 20.1 ports p0 to p4, p6 timing measurement circuit table 20.3 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ?? 10 bit ? absolute accuracy 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 3 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 2 lsb 10-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 5 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 2 lsb 10-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 5 lsb 8-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 2 lsb r ladder resistor ladder v ref = av cc 10 ? 40 k ? t conv conversion time 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 3.3 ?? s 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 2.8 ?? s v ref reference voltage 2.2 ? av cc v v ia analog input voltage (2) 0 ? av cc v ? a/d operating clock frequency without sample and hold v ref = av cc = 2.7 to 5.5 v 0.25 ? 10 mhz with sample and hold v ref = av cc = 2.7 to 5.5 v 1 ? 10 mhz without sample and hold v ref = av cc = 2.2 to 5.5 v 0.25 ? 5mhz with sample and hold v ref = av cc = 2.2 to 5.5 v 1 ? 5mhz p0 p1 p2 p3 p4 p6 30pf free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 431 of 485 rej09b0244-0300 notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of progr amming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), eac h block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operati on (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple pr ogramming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failur e rate information should contact their renesas technical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 20.4 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/24 group 100 (3) ?? times r8c/25 group 1,000 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 432 of 485 rej09b0244-0300 notes: 1. v cc = 2.7 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. definition of progr amming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), eac h block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operati on (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. standard of block a and block b when program and erase endurance exceeds 1,000 times. byte program time to 1,000 times is the same as that in program rom. 5. in a system that executes multiple pr ogramming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failur e rate information should contact their renesas technical support representative. 8. -40 c for d version. 9. the data hold time includes time that the po wer supply is off or t he clock is not supplied. table 20.5 flash memory (data flash block a, block b) electrical characteristics (4) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 50 400 s ? byte program time (program/erase endurance > 1,000 times) ? 65 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature -20 (8) ? 85 c ? data hold time (9) ambient temperature = 55 c20 ?? year free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 433 of 485 rej09b0244-0300 figure 20.2 time de lay until suspend notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version). 2. necessary time until the voltage detection circuit operates when setting to 1 again af ter setting the vca25 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version). 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again af ter setting the vca26 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates after setting to 1 again after setting the vca27 bit in the vca2 register to 0. table 20.6 voltage detection 0 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level 2.2 2.3 2.4 v ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 0.9 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 300 s vccmin mcu operating voltage minimum value 2.2 ?? v table 20.7 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level 2.70 2.85 3.00 v ? voltage monitor 1 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s table 20.8 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level 3.3 3.6 3.9 v ? voltage monitor 2 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 434 of 485 rej09b0244-0300 notes: 1. the measurement condition is t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. this condition (external power v cc rise gradient) does not apply if v cc 1.0 v. 3. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 res pectively, and the vca25 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain t w(por1) for 30 s or more if -20 c t opr 85 c, maintain t w(por1) for 3,000 s or more if -40 c t opr < -20 c. figure 20.3 power-on reset circuit electrical characteristics table 20.9 power-on reset circuit, voltage monitor 0 reset electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 0.1 v v por2 power-on reset or voltage monitor 0 reset valid voltage 0 ? v det0 v t rth external power v cc rise gradient (2) 20 ?? mv/msec notes: 1. when using the voltage monitor 0 digital filter, ensure that the voltage is within the mcu operation voltage range (2.2 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit for details. 3. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit for details. v det0 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det0 (3) 1 f oco-s 32 1 f oco-s 32 v por2 2.2 v external power v cc t rth t rth free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 435 of 485 rej09b0244-0300 notes: 1. v cc = 2.2 to 5.5 v, t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. standard values when the fra1 regist er value after reset is assumed. 3. standard values when the corrected value of the fra6 register has been written to the fra1 register. 4. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. v cc = 2.2 to 5.5 v, t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit st abilizes during power-on. 3. time until system clock supply starts after the interrupt is acknowledged to exit stop mode. table 20.10 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco40m high-speed on-chip oscillator frequency temperature ? supply voltage dependence v cc = 4.75 to 5.25 v 0 c t opr 60 c (2) 39.2 40 40.8 mhz v cc = 4.5 to 5.5 v -20 c t opr 85 c 38.8 40 40.8 mhz v cc = 4.5 to 5.5 v -40 c t opr 85 c 38.4 40 40.8 mhz v cc = 3.0 to 5.5 v -20 c t opr 85 c (2) 38.8 40 41.2 mhz v cc = 3.0 to 5.5 v -40 c t opr 85 c (2) 38.4 40 41.6 mhz v cc = 2.7 to 5.5 v -20 c t opr 85 c (2) 38 40 42 mhz v cc = 2.7 to 5.5 v -40 c t opr 85 c (2) 37.6 40 42.4 mhz v cc = 2.2 to 5.5 v -20 c t opr 85 c (3) 35.2 40 44.8 mhz v cc = 2.2 to 5.5 v -40 c t opr 85 c (3) 34 40 46 mhz high-speed on-chip oscillator frequency when correction value in fra7 register is written to fra1 register (4) v cc = 5.0 v, t opr = 25 c ? 36.864 mhz v cc = 3.0 to 5.5 v -20 c t opr 85 c -3% ? 3% % ? value in fra1 register after reset 08h ? f7h ? ? oscillation frequency adjustment unit of high- speed on-chip oscillator adjust fra1 register (value after reset) to -1 ? +0.3 ? mhz ? oscillation stability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 400 ? a table 20.11 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 30 125 250 khz ? oscillation stability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 15 ? a table 20.12 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabiliz ation during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 436 of 485 rej09b0244-0300 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 20.13 timing requirements of clock synchronous serial i/o with chip select (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ?? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (2) slave ?? 1 s t fall ssck clock falling time master ?? 1 t cyc (2) slave ?? 1 s t su sso, ssi data input setup time 100 ?? ns t h sso, ssi data input hold time 1 ?? t cyc (2) t lead scs setup time slave 1t cyc + 50 ?? ns t lag scs hold time slave 1t cyc + 50 ?? ns t od sso, ssi data output delay time ?? 1 t cyc (2) t sa ssi slave access time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 437 of 485 rej09b0244-0300 figure 20.4 i/o timing of clock synchronous serial i/o with chip select (master) v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 438 of 485 rej09b0244-0300 figure 20.5 i/o timing of clock synchronous serial i/o with chip select (slave) v ih or v oh v ih or v oh scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 439 of 485 rej09b0244-0300 figure 20.6 i/o timing of clock synchronous serial i/o with chip select (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v ih or v oh free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 440 of 485 rej09b0244-0300 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 20.7 i/o timing of i 2 c bus interface table 20.14 timing requirements of i 2 c bus interface (1) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 500 (2) ?? ns t sf scl, sda input fall time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hold time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stop stop condition input setup time 3t cyc (2) ?? ns t sdas data input setup time 1t cyc + 20 (2) ?? ns t sdah data input hold time 0 ?? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 441 of 485 rej09b0244-0300 note: 1. v cc = 4.2 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), f(xin) = 20 mhz, unless otherwise specified. table 20.15 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p2_0 to p2_7, xout i oh = -5 ma v cc ? 2.0 ? v cc v i oh = -200 av cc ? 0.5 ? v cc v p2_0 to p2_7 drive capacity high i oh = -20 ma v cc ? 2.0 ? v cc v drive capacity low i oh = -5 ma v cc ? 2.0 ? v cc v xout drive capacity high i oh = -1 ma v cc ? 2.0 ? v cc v drive capacity low i oh = -500 av cc ? 2.0 ? v cc v v ol output ?l? voltage except p2_0 to p2_7, xout i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v p2_0 to p2_7 drive capacity high i ol = 20 ma ?? 2.0 v drive capacity low i ol = 5 ma ?? 2.0 v xout drive capacity high i ol = 1 ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v, vcc = 5v ?? 5.0 a i il input ?l? current vi = 0 v, vcc = 5v ?? -5.0 a r pullup pull-up resistance vi = 0 v, vcc = 5v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 442 of 485 rej09b0244-0300 table 20.16 electrical characteristics (2) [vcc = 5 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 10 17 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 915ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 5 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz no division ? 10 15 ma xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.5 10 ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 130 300 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 30 ? a free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 443 of 485 rej09b0244-0300 table 20.17 electrical characteristics (3) [vcc = 5 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 75 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 60 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 4.0 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.2 ? a increase during a/d converter operation without sample & hold ? 2.6 ? ma with sample & hold ? 1.6 ? ma stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.8 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.2 ? a free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 444 of 485 rej09b0244-0300 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at topr = 25 c) [v cc = 5 v] figure 20.8 xin input and xcin input timing diagram when v cc = 5 v figure 20.9 traio input timing diagram when v cc = 5 v table 20.18 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 20.19 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 5 v xcin input t wh(xcin) t c(xcin) t wl(xcin) traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio) free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 445 of 485 rej09b0244-0300 i = 0 or 1 figure 20.10 serial interfa ce timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 20.11 external interrupt inti input timing diagram when v cc = 5 v table 20.20 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 20.21 external interrupt inti (i = 0 to 3) input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 250 (1) ? ns t w(inl) int0 input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 or 1 v cc = 5 v inti input t w(inl) t w(inh) i = 0 to 3 v cc = 5 v free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 446 of 485 rej09b0244-0300 note: 1. v cc =2.7 to 3.3 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), f(xin) = 10 mh z, unless otherwise specified. table 20.22 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p2_0 to p2_7, xout i oh = -1 ma v cc - 0.5 ? v cc v p2_0 to p2_7 drive capacity high i oh = -5 ma v cc - 0.5 ? v cc v drive capacity low i oh = -1 ma v cc - 0.5 ? v cc v xout drive capacity high i oh = -0.1 ma v cc - 0.5 ? v cc v drive capacity low i oh = -50 av cc - 0.5 ? v cc v v ol output ?l? voltage except p2_0 to p2_7, xout i ol = 1 ma ?? 0.5 v p2_0 to p2_7 drive capacity high i ol = 5 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v, vcc = 3v ?? 4.0 a i il input ?l? current vi = 0 v, vcc = 3v ?? -4.0 a r pullup pull-up resistance vi = 0 v, vcc = 3v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 447 of 485 rej09b0244-0300 table 20.23 electrical characteristics (4) [vcc = 3 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma high-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 59ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma low-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 130 300 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 30 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 70 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 55 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.8 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.0 ? a increase during a/d converter operation without sample & hold ? 0.9 ? ma with sample & hold ? 0.5 ? ma stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 448 of 485 rej09b0244-0300 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at topr = 25 c) [v cc = 3 v] figure 20.12 xin input and xcin input timing diagram when v cc = 3 v figure 20.13 traio input timing diagram when v cc = 3 v table 20.24 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 20.25 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 3 v xcin input t wh(xcin) t c(xcin) t wl(xcin) traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio) free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 449 of 485 rej09b0244-0300 i = 0 or 1 figure 20.14 serial interfa ce timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 20.15 external interrupt inti input timing diagram when v cc = 3 v table 20.26 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 20.27 external interrupt inti (i = 0 to 3) input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 380 (1) ? ns t w(inl) int0 input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 3 v i = 0 to 3 free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 450 of 485 rej09b0244-0300 note: 1. v cc = 2.2 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), f(xin) = 5 mh z, unless otherwise specified. table 20.28 electrical characteristics (5) [v cc = 2.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p2_0 to p2_7, xout i oh = -1 ma v cc - 0.5 ? v cc v p2_0 to p2_7 drive capacity high i oh = -2 ma v cc - 0.5 ? v cc v drive capacity low i oh = -1 ma v cc - 0.5 ? v cc v xout drive capacity high i oh = -0.1 ma v cc - 0.5 ? v cc v drive capacity low i oh = -50 av cc - 0.5 ? v cc v v ol output ?l? voltage except p2_0 to p2_7, xout i ol = 1 ma ?? 0.5 v p2_0 to p2_7 drive capacity high i ol = 2 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.05 0.3 ? v reset 0.05 0.15 ? v i ih input ?h? current vi = 2.2 v ?? 4.0 a i il input ?l? current vi = 0 v ?? -4.0 a r pullup pull-up resistance vi = 0 v 100 200 600 k ? r fxin feedback resistance xin ? 5 ? m ? r fxcin feedback resistance xcin ? 35 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 451 of 485 rej09b0244-0300 table 20.29 electrical characteristics (6) [vcc = 2.2 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.2 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma high-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma low-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 100 230 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 100 230 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 25 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 22 60 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 20 55 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.0 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 1.8 ? a increase during a/d converter operation without sample & hold ? 0.4 ? ma with sample & hold ? 0.3 ? ma stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 452 of 485 rej09b0244-0300 timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v at topr = 25 c) [v cc = 2.2 v] figure 20.16 xin input and xcin input timing diagram when v cc = 2.2 v figure 20.17 traio input timing diagram when v cc = 2.2 v table 20.30 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 200 ? ns t wh(xin) xin input ?h? width 90 ? ns t wl(xin) xin input ?l? width 90 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 20.31 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 2.2 v xcin input t wh(xcin) t c(xcin) t wl(xcin) traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v free datasheet http:///
r8c/24 group, r8c/25 group 20. electrical characteristics rev.3.00 feb 29, 2008 page 453 of 485 rej09b0244-0300 i = 0 or 1 figure 20.18 serial interfa ce timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 20.19 external interrupt inti input timing diagram when v cc = 2.2 v table 20.32 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 20.33 external interrupt inti (i = 0 to 3) input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 1000 (1) ? ns t w(inl) int0 input ?l? width 1000 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 2.2 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 2.2 v i = 0 to 3 free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 454 of 485 rej09b0244-0300 21. usage notes 21.1 notes on clock generation circuit 21.1.1 stop mode when entering stop mode, set the fmr01 bit in the fmr0 register to 0 (cpu rewrite mode disabled) and the cm10 bit in the cm1 register to 1 (stop mode). an instruction queue pre-reads 4 bytes from the instruction which sets the cm10 bit to 1 (stop mode) and the program stops. insert at least 4 nop instructions following the jmp.b instruction after the instruction which sets the cm10 bit to 1. ? program example to enter stop mode bclr 1,fmr0 ; cpu rewrite mode disabled bset 0,prcr ; protect disabled fset i ; enable interrupt bset 0,cm1 ; stop mode jmp.b label_001 label_001 : nop nop nop nop 21.1.2 wait mode when entering wait mode, set the fmr01 bit in the fm r0 register to 0 (cpu re write mode disabled) and execute the wait instruction. an instruction queue pre-reads 4 bytes from the wait instruction and the program stops. insert at least 4 nop instructions after the wait instruction. ? program example to execu te the wait instruction bclr 1,fmr0 ; cpu rewrite mode disabled fset i ; enable interrupt wait ; wait mode nop nop nop nop 21.1.3 oscillation stop detection function since the oscillation stop detection function cannot be used if the xin clock frequency is 2 mhz or below, set bits ocd1 to ocd0 to 00b. 21.1.4 oscillation circuit constants ask the manufacturer of the oscillator to specify th e best oscillation circuit constants for your system. to use this mcu with supply voltage below vcc = 2.7 v, it is recommended to set the cm11 bit in the cm1 register to 1 (on-chip feedback resistor disabled), the cm15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 455 of 485 rej09b0244-0300 21.2 notes on interrupts 21.2.1 reading address 00000h do not read address 00000h by a program. when a mask able interrupt request is acknowledged, the cpu reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. at this time, the acknowledged interrupt ir bit is set to 0. if address 00000h is read by a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. this may cause the interrupt to be cancel ed, or an unexpected interrupt to be generated. 21.2.2 sp setting set any value in the sp before an interrupt is acknowledged. the sp is set to 0000h afte r reset. therefore, if an interrupt is acknowledged before setting a value in the sp, the program may run out of control. 21.2.3 external interrupt and key input interrupt either ?l? level or an ?h? le vel of width shown in the el ectrical characteristics is ne cessary for the signal input to pins int0 to int3 and pins ki0 to ki3 , regardless of the cpu clock. for details, refer to table 20.21 (vcc = 5v), table 20.27 (vcc = 3v), table 20.33 (vcc = 2.2v) external interrupt inti (i = 0 to 3) input . free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 456 of 485 rej09b0244-0300 21.2.4 changing interrupt sources the ir bit in the interrupt control register may be se t to 1 (interrupt requested) when the interrupt source changes. when using an interrupt, set the ir bit to 0 (n o interrupt requested) after changing the interrupt source. in addition, changes of interrupt so urces include all factors that change the interr upt sources assigned to individual software interrupt numbers, polarities, and timing. therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and ti ming, set the ir bit to 0 (no interrupt requested) after the change. refer to the individual periph eral function for its related interrupts. figure 21.1 shows an exam ple of procedure for changing interrupt sources. figure 21.1 example of procedure for changing interrupt sources notes: 1. execute the above settings individually. do not execute two or more settings at once (by one instruction). 2. to prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. in this case, use the i flag if all maskable interrupts can be disabled. if all maskable interrupts cannot be disabled, use bits ilvl0 to ilvl2 of the interrupt whose source is changed. 3. refer to 12.6.5 changing interrupt control register contents for the instructions to be used and usage notes. interrupt source change disable interrupts (2, 3) set the ir bit to 0 (interrupt not requested) using the mov instruction (3) change interrupt source (including mode of peripheral function) enable interrupts (2, 3) change completed ir bit: the interrupt control register bit of an interrupt whose source is changed. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 457 of 485 rej09b0244-0300 21.2.5 changing interrupt c ontrol regist er contents (a) the contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. if in terrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) when changing the contents of an interrupt contro l register after disabling interrupts, be careful to choose appropriate instructions. changing any bit other than ir bit if an interrupt request corresponding to a register is generated while executing the instruction, the ir bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. if this causes a problem, use the following instructions to change the register : and, or, bclr, bset changing ir bit if the ir bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. therefore, use the mov instruct ion to set the ir bit to 0. (c) when disabling interrupts using the i flag, set the i flag as shown in the sample programs below. refer to (b) regarding changing the contents of interrupt control registers by the sample programs. sample programs 1 to 3 are for preventi ng the i flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. example 1: use nop instructions to prevent i flag from being set to 1 before interrupt control register is changed int_switch1: fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h nop ; nop fset i ; enable interrupts example 2: use dummy read to delay fset instruction int_switch2: fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h mov.w mem,r0 ; dummy read fset i ; enable interrupts example 3: use popc instruction to change i flag int_switch3: pushc flg fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h popc flg ; enable interrupts free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 458 of 485 rej09b0244-0300 21.3 notes on timers 21.3.1 notes on timer ra ? timer ra stops counting after a reset. set the values in the timer ra and timer ra prescalers before the count starts. ? even if the prescaler and timer ra are read out in 16- bit units, these registers are read 1 byte at a time by the mcu. consequently, the timer va lue may be updated during the period when these two registers are being read. ? in pulse period measurement mode, bits tedgf and tundf in the tracr register can be set to 0 by writing 0 to these bits by a program. however, these b its remain unchanged if 1 is written. when using the read-modify-write instruction for the tracr regi ster, the tedgf or tundf bit may be set to 0 although these bits are set to 1 while the instruction is being executed. in this case, write 1 to the tedgf or tundf bit which is not supposed to be set to 0 with the mov instruction. ? when changing to pulse period m easurement mode from another mode, the contents of bits tedgf and tundf are undefined. write 0 to bits tedgf and tundf before the count starts. ? the tedgf bit may be set to 1 by the first timer ra prescaler underflow generate d after the count starts. ? when using the pulse period measur ement mode, leave two or more periods of the timer ra prescaler immediately after the count starts, then set the tedgf bit to 0. ? the tcstf bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the tstart bit to 1 (count starts) while the count is stopped. during this time, do not access registers associated with timer ra (1) other than the tcstf bit. timer ra starts counting at the first valid edge of the count source after the tcstf bit is set to 1 (during count). the tcstf bit remains 1 for 0 to 1 cycle of the count source after setting the tstart bit to 0 (count stops) while the count is in progress. timer ra c ounting is stopped when the tcstf bit is set to 0. during this time, do not access re gisters associated with timer ra (1) other than the tcstf bit. note: 1. registers associated with timer ra: tracr, traioc, tramr, trapre, and tra. ? when the trapre register is continuously written during count operation (tcstf bit is set to 1), allow three or more cycles of the count source clock for each write interval. ? when the tra register is continuously written during count operation (tcstf bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 459 of 485 rej09b0244-0300 21.3.2 notes on timer rb ? timer rb stops counting after a reset. set the values in the timer rb and timer rb prescalers before the count starts. ? even if the prescaler and timer rb is read out in 16-bit units, these register s are read 1 byte at a time by the mcu. consequently, the timer value may be updated during the period when these two registers are being read. ? in programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the tstart bit in the trbcr register to 0 (c ount stops) or setting th e tossp bit in the trbocr register to 1 (one-shot stops), the timer reloads the value of reload register and stops. therefore, in programmable one-shot generation mode and programmab le wait one-shot generation mode, read the timer count value before the timer stops. ? the tcstf bit remains 0 (count stops) for 1 to 2 cycl es of the count source after setting the tstart bit to 1 (count starts) while the count is stopped. during this time, do not access re gisters associated with timer rb (1) other than the tcstf bit. the tcstf bit remains 1 for 1 to 2 cycles of the count source after setting the tstart bit to 0 (count stops) while the count is in progress. timer rb count ing is stopped when the tcstf bit is set to 0. during this time, do not access re gisters associated with timer rb (1) other than the tcstf bit. note: 1. registers associated with timer rb: trbcr, trbocr, trbioc , trbmr, trbpre, trbsc, and trbpr. ? if the tstop bit in the trbcr register is set to 1 during timer operation, timer rb stops immediately. ? if 1 is written to the tosst or tossp bit in the t rbocr register, the value of the tosstf bit changes after one or two cycles of the count source have elapsed. if the tossp bit is written to 1 during the period between when the tosst bit is written to 1 and when the tosstf bit is set to 1, the tosstf bit may be set to either 0 or 1 depending on the content state. likewise, if the tosst bit is written to 1 during the period between when the tossp bit is written to 1 and when th e tosstf bit is set to 0, the tosstf bit may be set to either 0 or 1. 21.3.2.1 timer mode the following workaround should be performed in timer mode. to write to registers trbpre and trbpr during count operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 460 of 485 rej09b0244-0300 21.3.2.2 programmable waveform generation mode the following three workarounds should be performe d in programmable waveform generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) to change registers trbpre and trbpr during coun t operation (tcstf bit is set to 1), synchronize the trbo output cycle using a timer rb interrupt, etc. this operation should be preformed only once in the same output cycle. also, make sure that writi ng to the trbpr register does not occur during period a shown in figures 21.2 and 21.3. the following shows the detailed workaround examples. ? workaround example (a): as shown in figure 21.2, write to registers trbsc and trbpr in the timer rb interrupt routine. these write operations must be completed by the beginning of period a. figure 21.2 workaround example (a) when timer rb interrupt is used trbo pin output count source/ prescaler underflow signal primary period period a ir bit in trbic register secondary period (b) interrupt sequence instruction in interrupt routine interrupt request is acknowledged (a) interrupt request is generated ensure sufficient time set the secondary and then the primary register immediately (a) period between interrupt request generation and the completion of execution of an instruction. the length of time varies depending on the instruction being executed. the divx instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 461 of 485 rej09b0244-0300 ? workaround ex ample (b): as shown in figure 21.3 detect the start of the pr imary period by the trbo pin output level and write to registers trbsc and trbpr. these write operations must be completed by the beginning of period a. if the port register?s bit value is read after the port direction register?s bit corresponding to the trbo pin is set to 0 (input mode), the read value indicates the trbo pin output value. figure 21.3 workaround example (b) when trbo pin output value is read (3) to stop the timer counting in the primary period, use the tstop bit in the trbcr register. in this case, registers trbpre and trbpr are initialized and th eir values are set to the values after reset. 21.3.2.3 programmable one-shot generation mode the following two workarounds should be performe d in programmable one-shot generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously du ring count operation (tcstf bit is set to 1), allow three or more cycles of the co unt source for each write interval. ? when the trbpr register is writte n continuously during count operation (tcstf bit is set to 1), allow three or more cycles of the prescal er underflow for each write interval. (2) do not set both the trbpre and trbpr registers to 00h. trbo pin output count source/ prescaler underflow signal primary period period a read value of the port register?s bit corresponding to the trbo pin (when the bit in the port direction register is set to 0) secondary period (i) the trbo output inversion is detected at the end of the secondary period. ensure sufficient time upon detecting (i), set the secondary and then the primary register immediately. (ii) (iii) free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 462 of 485 rej09b0244-0300 21.3.2.4 programmable wait one-shot generation mode the following three workarounds should be performe d in programmable wait one-shot generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) do not set both the trbpre and trbpr registers to 00h. (3) set registers trbsc and trbp r using the following procedure. (a) to use ?int0 pin one-shot trigger enabled? as the count start condition set the trbsc register an d then the trbpr register. at this time, after writing to the trbpr register, allow an interval of 0.5 or more cycles of the count source before trigger input from the int0 pin. (b) to use ?writing 1 to tosst bit? as the start condition set the trbsc register, the trbpr register, and then tosst bit. at this time, after writing to the trbpr register, allow an interval of 0.5 or more cycles of the count source before writing to the tosst bit. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 463 of 485 rej09b0244-0300 21.3.3 notes on timer rd 21.3.3.1 trdstr register ? set the trdstr register using the mov instruction. ? when the cseli (i = 0 to 1) is set to 0 (the c ount stops at compare matc h of registers trdi and trdgrai), the count does not stop and the tstarti b it remains unchanged even if 0 (count stops) is written to the tstarti bit. ? therefore, set the tstarti bit to 0 to change ot her bits without changing the tstarti bit when the cseli bit is se to 0. ? to stop counting by a program, set the tstarti bit after setting the cseli bit to 1. although the cseli bit is set to 1 and the tstarti bit is set to 0 at the same time (with 1 instruction), the count cannot be stopped. ? table 21.1 lists the trdioji (j = a, b, c, or d) pin output level when count stops to use the trdioji (j = a, b, c, or d) pin with the timer rd output. 21.3.3.2 trdi register (i = 0 or 1) ? when writing the value to the trdi register by a program while the ts tarti bit in the trdstr register is set to 1 (count starts), avoid overlapping with the timing for setting the trdi register to 0000h, and then write. if the timing for setting the trdi register to 0000h overlaps with the timing for writing the value to the trdi register, the value is not written and the trdi register is set to 0000h. these precautions are applicable when selecting the following by bits cclr2 to cclr0 in the trdcri register. - 001b (clear by the trdi register at co mpare match with the trdgrai register.) - 010b (clear by the trdi register at co mpare match with the trdgrbi register.) - 011b (synchronous clear) - 101b (clear by the trdi register at co mpare match with the trdgrci register.) - 110b (clear by the trdi register at compare match with the trdgrdi register.) ? when writing the value to the trdi register and continuously reading the same register, the value before writing may be read. in this cas e, execute the jmp.b instruction between the writing and reading. program example mov.w #xxxxh, trd0 ;writing jmp.b l1 ;jmp.b l1: mov.w trd0,data ;reading 21.3.3.3 trdsri regi ster (i = 0 or 1) when writing the value to the trdsri register and con tinuously reading the same register, the value before writing may be read. in this cas e, execute the jmp.b instruction between the writing and reading. program example mov.b #xxh, trdsr0 ;writing jmp.b l1 ;jmp.b l1: mov.b trdsr0,data ;reading table 21.1 trdioji (j = a, b, c, or d) pin output level when count stops count stop trdioji pin output when count stops when the cseli bit is set to 1, set the tstarti bit to 0 and the count stops. hold the output level immediately before the count stops. when the cseli bit is set to 0, the count stops at compare match of registers trdi and trdgrai. hold the output level after output changes by compare match. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 464 of 485 rej09b0244-0300 21.3.3.4 count source switch ? switch the count source after the count stops. change procedure (1) set the tstarti (i = 0 or 1) bit in the trdstr register to 0 (count stops). (2) change bits tck2 to tck0 in the trdcri register. ? when changing the count source fr om foco40m to another source and stopping foco40m, wait 2 cycles of f1 or more after setting the clock switch, and then stop foco40m. change procedure (1) set the tstarti (i = 0 or 1) bit in the trdstr register to 0 (count stops). (2) change bits tck2 to tck0 in the trdcri register. (3) wait 2 or more cycles of f1. (4) set the fra00 bit in the fra0 register to 0 (high-speed on-chip oscillator stops). 21.3.3.5 input capture function ? set the pulse width of the input capture signal to 3 or more cycles of the timer rd operation clock (refer to table 14.11 timer rd operation clocks ). ? the value in the trdi register is transferred to the trdgrji register 2 to 3 cycles of the timer rd operation clock after the input capture signal is applied to the trdioji pin (i = 0 or 1, j = either a, b, c, or d) (no digital filter). 21.3.3.6 reset synchronous pwm mode ? when reset synchronous pwm mode is used for motor control, make sure ols0 = ols1. ? set to reset synchronous pwm mode by the following procedure: change procedure (1) set the tstart0 bit in the trdstr register to 0 (count stops). (2) set bits cmd1 to cmd0 in the trdfcr register to 00b (timer mode, pwm mode, and pwm3 mode). (3) set bits cmd1 to cmd0 to 01b (reset synchronous pwm mode). (4) set the other registers asso ciated with timer rd again. 21.3.3.7 complementary pwm mode ? when complementary pwm mode is used for motor control, make sure ols0 = ols1. ? change bits cmd1 to cmd0 in the trdf cr register in the following procedure. change procedure: when setting to complementary pwm mode (including re-set), or changing the transfer timing from the buffer register to the general register in complementary pwm mode. (1) set both the tstart0 and tstart1 bits in the trdstr register to 0 (count stops). (2) set bits cmd1 to cmd0 in the trdfcr register to 00b (timer mode, pwm mode, and pwm3 mode). (3) set bits cmd1 to cmd0 to 10b or 11b (complementary pwm mode). (4) set the registers associated with other timer rd again. change procedure: when st opping complementary pwm mode (1) set both the tstart0 and tstart1 bits in the trdstr register to 0 (count stops). (2) set bits cmd1 to cmd to 00b (timer mode, pwm mode, and pwm3 mode). ? do not write to trdgra0, trdgrb0, trdgra1, or trdgrb1 register during operation. when changing the pwm waveform, transfer the values written to registers trdgrd0, trdgrc1, and trdgrd1 to registers trdgrb0, trdgra1, and trdgrb1 using the buffer operation. however, to write data to the trdgrd0, trdgrc1, or trdgrd1 register, set bits bfd0, bfc1, and bfd1 to 0 (general register). after this, bits bf d0, bfc1, and bfd1 may be set to 1 (buffer register). the pwm period cannot be changed. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 465 of 485 rej09b0244-0300 ? if the value in the trdgra0 register is assumed to be m, the trd0 register counts m-1, m, m+1, m, m-1, in that order, when changing from increment to decr ement operation. when changing from m to m+1, the imfa bit is set to 1. also, bits cmd1 to cmd0 in the trdfcr register are set to 11b (complementary pwm mode, buffer data transferred at compare match between registers trd0 and trdgra0), the content in the buffer registers (trdgrd0, trdgrc1, and trdgrd1) is transferred to the general re gisters (trdgrb0, trdgra1, and trdgrb1). during m+1, m, and m-1 operation, the imfa bit remains unchanged and data are not transferred to registers such as the trdgra0 register. figure 21.4 operation at compare match between registers trd0 and trdgra0 in complementary pwm mode no change imfa bit in trdsr0 register transferred from buffer register trdgrb0 register trdgra1 register trdgrb1 register count value in trd0 register setting value in trdgra0 register m m+1 set to 0 by a program not transferred from buffer register when bits cmd1 to cmd0 in the trdfcr register are set to 11b (transfer from the buffer register to the general register at compare match of between registers trd0 and trdgra0). 1 0 free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 466 of 485 rej09b0244-0300 ? the trd1 register counts 1, 0, ffffh, 0, 1, in that order, wh en changing from decr ement to increment operation. the udf bit is set to 1 when changing between 1, 0, and ffffh operation. also, when bits cmd1 to cmd0 in the trdfcr register are set to 10b (com plementary pwm mode, buffer data transferred at underflow in the trd1 register), the content in the buffer registers (trdgrd0, trdgrc1, and trdgrd1) is transferred to th e general registers (trdgrb0, trdgra1, and trdgrb1). during ffffh, 0, 1 operation, data are not transferred to registers such as the trdgrb0 register. also, at this time, the ovf bit remains unchanged. figure 21.5 operation when trd1 register underflows in complementary pwm mode no change udf bit in trdsr0 register transferred from buffer register trdgrb0 register trdgra1 register trdgrb1 register count value in trd0 register set to 0 by a program not transferred from buffer register when bits cmd1 to cmd0 in the trdfcr register are set to 10b (transfer from the buffer register to the general register when the trd1 register underflows). ovf bit in trdsr0 register ffffh 1 0 1 0 0 1 free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 467 of 485 rej09b0244-0300 ? select with bits cmd1 to cmd0 the timing of data tr ansfer from the buffer register to the general register. however, transfer takes place with th e following timing in spite of the value of bits cmd1 to cmd0 in the following cases: value in buffer register value in trdgra0 register: transfer take place at unde rflow of the trd1 register. after this, when the buffer register is set to 0001h or above and a smaller value than the value of the trdgra0 register, and the trd1 register underflows for the first time after setting, the value is transferred to the general re gister. after that, the value is transferred with the timing selected by bits cmd1 to cmd0. figure 21.6 operation when value in buffer register value in trdgra0 register in complementary pwm mode 0000h trdgrd0 register trdiob0 output n3 n2 m+1 n3 n2 n1 n2 n1 n3 n2 n2 n1 n1 trdgrb0 register transfer at underflow of trd1 register because of n3 > m transfer at underflow of trd1 register because of first setting to n2 < m trdiod0 output m: value set in trdgra0 register the above applies under the following conditions: ? bits cmd1 to cmd0 in the trdfcr register are set to 11b (data in the buffer register is transferred at compare match between registers trd0 and trdgra0 in complementary pwm mode). ? both the osl0 and ols1 bits in the trdfcr register are set to 1 (active ?h? for normal-phase and counter-phase). count value in trd0 register count value in trd1 register transfer with timing set by bits cmd1 to cmd0 transfer with timing set by bits cmd1 to cmd0 transfer transfer transfer transfer free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 468 of 485 rej09b0244-0300 when the value in the buffer register is set to 0000h: transfer takes place at compare match between registers trd0 and trdgra0. after this, when the buffer register is set to 0001h or above and a smaller value than the value of the trdgra0 register, and a compare match occurs betw een registers trd0 and trdgra0 for the first time after setting, the value is transferred to the general register. after that, the value is transferred with the timing selected by bits cmd1 to cmd0. figure 21.7 operation when value in buffer regi ster is set to 0000h in complementary pwm mode 21.3.3.8 count source foco40m ? the count source foco40m can be used with supply voltage vcc = 3.0 to 5.5 v. for supply voltage other than that, do not set bits tck2 to tck0 in re gisters trdcr0 and trdcr to 110b (select foco40m as the count source). 0000h trdgrd0 register trdiob0 output n1 m+1 n2 n1 0000h n1 0000h n1 n1 n2 trdgrb0 register transfer transfer at compare match between registers trd0 and trdgra0 because content in trdgrd0 register is set to 0000h transfer at compare match between registers trd0 and trdgra0 because of first setting to 0001h n1 < m transfer with timing set by bits cmd1 to cmd0 trdiod0 output m: value set in trdgra0 register the above applies under the following conditions: ? bits cmd1 to cmd0 in the trdfcr register are set to 10b (data in the buffer register is transferred at underflow of the trd1 register in pwm mode). ? both the ols0 and ols1 bits in the trdfcr register are set to 1 (active ?h? for normal-phase and counter-phase). count value in trd0 register count value in trd1 register transfer with timing set by bits cmd1 to cmd0 transfer transfer transfer free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 469 of 485 rej09b0244-0300 21.3.4 notes on timer re 21.3.4.1 starting and stopping count timer re has the tstart bit for instructing the count to start or stop, and the tcstf bit, which indicates count start or stop. bits tstart an d tcstf are in the trecr1 register. timer re starts counting and the tcstf bit is set to 1 (count starts) when the tstart bit is set to 1 (count starts). it takes up to 2 cycles of the count source until the tcstf bit is set to 1 after setting the tstart bit to 1. during this time, do not access re gisters associated with timer re (1) other than the tcstf bit. also, timer re stops counting when setting the tstart bit to 0 (count stops) and the tcstf bit is set to 0 (count stops). it takes the time for up to 2 cycles of the count source until the tcstf bit is set to 0 after setting the tstart bit to 0. during this ti me, do not access registers associated with timer re other than the tcstf bit. note: 1. registers associated with timer re: tresec, tremin, trehr, trewk, trecr1, trecr2, and trecsr. 21.3.4.2 register setting write to the following registers or bits when timer re is stopped. ? registers tresec, tremin, trehr, trewk, and trecr2 ? bits h12_h24, pm, and int in trecr1 register ? bits rcs0 to rcs3 in trecsr register timer re is stopped when bits tstart and tcstf in the trecr1 register are set to 0 (timer re stopped). also, set all above-mentioned registers and bits (immedia tely before timer re count starts) before setting the trecr2 register. figure 21.8 shows a setting example in real-time clock mode. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 470 of 485 rej09b0244-0300 figure 21.8 setting example in real-time clock mode stop timer re operation tcstf in trecr1 = 0? tstart in trecr1 = 0 trerst in trecr1 = 1 trerst in trecr1 = 0 setting of registers trecsr, tresec, tremin, trehr, trewk, and bits h12_h24, pm, and int in trecr1 register setting of trecr2 tstart in trecr1 = 1 tcstf in trecr1 = 1? treic 00h (disable timer re interrupt) setting of treic (ir bit 0, select interrupt priority level) timer re register and control circuit reset select clock output select clock source seconds, minutes, hours, days of week, operating mode set a.m./p.m., interrupt timing select interrupt source start timer re operation free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 471 of 485 rej09b0244-0300 21.3.4.3 time reading proce dure of real-time clock mode in real-time clock mode, read registers tresec, tr emin, trehr, and trewk wh en time data is updated and read the pm bit in the trecr1 register when th e bsy bit is set to 0 (not while data is updated). also, when reading several registers, an incorrect time will be r ead if data is updated before another register is read after reading any register. in order to prevent this, use the reading procedure shown below. ? using an interrupt read necessary contents of regi sters tresec, tremin, trehr, a nd trewk and the pm bit in the trecr1 register in the timer re interrupt routine. ? monitoring with a program 1 monitor the ir bit in the treic regi ster with a program and read necessa ry contents of registers tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register after the ir bit in the treic register is set to 1 (timer re interrupt request generated). ? monitoring with a program 2 (1) monitor the bsy bit. (2) monitor until the bsy bit is set to 0 after the bsy bit is set to 1 (approximately 62.5 ms while the bsy bit is set to 1). (3) read necessary contents of re gisters tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register after the bsy bit is set to 0. ? using read results if they are the same value twice (1) read necessary contents of re gisters tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register. (2) read the same register as (1) and compare the contents. (3) recognize as the correct value if th e contents match. if the contents do not match, repeat until the read contents match with th e previous contents. also, when reading several registers, r ead them as continuously as possible. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 472 of 485 rej09b0244-0300 21.4 notes on serial interface ? when reading data from the uirb (i = 0 or 1) register eith er in the clock synchronous serial i/o mode or in the clock asynchronous serial i/o mode. ensu re the data is read in 16-bit units. when the high-order byte of the uirb register is read, bits per and fe r in the uirb register and the ri bit in the uic1 register are set to 0. to check receive errors, read the uirb register and then use the read data. example (when reading r eceive buffer register): mov.w 00a6h,r0 ; read the u0rb register ? when writing data to the uitb register in the clock asynchronous serial i/o mode with 9-bit transfer data length, write data to the high-order byte first then the low-order byte, in 8-bit units. example (when reading tran smit buffer register): mov.b #xxh,00a3h ; write the high-order byte of u0tb register mov.b #xxh,00a2h ; write the low-order byte of u0tb register free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 473 of 485 rej09b0244-0300 21.5 notes on clock sync hronous serial interface 21.5.1 notes on clock synchronous serial i/o with chip select set the iicsel bit in the pmr register to 0 (select clock synchronous serial i/o with chip select function) to use the clock synchronous serial i/o with chip select function. 21.5.2 notes on i 2 c bus interface set the iicsel bit in the pmr register to 1 (select i 2 c bus interface function) to use the i 2 c bus interface. 21.5.2.1 multimaster operation the following actions must be performed to use the i 2 c bus interface in multimaster operation. ? transfer rate set the transfer rate by 1/1.8 or faster than the fastes t rate of the other masters. for example, if the fastest transfer rate of the other masters is set to 400 kbps, the i 2 c-bus transfer rate in this mcu should be set to 223 kbps (= 400/1.18) or more. ? bits mst and trs in the iccr1 register setting (a) use the mov instruction to set bits mst and trs. (b) when arbitration is lost, confirm the contents of b its mst and trs. if the contents are other than the mst bit set to 0 and the trs bit set to 0 (slave recei ve mode), set the mst bit to 0 and the trs bit to 0 again. 21.5.2.2 master receive mode either of the following actions must be performed to use the i 2 c bus interface in ma ster receive mode. (a) in master receive mode while the rdrf bit in the icsr register is set to 1, read the icdrr register before the rising edge of the 8th clock. (b) in master receive mode, set the rcvd bit in th e iccr1 register to 1 (disables the next receive operation) to perform 1-byte communications. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 474 of 485 rej09b0244-0300 21.6 notes on hardware lin for the time-out processing of the head er and response fields, use another timer to measure the duration of time with a synch break detection interrupt as the starting point. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 475 of 485 rej09b0244-0300 21.7 notes on a/d converter ? write to each bit (other than bit 6) in the adcon0 register, each b it in the adcon1 register, or the smp bit in the adcon2 register when a/d conversi on is stopped (before a trigger occurs). ? when the vcut bit in the adcon1 register is changed from 0 (vref no t connected) to 1 (vref connected), wait for at least 1 s before starting the a/d conversion. ? after changing the a/d operating mode, select an analog input pin again. ? when using the one-shot mode, ensure that a/d conversion is completed before reading the ad register. the ir bit in the adic register or the adst bit in the ad con0 register can be used to determine whether a/d conversion is completed. ? when using the repeat mode, select the frequency of the a/d converter operating clock ad or more for the cpu clock during a/d conversion. do not select th e foco-f for the ad. ? if the adst bit in the adcon0 register is set to 0 (a /d conversion stops) by a program and a/d conversion is forcibly terminated duri ng an a/d conversion operatio n, the conversion result of the a/d converter will be undefined. if the adst bit is set to 0 by a program, do not use the value of the ad register. ? connect 0.1 f capacitor between the p4_2 /vref pin and avss pin. ? do not enter stop mode during a/d conversion. ? do not enter wait mode when the cm02 bit in the cm0 re gister is set to 1 (peripheral function clock stops in wait mode) during a/d conversion. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 476 of 485 rej09b0244-0300 21.8 notes on flash memory 21.8.1 cpu rewrite mode 21.8.1.1 operating speed before entering cpu rewrite mode (ew0 mode), select 5 mhz or below for the cpu clock using the cm06 bit in the cm0 register and bits cm16 to cm17 in the cm1 register. this does not apply to ew1 mode. 21.8.1.2 prohibited instructions the following instructions cannot be used in ew0 mode because they reference da ta in the flash memory: und, into, and brk. 21.8.1.3 interrupts table 21.2 lists the ew0 mode interrupts, and table 21.3 lists the ew1 mode interrupts. notes: 1. do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in rom. 2. do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. table 21.2 ew0 mode interrupts mode status when maskable interrupt request is acknowledged when watchdog ti mer, oscillation stop detection, voltage monitor 1, or voltage monitor 2 interrupt request is acknowledged ew0 during auto-erasure any interrupt can be used by allocating a vector in ram once an interrupt request is acknowledged, auto-programming or auto-erasure is fo rcibly stopped immediately and the flash memory is reset. interrupt handling starts after the fixed period and the flash memory restarts. since the block during auto- erasure or the address during auto- programming is forcibly stopped, the normal value may not be read. execute auto-erasure again and ensure it completes normally. since the watchdog timer does not stop during the command operation, interrupt requests may be generated. reset the watchdog timer regularly. auto-programming free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 477 of 485 rej09b0244-0300 notes: 1. do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in rom. 2. do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. table 21.3 ew1 mode interrupts mode status when maskable interrupt request is acknowledged when watchdog ti mer, oscillation stop detection, voltage monitor 1, or voltage monitor 2 interrupt request is acknowledged ew1 during auto-erasure (erase-suspend function enabled) auto-erasure is suspended after td(sr-sus) and interrupt handling is executed. auto- erasure can be restarted by setting the fmr41 bit in the fmr4 register to 0 (erase restart) after interrupt handling completes. once an interrupt request is acknowledged, auto-programming or auto-erasure is fo rcibly stopped immediately and the flash memory is reset. interrupt handling starts after the fixed period and the flash memory restarts. since the block during auto- erasure or the address during auto- programming is forcibly stopped, the normal value may not be read. execute auto-erasure again and ensure it completes normally. since the watchdog timer does not stop during the command operation, interrupt requests may be generated. reset the watchdog timer regularly using the erase-suspend function. during auto-erasure (erase-suspend function disabled) auto-erasure has priority and the interrupt request acknowledgement is put on standby. interrupt handling is executed after auto-erasure completes. during auto- programming (program suspend function enabled) auto-programming is suspended after td(sr-sus) and interrupt handling is executed. auto-programming can be restarted by setting the fmr42 bit in the fmr4 register to 0 (program restart) after interrupt handling completes. during auto- programming (program suspend function disabled) auto-programming has priority and the interrupt request acknowledgement is put on standby. interrupt handling is executed after auto-programming completes. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 478 of 485 rej09b0244-0300 21.8.1.4 how to access write 0 before writing 1 when setting the fmr01, fmr02, or fmr11 bit to 1. do not generate an interrupt between writing 0 and 1. 21.8.1.5 rewriting user rom area in ew0 mode, if the supply voltage drops while rewr iting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. in this case, use standard serial i/o mode. 21.8.1.6 program do not write additions to th e already programmed address. 21.8.1.7 entering stop mode or wait mode do not enter stop mode or wait mode during erase-suspend. 21.8.1.8 program and erase voltage for flash memory to perform programming and erasure, use vcc = 2.7 to 5.5 v as the supply voltage. do not perform programming and erasure at less than 2.7 v. free datasheet http:///
r8c/24 group, r8c/25 group 21. usage notes rev.3.00 feb 29, 2008 page 479 of 485 rej09b0244-0300 21.9 notes on noise 21.9.1 inserting a bypass capacitor between vcc and vss pins as a countermeasure against noise and latch-up connect a bypass capacitor (at least 0.1 f) using the shortest and thickest write possible. 21.9.2 countermeasures against noise er ror of port control registers during rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the capacity of the mcu's internal noise control circuitry. in such cases the contents of the port related registers may be changed. as a firmware countermeasure, it is recommended that the port registers, port direc tion registers, and pull-up control registers be reset periodically. however, examin e the control processing fully before introducing the reset routine as conflicts may be created betw een the reset routine and interrupt routines. free datasheet http:///
r8c/24 group, r8c/25 group 22. notes on on-chip debugger rev.3.00 feb 29, 2008 page 480 of 485 rej09b0244-0300 22. notes on on-chip debugger when using the on-chip debugger to develop and debug pr ograms for the r8c/24 group and r8c/25 group take note of the following. (1) do not access the related uart1 registers. (2) some of the user flash memory and ram areas ar e used by the on-ship debugger. these areas cannot be accessed by the user. refer to the on-chip debugger manual for which areas are used. (3) do not set the address match interrupt (registers aier, rmad0, and rmad1 and fixed vector tables) in a user system. (4) do not use the brk instruction in a user system. (5) debugging is available under the condition of supply voltage vcc = 2.7 to 5.5 v. debugging with the on-chip debugger under less than 2.7 v is not allowed. connecting and using the on-chip debugger has some special restrictions. refer to the on-chip debugger manual for details. free datasheet http:///
r8c/24 group, r8c/25 group appendix 1. package dimensions rev.3.00 feb 29, 2008 page 481 of 485 rej09b0244-0300 appendix 1. package dimensions diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas technology website. include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. detail f c a l1 l a2 a1 index mark x y * 3 * 1 * 2 f 39 27 13 1 40 52 26 14 zd ze d hd e he bp terminal cross section c bp c1 b1 previous code jeita package code renesas code plqp0052ja-a 52p6a-a mass[typ.] 0.3g p-lqfp52-10x10-0.65 1.0 0.125 0.30 1.1 1.1 0.13 0.20 0.145 0.09 0.37 0.32 0.27 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.65 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 e under development 0.15 v 0.20 w previous code jeita package code renesas code ptlg0064ja-a 64f0g mass[typ.] 0.07g p-tflga64-6x6-0.65 0.08 0.47 0.43 0.39 max nom min dimension in millimeters symbol reference 6.0 d 6.0 e 1.05 a x 0.65 e 0.10 y b 1 b 0.31 0.35 0.39 b w s w a s a h g f e d c b 12345678 s ys ab index mark sab v x4 (laser mark) index mark d e a b 1 b e e free datasheet http:///
r8c/24 group, r8c/25 group appendix 2. connection ex amples between serial writer and on-chip debugging rev.3.00 feb 29, 2008 page 482 of 485 rej09b0244-0300 appendix 2. connection examples b etween serial writer and on-chip debugging emulator appendix figure 2.1 shows a connection example with m16c flash starter (m3a-0806), and appendix figure 2.2 shows a connection example with e8 emulator (r0e000080kce00). appendix figure 2.1 connection example with m16c flash starter (m3a-0806) appendix figure 2.2 connection example with e8 emulator (r0e000080kce00) vss vcc rxd 4 7 vss 1 vcc 10 m16c flash starter (m3a-0806) rxd txd txd reset mode note: 1. an oscillation circuit must be connected, even when operating with the on-chip oscillator clock. connect oscillation circuit (1) 52 r8c/24 group r8c/25 group 51 50 49 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 32 33 34 35 36 37 38 39 27 40 e8 emulator (r0e000080kce00) mode reset 12 10 8 6 4 2 vss 13 7 mode vcc 14 vss vcc note: 1. it is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. connect oscillation circuit (1) 52 r8c/24 group r8c/25 group 51 50 49 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 32 33 34 35 36 37 38 39 27 40 4.7k ? 10% 4.7k ? or more open collector buffer user logic free datasheet http:///
r8c/24 group, r8c/25 group a ppendix 3. example of osc illation evaluation circuit rev.3.00 feb 29, 2008 page 483 of 485 rej09b0244-0300 appendix 3. example of osc illation evaluation circuit appendix figure 3.1 shows an example of oscillation evaluation circuit. appendix figure 3.1 example of oscillation evaluation circuit vss connect oscillation circuit vcc reset note: 1. after reset, the xin and xcin clocks stop. write a program to oscilla te the xin and xcin clocks. 52 51 50 49 48 47 46 45 44 43 42 41 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 32 33 34 35 36 37 38 39 27 40 connect oscillation circuit r8c/24 group r8c/25 group free datasheet http:///
rev.3.00 feb 29, 2008 page 484 of 485 rej09b0244-0300 r8c/24 group, r8c/25 group index [ a ] ad ....................................................................................... 386 adcon0 ............................................................................. 385 adcon1 ............................................................................. 386 adcon2 ............................................................................. 386 adic .................................................................................... 106 aier .................................................................................... 121 [ c ] cm0 ....................................................................................... 75 cm1 ....................................................................................... 76 cpsrf .................................................................................. 80 cspr .................................................................................. 129 [ f ] fmr0 .................................................................................. 406 fmr1 .................................................................................. 407 fmr4 .................................................................................. 408 fra0 ..................................................................................... 78 fra1 ..................................................................................... 78 fra2 ..................................................................................... 79 fra4 ..................................................................................... 79 fra6 ..................................................................................... 79 fra7 ..................................................................................... 79 [ i ] iccr1 ................................................................................. 338 iccr2 ................................................................................. 339 icdrr ................................................................................. 344 icdrs ................................................................................. 344 icdrt ................................................................................. 343 icier ................................................................................... 341 icmr ................................................................................... 340 icsr .................................................................................... 342 iicic .................................................................................... 107 int0ic ................................................................................. 108 int1ic ................................................................................. 108 inten ................................................................................. 115 intf .................................................................................... 116 [ k ] kien .................................................................................... 119 kupic ................................................................................. 106 [ l ] lincr ................................................................................. 370 linst .................................................................................. 371 [ o ] ocd ...................................................................................... 77 ofs ....................................................................... 27, 128, 401 [ p ] p2drr .................................................................................. 58 pdi (i = 0 to 4 and 6) ............................................................. 56 pi (i = 0 to 4 and 6) ................................................................ 56 pm0 ....................................................................................... 71 pm1 ....................................................................................... 71 pmr .............................................................. 58, 293, 314, 344 prcr .................................................................................. 100 pur0 ..................................................................................... 57 pur1 .....................................................................................57 [ r ] rmad0 ................................................................................121 rmad1 ................................................................................121 [ s ] s0ric ..................................................................................106 s0tic ...................................................................................106 s1ric ..................................................................................106 s1tic ...................................................................................106 sar ......................................................................................343 sscrh ................................................................................308 sscrl .................................................................................309 sser ...................................................................................311 ssmr ...................................................................................310 ssmr2 .................................................................................313 ssrdr ................................................................................314 sssr ...................................................................................312 sstdr .................................................................................314 ssuic ..................................................................................107 [ t ] tra ......................................................................................136 tracr .................................................................................135 traic ..................................................................................106 traioc .......................................135, 137, 140, 142, 144, 147 tramr ................................................................................136 trapre ..............................................................................136 trbcr .................................................................................151 trbic ..................................................................................106 trbioc ...............................................152, 154, 158, 160, 165 trbmr ................................................................................152 trbocr ..............................................................................151 trbpr .................................................................................153 trbpre ..............................................................................153 trbsc .................................................................................153 trd0 ............................................192, 207, 222, 233, 245, 258 trd0ic ................................................................................107 trd1 ............................................................192, 207, 222, 245 trd1ic ................................................................................107 trdcr0 ......................................188, 203, 219, 231, 242, 256 trdcr1 ......................................................188, 203, 219, 242 trddf0 ...............................................................................187 trddf1 ...............................................................................187 trdfcr ......................................186, 200, 217, 229, 240, 253 trdgrai (i = 0 to 1) ....................193, 208, 223, 234, 245, 259 trdgrbi (i = 0 to 1) ....................193, 208, 223, 234, 245, 259 trdgrci (i = 0 to 1) ...................193, 208, 223, 234, 245, 259 trdgrdi (i = 0 to 1) ...................193, 208, 223, 234, 245, 259 trdier0 ......................................192, 207, 221, 233, 244, 258 trdier1 ......................................192, 207, 221, 233, 244, 258 trdiora0 ...................................................................189, 204 trdiora1 ...................................................................189, 204 trdiorc0 ...................................................................190, 205 trdiorc1 ...................................................................190, 205 trdmr ........................................184, 198, 215, 228, 239, 252 trdocr ..............................................................202, 219, 255 trdoer1 ............................................201, 218, 230, 241, 254 trdoer2 ............................................201, 218, 230, 241, 254 trdpmr ..............................................................185, 199, 216 trdpocr0 .........................................................................222 trdpocr1 .........................................................................222 trdsr0 .......................................191, 206, 220, 232, 243, 257 index free datasheet http:///
rev.3.00 feb 29, 2008 page 485 of 485 rej09b0244-0300 r8c/24 group, r8c/25 group index trdsr1 ...................................... 191, 206, 220, 232, 243, 257 trdstr ...................................... 184, 198, 215, 228, 238, 252 trecr1 ...................................................................... 275, 282 trecr2 ...................................................................... 276, 282 trecsr ..................................................................... 277, 283 trehr ................................................................................ 274 treic ................................................................................. 106 tremin ...................................................................... 273, 281 tresec ...................................................................... 273, 281 trewk ............................................................................... 274 [ u ] u0brg ................................................................................ 291 u0c0 ................................................................................... 292 u0c1 ................................................................................... 293 u0mr .................................................................................. 291 u0rb ................................................................................... 290 u0tb ................................................................................... 290 u1brg ................................................................................ 291 u1c0 ................................................................................... 292 u1c1 ................................................................................... 293 u1mr .................................................................................. 291 u1rb ................................................................................... 290 u1sr ................................................................................... 293 u1tb ................................................................................... 290 [ v ] vca1 ..................................................................................... 36 vca2 ............................................................................... 36, 80 vw0c .................................................................................... 37 vw1c .................................................................................... 38 vw2c .................................................................................... 39 [ w ] wdc .................................................................................... 128 wdtr ................................................................................. 129 wdts .................................................................................. 129 free datasheet http:///
c - 1 revision history r8c/24 group, r8c/25 group hard ware manual rev. date description page summary 0.10 jul 27, 2005 ? first edition issued 0.20 jan 16, 2006 all pages ? ?preliminary? deleted ? symbol name ?trdmdr? ?trdmr?, ?ssuaic? ?ssuic?, ?iic2aic? ?iicic?, and ?tstop0, tstop1? ?csel0, csel1? revised ?pin name ?tclk? ?trdclk? revised ? bit name ?tpsc0 to tpsc2? ?tck0 to tck2?, ?trd0 count stop bit? ?trd0 count operation select bit?, and ?trd1 count stop bit? ?trd1 count operation select bit? revised 2 table 1.1 functions and specifications for r8c/24 group revised 3 table 1.2 functions and specifications for r8c/25 group revised 4 figure 1.1 block diagram; ?peripheral functions? added, ?system clock generation? ?system clock generator? revised 5 table 1.3 product information for r8c/24 group revised 6 table 1.4 product information of r8c/25 group revised 7 figure 1.4 pin assignment (top view); ?vss? ?vss/avss? and ?vcc? ?vcc/avcc? revised 8 table 1.5 pin functions; ?analog power supply input? added, ?reference voltage input? revised 9 table 1.6 pin name information by pin number ?vss? ?vss/avss? and ?vcc? ?vcc/avcc? revised 10 figure 2.1 cpu registers; ?reserved area? ?reserved bit? revised 12 2.8.10 reserved area; ?reserved area? ?reserved bit? revised 13 figure 3.1 memory map of r8c/24 group; ?program area? ?program rom? revised 14 3.2 r8c/25 group, figure 3.2 memory map of r8c/25 group; ?data area? ?data flash?, ?program area? ?program rom? revised 15 table 4.1 sfr information(1); 0012h: ?x0h? ?00h? 0016h: ?x0h? ?00h? 0024h: ?tbd? ?when shipping? notes 3 and 4 revised 24 figure 5.4 ofs register; note1 revised and note3 added 25 5.1.1 when power supply is stable (2) revised 5.1.2 power on (4) revised 26 figure 5.5 example of hardware reset circuit and operation and figure 5.6 example of hardware reset circuit (usage example of external supply voltage detection circuit) and operation revised r8c/24 group, r8c/25 group hard ware manual revision history free datasheet http:///
c - 2 revision history r8c/24 group, r8c/25 group hard ware manual 0.20 jan 16, 2006 27 5.2 power-on reset function ?when a capacitor is ... or more.? added figure 5.7 example of power-on reset circuit and operation revised 28 5.4 voltage monitor 1 reset; ?when ... vcc pin drops the vdet1 ...? ?when ... vcc pin reaches to the vdet1 ...? revised 30 to 67 ?6. programmable i/o ports? ?6. voltage detection circuit? and ?7. voltage detection circuit? ?7. programmable i/o ports? revised 33 figure 6.5 registers vca1 and vca2; vca2 register revised 34 figure 6.6 vw0c register revised 46 figure 7.2 configuration of programmable i/o ports (2) revised 47 figure 7.3 configuration of programmable i/o ports (3) revised 49 figure 7.5 configuration of programmable i/o ports (5) revised 50 figure 7.6 configuration of programmable i/o ports (6) revised 51 figure 7.7 configuration of programmable i/o ports (7) revised 56 to 66 7.4 port setting added; table 7.4 port p0_0/an7 to table 7.47 port p6_7/int3 /rxd1 added 67 table 7.48 unassigned pin handling revised 69 9. bus revised; ?however, only following sfrs are ... accessed at a time.? added table 9.2 bus cycles by access space of the r8c/25 group added, table 9.3 access unit and bus operations; ?sfr? ?sfr, data flash?, ?rom/ram? ?rom (program rom), ram? revised 71 figure 10.1 clock generation circuit revised 72 figure 10.2 cm0 register revised 73 figure 10.3 cm1 register revised 75 figure 10.5 registers fra0 and fra1; fra0 register revised 77 figure 10.8 vca2 register added 78 figure 10.9 examples of xin clock connection circuit revised 79 10.2.2 high-speed on -chip oscillator clock; ?to use the high-speed on-chip ... or more).? added 80 10.3 xcin clock ?to input an external clock ... pin open.? added 81 10.4.2 cpu clock ?use the xcin clock while ... stabilizes.? added 10.4.3 peripheral function clock (f 1, f2, f4, f8, f32, fc4, and fc32); ?use fc4 and fc32 while the xcin cl ock oscillation stabilizes.? added 10.4.5 foco40m; ?foco40m can be ... supply voltage vcc = 3.0 to 5.5 v.? added 10.4.8 foco128 added 82 table 10.2 settings and modes of clock associated bits revised rev. date description page summary free datasheet http:///
c - 3 revision history r8c/24 group, r8c/25 group hard ware manual 0.20 jan 16, 2006 83 10.5.1.2 low-speed clock mode; ?in this mode, stopping the xin clock ... the vca20 bit.? added 10.5.1.4 low-sp eed on-chip oscillator mode; ?in this mode, stopping the xin clock ... the vca20 bit.? added 84 figure 10.11 handling procedure of internal power low consumption enabled by vca20 bit added 88 figure 10.12 state transition in power control mode revised 89 10.6.1 how to use oscillati on stop detection function; ? ? this function cannot be.. . is 2 mhz or below. ...? ? ? this function cannot be... is below 2 mhz. ...? revised 92 10.7.1 stop mode and 10.7.2 wait mode 10.7.1 stop mode and wait mode revised 10.7.3 oscillation stop detection function; ?since ... is 2 mhz or below, ...? ?since ... is below 2 mhz. ...? revised ?to use this mcu with supply voltage ... to the chip externally.? added 10.7.4 foco40m added 107 figure 12.11 interrupt priority level judgement circuit; note2 deleted 114 figure 12.18 registers aier and rmad0 to rmad1; aier and rmad0 to rmad1 register revised 119 12.6.7 entering wait mode after osc illation stop detection interrupt is detected added 121 figure 13.2 registers ofs and wdc; ofs register note1 revised and note3 added, and wdc register note1 deleted 126 table 14.1 functional comparison of timers; input pin: timer rd ?trdclk? added 127 figure 14.1 block diagram of timer ra revised 135 table 14.3 pulse output mode specifications revised 142 table 14.6 pulse period measurem ent mode specifications revised 144 figure 14.11 operating example of pu lse period measurement mode revised 146 figure 14.12 block diagram of timer rb revised 147 figure 14.13 registers trbcr and tr bocr; trbocr register revised 149 figure 14.15 registers trbpre, trbsc, and trbpr; trbpr register revised 158 figure 14.20 trbioc register in programmable one-shot generation mode figure 14.23 registers trbioc and trbmr in programmable one- shot generation mode; trbioc register note2 revised 162 figure 14.25 register s trbioc and trbmr in programmable wait one-shot generation mode; trbioc register note2 revised 165 -output compare function; ?(pin output can be changed at detection)? added rev. date description page summary free datasheet http:///
c - 4 revision history r8c/24 group, r8c/25 group hard ware manual 0.20 jan 16, 2006 166 to 168 tables 14.12 pin functions trdioa0/trdclk(p2_0) tables 14.13 pin functions trdiob0(p2_1) tables 14.14 pin functions trdioc0(p2_2) tables 14.15 pin functions trdiod0(p2_3) tables 14.16 pin functions trdioa1(p2_4) tables 14.17 pin functions trdiob1(p2_5) tables 14.18 pin functions trdioc1(p2_6) tables 14.19 pin functions trdiod1(p2_7) tables 14.20 pin functions int0(p4_5) added 170 14.3.1 mode selection deleted 170 table 14.21 count source selection revised 14.3.1 count sources; ?trdcri register to ...? ?trdcri register (i = 0 or 1) to ...? revised 171 figure14.29 buffer operation in input capture function revised 172 figure14.30 buffer operation in output capture function revised 14.3.2 buffer operation; ?input capture and ...? ?timer mode (input capture and ...? ?the ioc2 to ioc0 bits in ...? ?the ioc2 bit in ...? ?the ioa2 to ioa0 bits in ...? ?the ioa2 bit in ...? ?the iod2 to iod0 bits in ...? ?the iod2 bit in ...? ?the iob2 to ioc0 bits in ...? ?the iob2 bit in ...? revised ?bits imfc and imfd in the trdsri ...input capture function.? added 173 14.3.3 synchronous operation; ?for the synchronous operation, ... register = 110b).? deleted 174 14.3.4 pulse output forced cutoff; ?p2d? ?pd2?, ?p4d? ?pd4?, and ?p4_5? ?pd4_5?, revised ?according to the selection ... details of interrupts.? added 176 14.3.5 input ca pture function; ?the trdgra0 register can also ... trigger input.? added figure 14.33 block diagram of input capture function revised 177 table 14.23 specifications of input capture function revised 178 figure 14.34 registers trdstr and trdmr in input capture function revised 179 figure 14.35 trdpmr register in input capture function revised 180 figure 14.36 trdfcr register in input capture function revised 183 figure 14.39 registers trdiora0 to trdiora1 in input capture function revised 184 figure 14.40 register s trdiorc0 to trdiorc1 in input capture function revised 185 figure 14.41 registers trdsr0 to trdsr1 in input capture function revised 187 table 14.25 input pin function in input capture function deleted 189 14.3.5.1 digital filter; ?trddf register ...? ?trddfi register ...? revised rev. date description page summary free datasheet http:///
c - 5 revision history r8c/24 group, r8c/25 group hard ware manual 0.20 jan 16, 2006 192 figure 14 .48 registers trdstr and trdmr in output compare function revised 193 figure 14.49 trdpmr register in output compare function revised 194 figure 14.50 trdfcr register in output compare function revised 195 figure 14.51 registers trdoer1 to trdoer2 in output compare function; trdoer2 register: note1 added 198 figure 14.54 registers trdiora0 to trdiora1 in output compare function revised 199 figure 14.55 registers trdiorc0 to trdiorc1 in output compare function revised 200 figure 14.56 registers trdsr0 to trdsr1 in output compare function revised 209 figure 14.64 registers trdstr and trdmr in pwm mode revised 210 figure 14.65 trdpmr register in pwm mode revised 211 figure 14.66 trdfcr register in pwm mode revised 212 figure 14.67 registers trdoer 1 to trdoer2 in pwm mode; trdoer2 register: note1 added 214 figure 14.69 registers trdsr0 to trdsr1 in pwm mode revised 222 figure 14.77 registers trdstr to trdmr in reset synchronous pwm mode revised 223 figure 14.78 trdfcr register in reset synchronous pwm mode revised 224 figure 14.79 registers trdoer1 to trdoer2 in reset synchronous pwm mode; trdoer2 register: note1 added 226 figure 14.81 registers trdsr0 to trdsr1 in reset synchronous pwm mode revised 232 figure 14.87 trdstr register in complementary pwm mode revised 233 figure 14.88 trdmr register in complementary pwm mode revised 234 figure 14.89 trdfcr register in complementary pwm mode revised 235 figure 14.90 registers trdoer1 to trdoer2 in complementary pwm mode; trdoer2 register: note1 added 237 figure 14.92 registers trdsr0 to trdsr1 in complementary pwm mode revised 244 figure 14.98 block diagram of pwm3 mode revised 245 table 14.33 specifications of pwm3 mode revised 246 figure 14.99 trdstr register in pwm3 mode revised 247 figure 14.100 trdmr register in pwm3 mode revised 248 figure 14.101 trdfcr register in pwm3 mode revised rev. date description page summary free datasheet http:///
c - 6 revision history r8c/24 group, r8c/25 group hard ware manual 0.20 jan 16, 2006 249 figure 14.102 registers trdoer1 to trdoer2 in pwm3 mode; trdoer2 register: note1 added 251 figure 14.104 trdcr0 register in pwm3 mode note1 deleted 252 figure 14.105 trdsr0 register in pwm3 mode revised 253 figure 14.106 trdier0 register in pwm3 mode revised 255 table 14.34 trdgrji register functions in pwm3 mode revised 256 figure 14.109 operating example of pwm3 mode revised 259 14.3.12.1 trdstr register (i = 0 or 1) added 260 14.3.12.4 ?count clock source switch? ?count source switch? revised 264 14.3.12.9 count source foco40m added 275 table 14.39 output compare mode specifications revised 281 figure 14.132 setting example in real-time clock mode revised 285 figure 15.3 registers u0tb to u1tb and u0rb to u1rb revised 286 figure 15.4 registers u0brg to u1brg and u0mr to u1mr; u0brg to u1brg register revised 287 figure 15.5 registers u0c0 to u1c0 note1 added 295 table 15.5 registers used and settings for uart mode; uibrg: ? ? ? ?0 to 7? revised 300 table 16.1 mode selections revised 358 figure 16.46 example of register setting in master transmit mode (clock synchronous serial mode); ? ? set the iicsel bit in the pmr register to 1? added 377 table 18.1 performance of a/d converter revised 378 figure 18.1 block diagram of a/d converter; ?vss? ?avss? and ?vref? ?vcom? revised 387 to 389 18.4 a/d conversion cycles to 18.6 inflow current bypass circuit added 390 18.7 notes on a/d converter ? ? connect 0.1 f capacitor ... vss pin.? ? ? connect 0.1 f capacitor ... avss pin.? revised 391 table 19.1 flash memory version performance; ? program and erase endurance:(program area) (program rom), (data area) (data flash) revised ? note3 added 392 19.2 memory map; ?the user rom ... area ... block a and b.? ?the user rom ... area (program rom) ... block a and b (data flash).? revised figure 19.1 flash memory block diagram for r8c/24 group revised 393 figure 19.2 flash memory block diagram for r8c/25 group revised 395 figure 19.4 ofs register; note1 revised and note3 added 398 19.4.2.4 fmstp bit revised rev. date description page summary free datasheet http:///
c - 7 revision history r8c/24 group, r8c/25 group hard ware manual 0.20 jan 16, 2006 399 19.4.2.16 fmr47 bit revised 402 figure 19.7 fmr4 register note4 revised 405 figure 19.11 process to reduce po wer consumption in high-speed on- chip oscillator mode, lo w-speed on-chip oscilla tor mode (xin clock stops) and low-speed clock mode (xin clock stops) revised 408 19.4.3.5 block erase; ?the block erase command cannot be ... program-suspend.? added 409 figure 19.14 block erase comm and (when using erase-suspend function) revised 412 figure 19.15 full status check and handling procedure for individual errors revised 414 figure 19.16 pin connections for standard serial i/o mode revised 419 19.7.1.9 program and erase voltage for flash memory added 420 table 20.1 absolute maximum ratings; ?v cc ? ?v cc /av cc ? revised table 20.2 recommended operating conditions revised 421 table 20.3 a/d converter characteristics revised 422 table 20.4 flash memory (program rom) electrical characteristics revised 423 table 20.5 flash memory (data flash bl ock a, block b) electrical revised 424 table 20.6 voltage detection 0 circui t electrical characteristics revised table 20.7 voltage detection 1 circui t electrical characteristics revised table 20.8 voltage detection 2 circui t electrical characteristics revised 425 table 20.9 reset circuit electrical characteristics (when using voltage monitor 0 reset) note2 revised 426 table 20.11 high-speed on-chi p oscillator circuit electrical characteristics revised table 20.12 low-spee d on-chip oscillator circuit electrical characteristics revised table 20.13 power supply circui t timing characteristics revised 427 table 20.14 timing requirements of clock synchronous serial i/o with chip select revised 431 table 20.15 timing requirements of i 2 c bus interface note1 revised 432 table 20.16 electrical characteristics (1) [v cc = 5 v] revised 433 table 20.17 electrical characteristics (2) [v cc = 5 v] revised 434 table 20.18 xin input, xcin input revised 435 table 20.20 serial interface revised 436 table 20.22 electrical characteristics (3) [v cc = 3 v] revised 437 table 20.23 electrical characteristics (4) [vcc = 3 v] revised 438 table 20.24 xin input, xcin input revised 439 table 20.26 serial interface revised 440 table 20.28 electrical characteristics (5) [v cc = 2.2 v] revised rev. date description page summary free datasheet http:///
c - 8 revision history r8c/24 group, r8c/25 group hard ware manual 0.20 jan 16, 2006 441 table 20.29 electrical characteristics (6) [vcc = 2.2 v] revised 442 table 20.30 xin input, xcin input revised table 20.31 traio input, int1 input revised 443 table 20.32 serial interface revised table 20.33 external interrupt inti (i = 0, 2, 3) input 444 21.1.1 stop mode and 21.1.2 wait mode 21.1.1 stop mode and wait mode revised 21.1.3 oscillation stop detection function; ?since ... is 2 mhz or below, ...? ?since ... is below 2 mhz. ...? revised ?to use this mcu with supply voltage ... to the chip externally.? added 21.1.4 foco40m added 447 21.2.7 entering wait mode after osc illation stop detection interrupt is detected added 462 21.7 notes on a/d converter ? ? connect 0.1 f capacitor ... vss pin.? ? ? connect 0.1 f capacitor ... avss pin.? revised 465 21.8.1.9 program and erase voltage for flash memory added 467 22. notes for on-chip debugger; (1) and (6) added, ?(2) do not use addresses ... addresses.? deleted 468 appendix 1. package dimensions; ?tbd? ?plqp0052ja-a (52p6a-a)? added 469 appendix figure 2.1 connection example with m16c flash starter (m3a-0806) revised appendix figure 2.2 connection example with e8 emulator (r0e000080kce00) revised 470 appendix figure 3.1 example of osc illation evaluation circuit revised 1.00 may 31, 2006 all pages ?under development? deleted 3 table 1.2 functions and specifications for r8c/25 group revised 4 figure 1.1 block diagram; ?system clock generator? ?system clock generation circuit? revised 5 to 6 table 1.3 product information for r8c/24 group and table 1.4 product information for r8c/25 group; a part of (d) mark is deleted. 9 table 1.6 pin name information by pin number note1 added 15 table 4.1 sfr information(1); 001ch: ?00h? ?00h, 10000000b? revised 0029h: high-speed on-chip oscillator cont rol register 4 fra4 when shipping added 002bh: high-speed on-chip oscillator c ontrol register 6 fra6 when shipping added note6 added 19 table 4.5 sfr information(5); 0118h: timer re second data register / counter data register, 0119h: timer re minute data r egister / compare data register register name revised rev. date description page summary free datasheet http:///
c - 9 revision history r8c/24 group, r8c/25 group hard ware manual 1.00 may 31, 2006 20 table 4.6 sfr information(6); 0143h: ?11000000b? ?11100000b? revised 24 figure 5.4 ofs register note2 revised 25 5.1.1 when power supply is stable (2) revised 5.1.2 power on (4) revised 26 figure 5.5 example of hardware reset circuit and operation and figure 5.6 example of hardware reset circuit (usage example of external supply voltage detection circuit) and operation revised 27 figure 5.7 example of power-on reset circuit and operation revised 28 5.3 voltage monitor 0 reset revised 33 figure 6.5 registers vca1 and vca2; vca2 register note6 revised 45 to 51 figures 7.1 to .7.7 configuration of programmable i/o ports note1 added 53 figure 7.9 pdi (i = 0 to 4 and 6) registers note3 added 54 figure 7.11 registers pur0 and pur1; after reset revised 62 table 7.31 port p3_4/sda/scs revised 70 table 10.1 specifications of clock generation circuit revised 71 figure 10.1 clock generation circuit revised 72 figure 10.2 cm0 register; note6 deleted and note9 revised 74 figure 10.4 ocd register revised 75 figure 10.5 registers fra0 and fra1; fra0 register note2 revised 76 figure 10.6 registers fra2, fra4, and fra6; fra2 register note2 deleted, registers fra4 and fra6 added 77 figure 10.8 vca2 register note6 revised 78 figure 10.9 examples of xin clock connection circuit note1 revised 79 10.2.2 high-speed on-chi p oscillator clock revised 81 10.4.3 peripheral func tion clock (f1, f2, f4, f8, and f32) revised 82 10.4.9 fc4 and fc32 added 83 table 10.2 settings and modes of clock associated bits revised 84 10.5.1.2 low-speed clock mode revised 85 10.5.2.2 entering wait mode and 10.5.2.3 pin status in wait mode revised 86 10.5.2.4 exiting wait mode; ?when using a peripheral ...instr uction is executed.? page changed table 10.3 interrupts to exit wait mode and usage conditions revised 87 10.5.2.4 exiting wait mode; ?when exiting by a peripheral .. . cpu clock supply is started.? ?when exiting by a peripheral ... cm07 bit in the cm0 register.? revised figure 10.11 time between wait mode and interrupt routine execution added 88 10.5.2.5 reducing the internal power consumption added figure 10.12 handling pr ocedure of internal power low consumption enabled by vca20 bit revised rev. date description page summary free datasheet http:///
c - 10 revision history r8c/24 group, r8c/25 group hard ware manual 1.00 may 31, 2006 89 table 10.4 interrupts to exit stop mode and usage conditions revised 90 figure 10.13 time between stop mo de and interrupt routine execution added 92 10.6.1 how to use oscillation stop detection function revised 93 figure 10.15 procedure for switching clock source from low-speed on-chip oscillator to xin clock revised 94 figure 10.16 example of determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, or voltage monitor 2 interrupt revised 95 10.7.1 stop mode and wait mode re vised and 10.7.4 foco40m deleted 97 figure 12.1 interrupts revised 107 table 12.5 ipl value when software or special interrupt is acknowledged revised 109 figure 12.10 priority levels of hardware interrupts revised 122 12.6.7 entering wait mode after osc illation stop detection interrupt is detected deleted 123 figure 13.1 block diagram of watchdog timer revised 124 figure 13.2 registers ofs and wdc; ofs register note2 revised 128 14. timers; ?the count source for each timer ... and reloading.? deleted 130 14.1 timer ra; ?the count source fo r timer ra ... and reloading.? added figure 14.1 block diagram of timer ra revised 131 figure 14.2 registers tracr and traioc revised 132 figure 14.3 registers tramr, trapre, and tra revised 133 table 14.2 timer mode specifications revised figure 14.4 traioc register in timer mode revised (figure 14.4 tracr register in timer mode deleted, figure 14.5 registers traioc and tramr in timer mode tramr register deleted) 134 14.1.1.1 timer write control during count added figure 14.5 operating example of timer ra when count value is rewritten during count added 135 table 14.3 pulse output mode specifications revised 136 figure 14.6 traioc register in pulse output mode revised (figure 14.6 registers tracr and traioc in pulse output mode tracr register deleted, figure 14.7 tramr register in pulse output mode deleted) 137 table 14.4 event counter mode specifications revised 138 figure 14.7 traioc register in event counter mode revised (figure 14.8 registers tracr and traioc in event counter mode tracr register deleted, figure 14.9 tramr register in event counter mode deleted) 139 table 14.5 pulse width measurement mode specifications revised rev. date description page summary free datasheet http:///
c - 11 revision history r8c/24 group, r8c/25 group hard ware manual 1.00 may 31, 2006 140 figure 14.8 traioc register in pulse width measurement mode revised (figure 14.10 registers tracr and traioc in pulse width measurement mode tracr register deleted, figure 14.11 tramr register in pulse width measurement mode deleted) 141 figure 14.9 operating example of pulse width measurement mode revised 142 table 14.6 pulse period measurem ent mode specifications revised 143 figure 14.10 traioc register in pulse period measurement mode revised (figure 14.13 registers tracr and traioc in pulse period measurement mode tracr register deleted, figure 14.14 tramr register in pulse period measurement mode deleted) 144 figure 14.11 operating example of pulse period measurement mode revised 146 14.2 timer rb; ?the count source fo r timer rb ... and reloading.? added ? timer mode: ... (peripheral function clock ... added figure 14.12 block diagram of timer rb revised 147 figure 14.13 registers trbcr and trbocr revised 148 figure 14.14 registers tr bioc and trbmr revised 149 figure 14.15 registers trbpr e, trbsc, and trbpr revised 150 table 14.7 timer mode specifications revised figure 14.16 trbioc register in timer mode revised (figure 14.20 registers trbioc and trbmr in timer mode trbmr register deleted) 151 14.2.1.1 timer write control during count added 152 figure 14.17 operating example of timer rb when count value is rewritten during count added 153 table 14.8 programmable waveform generation mode specifications revised 154 figure 14.18 trbioc register in programmable waveform generation mode revised (figure 14.20 registers trbioc and trbmr in timer mode trbmr register deleted) figure 14.19 operating example of timer rb in programmable waveform generation mode revised 155 table 14.9 programmable one-shot gener ation mode specifications revised 156 figure 14.20 trbioc register in programmable one-shot generation mode revised (figure 14.23 register s trbioc and trbmr in programmable one- shot generation mode trbmr register deleted) 157 figure 14.21 operating exampl e of programmable one-shot generation mode revised 158 14.2.3.1 selecting one-shot trigger added 159 table 14.10 programmable wait one-shot generation mode specifications revised rev. date description page summary free datasheet http:///
c - 12 revision history r8c/24 group, r8c/25 group hard ware manual 1.00 may 31, 2006 161 figure 14.22 trbioc register in programmable wait one-shot generation mode (figure 14.25 register s trbioc and trbmr in programmable wait one-shot generation mode trbmr register deleted) 162 figure 14.23 operating example of programmable wait one-shot generation mode revised 163 14.2.5 notes on timer rb; ? ? ... timer rb starts counting at th e first ... 1 (during count).? deleted ? ? when the tstop bit in the trbcr register ... immediately stops. ? if the tosst bit or the tossp bit ... also be set to 0 or 1.? added 165 table 14.12 pin functions trdioa0/trdclk(p2_0) revised 167 table 14.20 pin functions int0 (p4_5) revised 179 figure 14.33 trdfcr register in input capture function note2 revised 193 figure 14.47 trdfcr register in outp ut compare function note2 revised 210 figure 14.63 trdfcr register in pwm mode note2 revised 220 table 14.29 reset synchronous pwm mode specifications revised 222 figure 14.75 trdfcr register in reset synchronous pwm mode notes 1 and 3 revised 225 figure 14.78 registers trdsr0 to trdsr1 in reset synchronous pwm mode revised 227 table 14.30 trdgrji register functions in reset synchronous pwm mode revised 233 figure 14.86 trdfcr register in complementary pwm mode notes 1 and 4 revised 239 14.3.9 complementary pwm mode; ?since a value cannot be writte n to ... bfc1, and bfd1.? added 244 table 14.33 specifications of pwm3 mode revised 247 figure 14.98 trdfcr register in pwm3 mode note2 revised 254 table 14.34 trdgrji register functions in pwm3 mode revised, 14.3.10 pwm3 mode; ?registers trdgrc0, ... and bfd1.? added 258 14.3.12.1 trdstr register (i = 0 or 1); ? ? table 14.36 lists the trdioji (j = a, b, c, ... timer rd output.? added 259 14.3.12.6 reset synchronous pwm mode; change procedure (2) revised 14.3.12.7 complementary pwm mode; ?change bits cmd1 to cmd0 in the trdfcr register in the ... ; change procedure: when setting to complementary ... (2) , change procedure: when stopping complementary ... (1) and (2) revised ?do not write to ... ; ?however, set to the trdgrd0, ... bfd1.? added 263 14.3.12.8 pwm3 mode deleted 264 14.4 timer re; ?the count source for timer re ... operations.? added 265 figure 14.112 block diagram of real-time clock mode revised rev. date description page summary free datasheet http:///
c - 13 revision history r8c/24 group, r8c/25 group hard ware manual 1.00 may 31, 2006 287 figure 15.6 registers u0c1 to u1c1, u1sr, and pmr; u0c1 to u1c1 register note2 added 288 table 15.1 clock synchronous serial i/o mode specifications revised 289 15.1 clock synchronous serial i/o mode; ?table 15.3 ... the txd0 pin ...? ?table 15.3 ... the txdi pin ...? revised 294 15.2 clock asynchronous serial i/o (uart) mode; ?table 15.6 ... the txd0 pin ...? ?table 15.6 ... the txdi pin ...? revised 296 figure 15.11 receive timing example in uart mode; ?ri bit? ?ir bit? revised 300 table 16.2 clock synchronous serial i/o with chip select specifications; ? ? ?f1? revised and note2 deleted 304 figure 16.4 ssmr register 307 figure 16.7 ssmr2 register revised 308 figure 16.8 registers sstdr and ssrdr ; sstdr registers note1 deleted 309 16.2.1 transfer clock; ? ? ?f1? revised 314 16.2.5.2 data transmission; ?when setting the mcu is set as a slave device, ... enabled.? deleted 316 figure 16.14 sample flowchart of data transmission (clock synchronous communication mode) note2 deleted 319 16.2.5.4 data transmission/reception; ?when the mcu is set as the slave device, ... enabled.? deleted 320 figure 16.17 sample flowchart of data transmission/reception (clock synchronous communication mode) note2 deleted 322 figure 16.18 initialization in 4-wire bus communication mode revised 323 16.2.6.2 data transmission; ?when the mcu is set as a slave device, ... enabled.? deleted 358 figure 16.47 example of register setting in master receive mode (i 2 c bus interface mode) revised 362 to 375 17. hardware lin; ?sync break? ?synch break? and ?sync field? ?synch field? revised 362 figure 17.1 block diagram of hardware lin revised 364 figure 17.2 lincr register revised 365 figure 17.3 linst register revised 366 figure 17.4 typical operation when sending a header field ?raic? ?traic? revised 367 figure 17.5 example of header field transmission flowchart (1) revised 368 figure 17.6 example of header field transmission flowchart (2) revised 369 17.4.2 slave mode (5) revised figure 17.7 typical operation when receiving a header field revised 370 figure 17.8 example of header field reception flowchart (1) revised 371 figure 17.9 example of header field reception flowchart (2) revised rev. date description page summary free datasheet http:///
c - 14 revision history r8c/24 group, r8c/25 group hard ware manual 1.00 may 31, 2006 372 figure 17.10 example of he ader field reception flowchart (3) revised 373 figure 17.11 typical operation wh en a bus collision is detected; ?raic? ?traic? revised 374 17.5 interrupt requests; ?there are four ... sync break generation completed, ... , and bus collision detection.? ?there are three ... , and bus collision detection.? revised table 17.2 interrupt requests of hardware lin revised 376 table 18.1 performance of a/d converter revised 380 table 18.2 one-shot mode specifications revised 384 figure 18.6 adcon0 register in repeat mode revised 386 18.3 sample and hold; ?... to 28 ad cycles for 8-bit resolution or 33 ad resolution? and ?when performing a/d conversion, ch arge the sampling time.? deleted 387 figure 18.10 internal equivalent circuit of analog input revised 388 18.6 inflow current bypass circuit deleted 18.6 output impedance of sensor under a/d conversion added 389 18.7 notes on a/d converter revised 394 figure 19.4 ofs register note2 revised 395 table 19.3 differences between ew0 mode and ew1 mode revised 397 19.4.2.1 fmr00 bit ?... (including suspend periods) ...? added 399 figure 19.5 fmr0 register note6 added 401 figure 19.7 fmr4 register; notes 2, 3 and 4 revised and note5 added 402 figure 19.8 timing of suspend operation revised 405 19.4.3.1 read array command ?the mcu also enters read array mode after a reset.? added 19.4.3.2 read status register command ?the mcu remains in read status mode ... command is written.? added 406 19.4.3.4 program command; ?when suspend function disabled, ...?, ?when suspend function enabled, the fmr44 bit ... when auto -programming co mpletes.? added figure 19.12 program command (when suspend function disabled) title revised 407 figure 19.13 program command (when suspend function enabled) added 408 19.4.3.5 block erase revised figure 19.14 block erase command (when erase-suspend function disabled) title revised 409 figure 19.15 block erase comman d (when erase-suspend function enabled) revised 410 table 19.5 status register bits revised 413 19.5 standard serial i/o mode revised table 19.7 pin functions (flash memory standard serial i/o mode 2) added 414 table 19.8 pin functions (flash memory standard serial i/o mode 3) revised rev. date description page summary free datasheet http:///
c - 15 revision history r8c/24 group, r8c/25 group hard ware manual 1.00 may 31, 2006 415 figure 19.17 pin connections for standa rd serial i/o mode 3 title revised 416 figure 19.18 pin processing in standard serial i/o mode 2 added, figure 19.19 pin processing in standard serial i/o mode 3 title revised 420 19.7.1.7 reset flash memory deleted 421 table 20.2 recommended operating conditions revised 422 figure 20.1 ports p0 to p4, p6 timin g measurement circuit; title revised 423 table 20.4 flash memory (program rom) electrical characteristics revised 424 table 20.5 flash memory (data flash block a, block b) electrical characteristics revised 425 figure 20.2 time delay until suspend title revised 426 table 20.9 voltage monitor 0 re set electrical characteristics table 20.9 power-on re set circuit, voltage monitor 0 reset electrical characteristics revised table 20.10 power-on reset circuit electrical characteristics (when not using voltage monitor 0 reset) deleted figure 20.3 power-on reset circuit electrical characteristics revised 427 table 20.10 high-spee d on-chip oscillator circuit electrical characteristics revised table 20.11 low-speed on-chip oscillator circuit electrical characteristics revised 434 table 20.16 electrical characteristics (2) [vcc = 5 v] revised 438 table 20.22 electrical characteristics (4) [vcc = 3 v] revised 442 table 20.28 electrical characteristics (6) [vcc = 2.2 v] revised 445 21.1.1 stop mode and wait mode revised and 21.1.4 foco40m deleted 448 21.2.7 entering wait mode after osc illation stop detection interrupt is detected deleted 450 21.3.2 notes on timer rb; ? ? ... timer rb starts counting at th e first ... 1 (during count).? deleted ? ? when the tstop bit in the trbcr register ... immediately stops. ? if the tosst bit or the tossp bit ... also be set to 0 or 1.? added 451 21.3.3.1 trdstr register (i = 0 or 1) revised 452 21.3.3.6 reset synchronous pwm mode; change procedure (2) revised 21.3.3.7 complementary pwm mode; ?change bits cmd1 to cmd0 in the trdfcr register in the ...; change procedure: when setting to complementary ... (2) , change procedure: when stopping complementary ... (1) and (2) revised ?do not write to ...; ?however, set to the trdgrd0, ... bfd1.? added 456 21.3.3.8 pwm3 mode deleted 462 21.6 notes on hardware lin; ?sync break? ?synch break? revised 463 21.7 notes on a/d converter revised 466 21.8.1.7 reset flash memory deleted rev. date description page summary free datasheet http:///
c - 16 revision history r8c/24 group, r8c/25 group hard ware manual 1.00 may 31, 2006 468 22. notes on on-chip debugger; (2) revised 469 appendix 1. package dimensions ?the latest package ... renesas technology website.? added 2.00 nov 01, 2006 all pages ?ptlg0064ja-a (64f0g)? package added y version added factory programming product added 1 1. overview; ?... or a 64-pin molded-plastic flga.? added 2, 3 table 1.1 functions and specific ations for r8c/24 group, table 1.2 functions and specifications for r8c/25 group; package: ?64-pin molded-plastic flga? added 9 figure 1.4 plqp0052ja-a package pin assignments (top view); note3 revised 10 figure 1.5 ptlg0064ja-a package pin assignments added 18 table 4.1 revised 36 figure 6.5 note6 revised 61 table 7.17 revised 62 table 7.19 revised 66 table 7.33, table 7.35 revised 67 table 7.36 revised 78 figure 10.5 note2 added 80 figure 10.8 note6 revised 81 figure 10.9 revised 82 10.2.2 ?adjust the fra1 register so that .... 40 mhz or less.? added 90 figure 10.11 revised 91 figure 10.12 revised 93 figure 10.13 revised 98 10.7.1 revised, 10.7.2 added 123 12.6.3 ?and table 20.18 (vcc = 5v), ... traio input, int1 input.? deleted 127 figure 13.2; watchdog timer control register: after reset ?when read, the content is undefined.? added 140 table 14.4; trao pin function: specification ?or pulse output? added 198 figure 14.49 note2 added 215 figure 14.65 timer rd output control register note2 added 220 figure 14.71 revised 252 figure 14.100 note2 added 262 14.3.12.7 ?do not use the trdgrc0 register in complementary pwm mode.? deleted 291 table 15.1 note2 revised 296 table 15.4 note1 revised rev. date description page summary free datasheet http:///
c - 17 revision history r8c/24 group, r8c/25 group hard ware manual 2.00 nov 01, 2006 298 figure 15.10 revised 306 figure 16.3 note2 revised 337 figure 16.26 note3 revised 344 to 349 figure 16.32, figure 16.33, figure 16.34, figure 16.35, figure 16.36 revised 370 figure 17.5 revised 374 figure 17.9 revised 375 figure 17.10 revised 377 17.4.4 added 378 table 17.2 cause of interrupt ?8? ?6? 384 table 18.2; stop condition: specif ication ?when the adcap .... (software trigger)? added, input pi n: specification ?an8? ?an0? 395 figure 19.1 revised 396 figure 19.2 revised 411 figure 19.13 note3 added 413 figure 19.15 note3 added 416 figure 19.16 revised 425 table 20.1 absolute maximum ratings; note1 added 432 table 20.10; ?v cc = 4.5 v to 5.5 v -20c to p r 85c?, ?v cc = 4.5 v to 5.5 v -40c to p r 85c? added oscillation stability time: condition ?v cc = 5.0 v, topr = 25c? deleted table 5.11; oscillation stability time: condition ?v cc = 5.0 v, topr = 25c? deleted 438 table 20.15; i ih , i il , r pullup condition: ?vcc = 5v? added 439 table 20.16; condition : high-speed on-chip oscillator mode revised 440 table 20.17 added 441 figure 20.8 revised 443 table 20.22; i ih , i il , r pullup condition: ?vcc = 3v? added 444 table 20.23; condition ?increase du ring a/d converter operation? added 445 figure 20.12 revised 448 table 20.29; condition ?increase du ring a/d converter operation? added 449 figure 20.16 revised 475 package dimensions; ?ptlg0064ja-a (64f0g)? added 3.00 feb 29, 2008 ? ?renesas technical update? reflected: tn-16c-a164a/e, tn-16c-a 165a/e, tn-16c-a166a/e, tn-16c-a167a/e 2, 3 table 1.1, table 1.2 clock; ?real-time clock (timer re)? added 5, 7 table 1.3, table 1.4 revised 6, 8 figure 1.2, figure 1.3; rom number ?xxx? added 16, 17 figure 3.1, figure 3.2; ?expanded area? deleted rev. date description page summary free datasheet http:///
c - 18 revision history r8c/24 group, r8c/25 group hard ware manual 3.00 feb 29, 2008 18 table 4.1; ?002ch? added, ?003bh? ?003ch? ?003dh? deleted 27 figure 5.3 revised 27, 128, 401 figure 5.4, figure 13.2, figure 19.4; ?ofs register? revised 28 5.1.1, 5.1.2; ?wait for 1/foco-s 20.? ?wait for 10 s or more.? 29 figure 5.5, figure 5.6 revised 30 5.2, figure 5.7 revised 36 figure 6.5 note6 revised 61, 62 table 7.17, table 7.19 revised 65 table 7.29, table 7.30 revised 70 table 7.48 revised 73 10. ?(with oscillation stop detection function)? deleted 74 figure 10.1 revised 75 figure 10.2 note4 revised 78 figure 10.5 note2 revised 79 figure 10.6 ?fra7 register? added 80 figure 10.8 note6 revised 81 figure 10.9 added 83 10.2.2 revised 88 10.5.1.2, 10.5.1.4 revised 90 table 10.3 revised 92 10.5.2.5, figure 10.13 revised 94 figure 10.14 revised 96 10.6.1 revised 99 10.7.1, 10.7.2 revised 103 12.1.3.1 revised 105 table 12.2 ?reference? revised 115 12.2.1 revised 120 table 12.6 revised, note2 added 124 12.6.4 deleted 125 figure 12.20 note2 revised 133 table 14.1 ?? fc32? deleted 134 figure 14.1 ?tstart? ?tcstf? 138 figure 14.5 ?... to 0 (during count).? ?... to 1 (during count).? 149 14.1.6 revised, ?? when the trapre ...? ?? when the tra ...? added 150 14.2 ?the reload register ...? deleted figure 14.12 revised 153 table 14.15 revised 156 figure 14.17 ?... to 0 (during count).? ?... to 1 (during count).? rev. date description page summary free datasheet http:///
c - 19 revision history r8c/24 group, r8c/25 group hard ware manual 3.00 feb 29, 2008 159 table 14.9 note2 added ?...0 (one-shot stops).? ?...1 (one-shot stops).? ?trbp pin function? ?trbo pin function? 160 figure 14.20 ?... when write, ...? ?... if necessary, ...? 164 table 14.10 note2 added 167 to 170 14.2.5 revised 14.2.5.1, 14.2.5.2, 14 .2.5.3, 14.2.5.4 added 197, 214 table 14.25, table 14.27; ?at the same time as the trdi register ... 0000h? deleted 198, 215 figure 14.47, figure 14 .63; ?trdstr register? revised 201 figure 14.50 ?trdoer1 register? revised 206 figure 14.55 revised 209 figure 14.59 ?of counter clear? deleted 212 figure 14.61 revised 214 table 14.27 revised 220 figure 14.68 revised 227, 251 table 14.29, table 14.33; ?at the same time as the trd0 register ... 0000h? deleted 228 figure 14.76 revised 232 figure 14.80 revised 238 figure 14.86 revised 239 figure 14.87 revised 243 figure 14.91 revised 252 figure 14.98 ?trdstr register? revised 257 figure 14.103 revised 261 figure 14.107 revised 264 14.3.12.1, table 14.36; ?after the count is cleared? deleted 277 figure 14.121 ?00? ?00b? 286 figure 14.130 revised 291 figure 15.4 ?uarti transmit/receive mode register? note2 deleted 293 figure 15.6 ?(b7-b4)? ?(b7-b6)? 300 table 15.5 note2 added 303 table 15.7 revised 304 15.3 revised 308 figure 16.2 note4 deleted 309 figure 16.3 revised, note4 deleted 310 figure 16.4 note2 deleted 311 figure 16.5 note1 deleted 312 figure 16.6 note2, note7 revised 313 figure 16.7 note5 revised rev. date description page summary free datasheet http:///
c - 20 revision history r8c/24 group, r8c/25 group hard ware manual 3.00 feb 29, 2008 314 figure 16.8; sstdr register: note1 deleted, ssrdr register: note2 deleted 328 figure 16.18 revised 334 16.2.8.1 deleted 338 figure 16.24 note6 revised 339 figure 16.25 note5 deleted 340 figure 16.26 note7 deleted 341 figure 16.27 note3 revised 342 figure 16.28 note7 revised 343, 344 figure 16.29, figu re 16.30; note1 deleted 367 16.3.8.1 revised, 16.3.8.2 added 368 figure 17.1 revised 373 figure 17.5 ?... in linst register 0? ?... in linst register 1? 374 figure 17.6 revised 375 figure 17.7 revised 377 figure 17.9 revised 379 figure 17.11 ?scdct? ?bcdct? 380 figure 17.12 revised 385, 388, 391 figure 18.2, figure 18.4, figure 18.6; note4 revised 394 figure 18.10 revised 396 18.7 revised 397 table 19.2 revised 402 table 19.3 revised 403 19.4.1, 19.4.2; ?(sr-es)? ?(sr-sus)? 404 19.4.2.4 ?located outside ... memory.? ?transferred to the ram.? 405 19.4.2.15 revised 406 figure 19.5 note3, note5 revised 408 figure 19.7 note5 revised 410 figure 19.9 revised 411 figure 19.11 revised 413 19.4.3.4 revised 414 figure 19.13 revised 416 figure 19.15 revised 418 table 19.6 ?frm00 register? ?frm0 register? 420 table 19.7 revised 429 table 20.2 note2 revised 435 table 20.10 revised, note4 added 454 21.1.1, 21.1.2 revised rev. date description page summary free datasheet http:///
c - 21 revision history r8c/24 group, r8c/25 group hard ware manual 3.00 feb 29, 2008 455 21.2.4 deleted 456 figure 21.1 note2 revised 458 21.3.1 revised, ?? when the tr apre ...? ?? when the tra ...? added 459 to 462 21.3.2 revised 21.3.2.1, 21.3.2.2, 21 .3.2.3, 21.3.2.4 added 463 21.3.1.1, table 21.1; ?after the count is cleared? deleted 470 figure 21.8 revised 472 21.4 revised 473 2.5.1.1 deleted, 2.5.2. 1 revised, 2.5.2.2 added 475 21.7 revised 482 appendix figure 2.1, appendix figure 2.2 revised 483 appendix figure 3.1 revised rev. date description page summary free datasheet http:///
r8c/24 group, r8c/25 group hardware manual publication data: rev.0.10 jul 27, 2005 rev.3.00 feb 29, 2008 published by: sales strategic planning div. renesas technology corp. ? 2008. renesas technology corp., all rights reserved. printed in japan free datasheet http:///
2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan r8c/24 group, r8c/25 group hardware manual free datasheet http:///

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